Storage state reading circuit and storage state reading method

Abstract

The present invention provides a storage state reading circuit and a storage state reading method. Among them, the storage state reading circuit includes a state measurement terminal, a constant current module, a pre-charge module, and a comparison module. When the pre-charge module receives a pre-charge enable signal, it charges the parasitic capacitance at a third rate, and the third rate is relatively large during at least a part of the charging process; the comparison module outputs a signal based on the voltage of the state measurement terminal; the storage state reading circuit outputs a reading signal based on the output signal of the comparison module. With such a configuration, the charging process during state reading is accelerated, and the problem in the prior art that the waiting time for the charge and discharge process is relatively long and it is difficult to further improve the data reading speed is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a storage state reading circuit and a storage state reading method. Background Art

[0002] A memory stores data through multiple storage cells. Each storage cell has two storage states, namely "0" and "1", and the corresponding cell types are erase cell and program cell, simply referred to as Ecell and Pcell. Different types of cells will exhibit different cell currents of different magnitudes under the same specific bias conditions (the specific bias conditions and the magnitudes of the cell currents are related to the manufacturing process and materials of the cells).

[0003] Under a specific storage cell structure and bias conditions, the Ecell current is very small and can be basically ignored, and the Pcell current exhibits a large current. It should be understood that here it means that the Pcell current is relatively large compared to the Ecell current, but the absolute value of the Pcell current is still small.

[0004] The characteristics of the Ecell current and the Pcell current can be used to design a storage state reading circuit. An exemplary reading circuit is to sense the small signal change on the bit line caused by the different cell currents and then amplify the small signal change to obtain the stored data on the storage cell.

[0005] Since the basic principle of reading is to charge and discharge a capacitor, and because the absolute values of both the Pcell current and the Ecell current are small, the charging and discharging process needs to wait for a relatively long time to complete, which limits the improvement of the data reading speed.

[0006] In summary, there is a problem that the waiting time for the charging and discharging process is relatively long, and it is difficult to further improve the data reading speed. Summary of the Invention

[0007] The purpose of the present invention is to provide a storage state reading circuit and a storage state reading method to solve the problem in the prior art that the waiting time for the charging and discharging process is relatively long and it is difficult to further improve the data reading speed.

[0008] To solve the above technical problems, the present invention provides a storage state reading circuit. The storage state reading circuit includes a state measurement terminal, a constant current module, a pre-charge module, and a comparison module. Among them, the state measurement terminal is used to connect to a storage unit. The storage unit includes a state element and a parasitic capacitance connected in parallel. The state element outputs a first current or a second current according to its own storage state. The output terminal of the constant current module is connected to the state measurement terminal and outputs a negative third current to the state measurement terminal. When only the first current and the third current flow through the state measurement terminal, the parasitic capacitance discharges at a first rate. When only the second current and the third current flow through the state measurement terminal, the parasitic capacitance charges at a second rate. The ratio of the first rate to the second rate is between 0.9 and 1.1. When the pre-charge module receives a pre-charge enable signal, it charges the parasitic capacitance at a third rate, and the ratio of the third rate to the first rate is greater than 5 during at least a part of the charging process. When the voltage of the state measurement terminal is higher than a preset voltage, the comparison module outputs a first level. When the voltage of the state measurement terminal is lower than the preset voltage, the comparison module outputs a second level, and the first level and the second level are opposite. The storage state reading circuit outputs a reading signal based on the output signal of the comparison module.

[0009] Optionally, the storage state reading circuit further includes a cache module. The input terminal of the cache module is connected to the output terminal of the comparison module, and the output terminal of the cache module is configured as the output terminal of the storage state reading circuit.

[0010] Optionally, the absolute value of the third current is configured to be between 0.45 and 0.55 times of a preset current value, and the preset current value is the sum of the theoretical values of the first current and the second current.

[0011] Optionally, the constant current module is a current mirror, and the input terminal of the current mirror is used to obtain a first reference current.

[0012] Optionally, the pre-charge module includes a switching element. The first connection terminal of the switching element is used to connect to a power supply, the second connection terminal of the switching element is connected to the state measurement terminal, and the control terminal of the switching element is used to obtain the pre-charge enable signal.

[0013] Optionally, the comparison module is an operational amplifier. The non-inverting terminal of the operational amplifier is connected to the state measurement terminal, and the inverting terminal of the operational amplifier is used to obtain a reference voltage, and the voltage value of the reference voltage is equal to the preset voltage.

[0014] Optionally, the pre-charge module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and an enable inverter. Among them, the enable inverter is used to obtain the pre-charge enable signal and output an inverted signal; the gate of the first PMOS transistor is connected to the output terminal of the enable inverter, and the drain of the first PMOS transistor is used to connect to the power supply; the gate of the second PMOS transistor is connected to the output terminal of the enable inverter, and the drain of the second PMOS transistor is used to connect to the power supply; the source of the first NMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first NMOS transistor is connected to its own source; the source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor is connected to its own source, and the drain of the second NMOS transistor is used to connect to the ground; the source of the third NMOS transistor is connected to the source of the first PMOS transistor, and the gate of the third NMOS transistor is connected to the source of the second PMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the fourth NMOS transistor is also connected to the state measurement terminal, and the gate of the fourth NMOS transistor is used to obtain the pre-charge enable signal; the source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the second NMOS transistor, and the drain of the fifth NMOS transistor is used to connect to the ground; the pre-charge enable signal is a high-level signal.

[0015] Optionally, the comparison module includes a sixth NMOS transistor and a single-stage common-source amplifier. The gate of the sixth NMOS transistor is connected to the state measurement terminal, the drain of the sixth NMOS transistor is used to connect to the ground, the source of the sixth NMOS transistor is used to obtain a second reference current, the source of the sixth NMOS transistor is connected to the input terminal of the single-stage common-source amplifier, the output terminal of the single-stage common-source amplifier is configured as the output terminal of the comparison module, and the turn-on voltage of the sixth NMOS transistor is equal to the preset voltage.

[0016] To solve the above technical problems, the present invention also provides a method for reading a storage state, including a switching step, a pre-charging step, an amplifying and comparing step, and a reading step that are executed in sequence, where: the switching step is: connecting the above-mentioned storage state reading circuit to the storage unit to be read; the pre-charging step is: the pre-charging module works; the amplifying and comparing step is: the pre-charging module stops working, and only the first current and the third current flow through the state measurement terminal, or only the second current and the third current flow through the state measurement terminal; the reading step is: reading the signal at the output terminal of the storage state reading circuit.

[0017] Optionally, the pre-charging step is that the pre-charging module works and controls the working duration of the pre-charging module, so that the difference between the voltage at the state measurement terminal and the preset voltage at the end of the pre-charging step is within a preset difference range.

[0018] Compared with the prior art, in the storage state reading circuit and the storage state reading method provided by the present invention, the storage state reading circuit includes a state measurement terminal, a constant current module, a pre-charging module, and a comparison module. Among them, the state measurement terminal is used to connect to the storage unit, and the storage unit includes a state element and a parasitic capacitance connected in parallel. The state element outputs a first current or a second current according to its own storage state; the output terminal of the constant current module is connected to the state measurement terminal and outputs a negative third current to the state measurement terminal; when only the first current and the third current flow through the state measurement terminal, the parasitic capacitance discharges at a first rate, and when only the second current and the third current flow through the state measurement terminal, the parasitic capacitance charges at a second rate. The ratio of the first rate to the second rate is between 0.9 and 1.1; when the pre-charging module receives a pre-charging enable signal, it charges the parasitic capacitance at a third rate, and the ratio of the third rate to the first rate is greater than 5 during at least a part of the charging process; when the voltage at the state measurement terminal is higher than the preset voltage, the comparison module outputs a first level; when the voltage at the state measurement terminal is lower than the preset voltage, the comparison module outputs a second level, and the first level and the second level are opposite; the storage state reading circuit outputs a reading signal based on the output signal of the comparison module. With such a configuration, the charging process during state reading is accelerated, and the problem in the prior art that the waiting time for the charging and discharging process is relatively long and it is difficult to further improve the data reading speed is solved. Description of the Drawings

[0019] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0020] Figure 1It is a circuit schematic diagram of a storage state reading circuit according to an embodiment of the present invention;

[0021] Figure 2 It is an operation timing schematic diagram of a storage state reading method according to an embodiment of the present invention;

[0022] Figure 3 It is a circuit schematic diagram of a precharge module according to an embodiment of the present invention;

[0023] Figure 4 It is a circuit schematic diagram of a storage state reading circuit according to another embodiment of the present invention;

[0024] In the drawings:

[0025] 1 - constant current module; 2 - precharge module; 3 - comparison module; 4 - storage cell; 41 - status element; 5 - cache module; 6 - single - stage common - source amplifier. Detailed implementation manners

[0026] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis that each drawing needs to show is different, and sometimes different scales are used.

[0027] As used in the present invention, the singular forms "a", "an", and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. "One end" and "the other end", as well as "proximal end" and "distal end" generally refer to two corresponding parts, which not only include the endpoints. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. In addition, as used in the present invention, when an element is disposed on another element, it generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element, etc. in any orientation, unless otherwise explicitly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] The core idea of the present invention is to provide a storage state reading circuit and a storage state reading method to solve the problem that the waiting time in the charge and discharge process is relatively long in the prior art and it is difficult to further improve the data reading speed.

[0029] The following is a description with reference to the accompanying drawings.

[0030] Please refer to Figures 1 to 4 , wherein, Figure 1 is a circuit schematic diagram of a storage state reading circuit according to an embodiment of the present invention; Figure 2 is an operation timing schematic diagram of a storage state reading method according to an embodiment of the present invention; Figure 3 is a circuit schematic diagram of a pre-charge module according to an embodiment of the present invention; Figure 4 is a circuit schematic diagram of a storage state reading circuit according to another embodiment of the present invention.

[0031] As Figure 1As shown in the figure, this embodiment provides a storage state reading circuit, which includes a state measurement terminal vd1, a constant current module 1, a pre-charging module 2, and a comparison module 3.

[0032] Among them, the state measurement terminal vd1 is used to connect to the storage unit 4. The storage unit 4 includes a state element 41 and a parasitic capacitor C1 connected in parallel. The state element 41 outputs a first current or a second current according to its own storage state. In this embodiment, the first current is the Ecell current, and the second current is the Pcell current. There are two storage states of the state element 41, which are 0 and 1 respectively. When it is 0, the state element 41 outputs the first current, and when it is 1, the state element 41 outputs the second current. The state element 41 also needs to be excited according to specific bias conditions to work, which will not be described in detail in this specification. In the following text, |I1| represents the absolute value of the magnitude of the first current, and |I2| represents the absolute value of the magnitude of the second current.

[0033] The output terminal of the constant current module 1 is connected to the state measurement terminal vd1 and outputs a negative third current to the state measurement terminal vd1. It can be understood that the actual flowing direction of the third current is from the state measurement terminal vd1 and flows into the output terminal of the constant current module 1. In the following text, |I3| represents the absolute value of the magnitude of the third current.

[0034] When only the first current and the third current flow through the state measurement terminal vd1, the parasitic capacitor C1 discharges at a first rate. That is to say, I3 > I1. The amount of electricity maintaining the third current I3 cannot be completely provided by the first current I1. Therefore, the amount of electricity in the parasitic capacitor C1 is also pulled out to maintain the balance of the circuit. So the parasitic capacitor C1 is in a discharging state. The first rate is proportional to (I3 - I1), and the first rate can be represented by (I3 - I1).

[0035] When only the second current and the third current flow through the state measurement terminal vd1, the parasitic capacitor is charged at a second rate. That is to say, I2 > I3. Since the current flowing out is greater than the current flowing into the constant current module, part of the current enters the parasitic capacitor C1, and the parasitic capacitor C1 is in a charging state. The second rate can be represented by (I2 - I3).

[0036] The ratio of the first rate to the second rate is between 0.9 and 1.1. With such a configuration, it is convenient to adjust the reading durations of Ecell and Pcell to be approximately equal, so that the complete data reading duration can be shorter.

[0037] If the storage state reading circuit only includes the state measurement terminal vd1 and the constant current module 1 cooperating with the subsequent judgment circuit, it can actually work because the difference between the first current and the second current will ultimately cause the voltage of the parasitic capacitor C1 to change, that is, the voltage of the state measurement terminal vd1 to change. By analyzing and judging through the subsequent circuit, the state of the state element 41 can be distinguished. However, as introduced in the foregoing content, since the absolute values of I1 and I2 are actually small, it takes a long time for the voltage of vd1 to change to a degree that can be accurately distinguished without misjudgment, thus affecting the overall reading time.

[0038] Therefore, this embodiment further includes the pre-charge module 2. When the pre-charge enable signal EN2 is received, the pre-charge module 2 charges the parasitic capacitor C1 at a third rate. It should be understood that one or more of I1 to I3 may exist simultaneously at this time. However, since the current output by the pre-charge module 2 is large, the existence of I1 to I3 actually does not affect the working result of the pre-charge module 2. The ratio of the third rate to the first rate is greater than 5 during at least a part of the charging process. That is to say, in some embodiments, the third rate is always greater than 5 times the first rate (corresponding to the embodiment shown in Figure 1 ), and in some other embodiments, the charging process is divided into two time periods. In one time period, the third rate is greater than 5 times the first rate, and in the other time period, it is less than (corresponding to the embodiment shown in Figure 4 ). Figure 4 The reason for such a design of the embodiment shown in is described in the subsequent content of this specification. However, whether it is all or part of the charging process, as long as the third rate is greater than 5 times the first rate, the beneficial effect of quickly charging the parasitic capacitor C1 can be obtained.

[0039] When the voltage of the state measurement terminal vd1 is higher than the preset voltage, the comparison module 3 outputs a first level; when the voltage of the state measurement terminal vd1 is lower than the preset voltage, the comparison module 3 outputs a second level, and the first level and the second level are opposite. For example, the first level is a high level and the second level is a low level. When the voltage of the state measurement terminal vd1 is equal to the preset voltage, depending on different implementation methods and cost considerations, the first level or the second level can be output, which does not affect the final result and is not limited here.

[0040] The storage state reading circuit outputs a reading signal based on the output signal of the comparison module 3. It should be understood that the meaning described in this sentence is that due to the different processes and principles of different reading methods, the storage state reading circuit does not necessarily directly output the output signal of the comparison module 3, but also needs to perform some simple transformations or delays before outputting. However, the reading signal output by the storage state reading circuit is essentially determined by the output signal of the comparison module 3.

[0041] With such a configuration, through the pre-charge module 2, the parasitic capacitance C1 can be charged to near the critical state, so that the first current or the second current can quickly change the magnitude relationship between the parasitic capacitance C1 and the preset voltage, accelerating the reading process. Cooperating with the corresponding reading method, the duration of reading a single data can be shortened, thereby accelerating the complete data reading process.

[0042] Here, the influence of the acceleration of the charging process on the waiting duration of the discharging process is discussed. Let's assume that the charging duration is shortened from T1 to T2. Before accelerating the charging process through the pre-charge module 2, it is necessary to wait for a duration of T1 before it can be confirmed whether the current is in the charging state or the discharging state. If judged before the duration of T1 and the voltage is low, there are two possibilities. One is that the current is indeed in the discharging state, so the voltage is low. The other is that the current is actually in the charging state, but the time is not long enough, so the voltage is low. That is to say, no accurate result can be obtained by judging during the duration of T1. After accelerating the charging process through the pre-charge module 2, since the charging time is shortened, only a waiting duration of T2 is required to judge the charging result. If the voltage is low at this time, it can be accurately judged that the current must be in the discharging stage. Therefore, only by accelerating the charging process can the waiting durations of both the charging and discharging processes be shortened simultaneously.

[0043] There are still many details not described in this embodiment. However, for the sake of easy understanding, the corresponding storage state reading method is described first.

[0044] In one embodiment, the storage state reading method includes a switching step, a pre-charging step, an amplifying and comparing step, and a reading step that are executed in sequence. The above steps are driven by different enable signals. Please refer to Figure 2 , Figure 2 shows the waveforms of different enable signals. Among them, RE represents the enable signal for the reading process. When RE is at a high level, a complete reading process is performed. When RE is at a low level, no reading is performed. EN1 represents the enable signal for the switching step. The switching step is at Figure 2In the Chinese text, it is represented by Ta. EN2 is the pre-charge enable signal, and the pre-charge step is represented by Tc. EN3 represents the enable signal of the read step. The read step is represented by To, EN4 represents the enable signal of the amplification and comparison step, and the amplification and comparison step is represented by Tsa.

[0045] Specifically, the switching step is as follows: the above-mentioned storage state reading circuit is connected to the storage unit 4 to be read; the pre-charge step is as follows: the pre-charge module 2 operates; the amplification and comparison step is as follows: the pre-charge module 2 stops operating, and only the first current and the third current flow through the state measurement terminal vd1, or only the second current and the third current flow through the state measurement terminal vd1; the read step is as follows: reading the signal at the output terminal of the storage state reading circuit.

[0046] With such a configuration, within a complete read cycle, the data of one storage unit can be read. Moreover, through the pre-charge step, the total duration of the amplification and comparison step is actually compressed; thus, the effect of a shorter total read cycle duration is obtained.

[0047] Furthermore, in order to improve the read accuracy, in the pre-charge step, the pre-charge module 2 operates, and the operating duration of the pre-charge module is controlled such that the difference between the voltage of the state measurement terminal vd1 at the end of the pre-charge step and the preset voltage is within the preset difference range. In one embodiment, the preset difference range is 90 mV to 110 mV. In another embodiment, the preset difference range can also be 80 mV to 120 mV. It should be understood that in the pre-charge step, the voltage of the state measurement terminal vd1 is always less than the preset voltage.

[0048] In one embodiment, the storage state reading circuit further includes a cache module 5. The input terminal of the cache module 5 is connected to the output terminal of the comparison module 3, and the output terminal of the cache module 5 is configured as the output terminal of the storage state reading circuit. With such a configuration, the signal of the comparison module 3 can be held, facilitating the smooth operation of the read process.

[0049] Preferably, the absolute value of the third current is configured to be between 0.45 and 0.55 times the preset current value, and the preset current value is the sum of the theoretical values of the first current and the second current. With such a configuration, it is convenient for the first rate and the second rate to be close to each other.

[0050] Optionally, the constant current module is a current mirror, and the input terminal of the current mirror is used to obtain the first reference current Iref. The constant current module is composed of NMOS transistors MN1 and MN2, and its specific connection method can be understood by referring to Figure 1 for understanding.

[0051] The pre-charge module 2 includes a switching element. The first connection end of the switching element is used to connect to the power supply VDD. The second connection end of the switching element is connected to the state measurement terminal vd1. The control end of the switching element is used to obtain the pre-charge enable signal EN2. In Figure 1 In the illustrated embodiment, the switching element is a PMOS transistor MP1, and the pre-charge enable signal EN2 is at a low level. In other embodiments, the switching element may also be other elements or circuit structures.

[0052] With this setting, the pre-charge module 2 can achieve the expected effect. However, the duration requirement for the pre-charge enable signal EN2 is relatively strict, or it needs to cooperate with a controller to determine when to stop the pre-charge enable signal EN2 by measuring the voltage of the state measurement terminal vd1 in real time. However, such a solution can also solve the problems raised in the background art and should be regarded as within the protection scope of the technical solution of the present invention.

[0053] The comparison module 3 is an operational amplifier. The non-inverting terminal of the operational amplifier is connected to the state measurement terminal. The inverting terminal of the operational amplifier is used to obtain the reference voltage vref, and the voltage value of the reference voltage is equal to the preset voltage. The operational amplifier also has the function of amplifying the signal to facilitate subsequent circuit signal recognition.

[0054] To solve Figure 1 the problem that the duration requirement for the pre-charge enable signal EN2 in the embodiment of Figure 3 , the pre-charge module 2 can be improved. For example, please refer to Figure 3 , in an embodiment, the pre-charge module includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a first PMOS transistor P1, a second PMOS transistor P2, and an enable inversion element (not shown).

[0055] Among them, the enable inversion element is used to obtain the pre-charge enable signal EN2 and output an inverted signal EN2b. The gate of the first PMOS transistor P1 is connected to the output end of the enable inversion element, and the drain of the first PMOS transistor P1 is used to connect to the power supply VDD.

[0056] The gate of the second PMOS transistor P2 is connected to the output end of the enable inversion element, and the drain of the second PMOS transistor P2 is used to connect to the power supply VDD.

[0057] The source of the first NMOS transistor N1 is connected to the source of the second PMOS transistor P2, and the gate of the first NMOS transistor N1 is connected to its own source.

[0058] The source of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to its own source, and the drain of the second NMOS transistor N2 is grounded.

[0059] The source of the third NMOS transistor N3 is connected to the source of the first PMOS transistor P1, and the gate of the third NMOS transistor N3 is connected to the source of the second PMOS transistor P2.

[0060] The source of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3. The source of the fourth NMOS transistor N4 is also connected to the state measurement terminal vd1, and the gate of the fourth NMOS transistor N4 is used to obtain the pre-charge enable signal EN2.

[0061] The source of the fifth NMOS transistor N5 is connected to the drain of the fourth NMOS transistor N4. The gate of the fifth NMOS transistor N5 is connected to the gate of the second NMOS transistor N2, and the drain of the second NMOS transistor N5 is grounded; the pre-charge enable signal EN2 is a high-level signal.

[0062] When the pre-charge enable signal EN2 is "1", EN2b is "0". The first PMOS transistor P1 and the second PMOS transistor P2 are turned on. VDD charges the node vpre through the second PMOS transistor P2. The first NMOS transistor N1 and the second NMOS transistor N2 form a clamp in the form of a diode connection, resulting in the node vpre voltage being limited near the two NMOS threshold voltages vth, denoted as 2*vth. At the same time, since the node vpre voltage is also the gate voltage of the third NMOS transistor N3, the Vgs of the third NMOS transistor N3 will be greater than the threshold voltage of this transistor and conduct. VDD will charge the state measurement terminal vdl through the first PMOS transistor P1 and the third NMOS transistor N3, causing the voltage of the state measurement terminal vdl to increase. At the same time, since the fifth NMOS transistor N5 and the second NMOS transistor N2 form a current mirror structure, a mirror image forms a current I0 flowing through the fourth NMOS transistor N4 and the fifth NMOS N5 pointing to GND (as Figure 3As shown. As the voltage of the state measurement terminal vdl increases, the Vgs voltage of the third NMOS transistor N3 continuously decreases and finally becomes equal to the mirror current of the fifth NMOS transistor N5 to reach equilibrium, forming a stable DC path. Since the DC current after reaching the steady state is the mirror current, the state measurement terminal vdl will finally stabilize near a voltage less than the NMOS threshold voltage vth with a small difference, within about 100 mV, achieving the final voltage regulation goal.

[0063] In this embodiment, the working rule of the pre-charge module 2 can also be summarized as follows: when the pre-charge module receives a pre-charge enable signal, it charges the parasitic capacitance at a third rate. During a part of the charging process, the ratio of the third rate to the first rate is greater than 5. During another part of the charging process, the third rate decreases as the voltage of the state measurement terminal vd1 increases and decreases to 0 before the voltage of the state measurement terminal vd1 is higher than the preset voltage.

[0064] Since transistors N1, N2, N3 and transistor MN0 in the amplifier (which can be understood by referring to Figure 4 ) are of the same type of transistors, their threshold voltages vth are all equal. When the process parameters fluctuate and cause the vth to change, the voltage value of the state measurement terminal vdl will change with the change of the threshold voltage vth, but the voltage difference between the voltage of the state measurement terminal vdl and the NMOS transistor threshold voltage vth remains basically unchanged. Since the voltage of the state measurement terminal vdl is less than the threshold voltage of the NMOS transistor, the Vgs of transistor MN0 is less than the threshold voltage vth and cannot conduct, and the state of the amplifier output will not change.

[0065] When entering the amplification and comparison stage, if a read operation is performed on Pcell, then the state measurement terminal vdl can be charged by the difference between the second current and the third current, and the '1' data can be correctly read out. If a read operation is performed on Ecell, since the first current is less than the third current, the data remains '0' unchanged, and the data can also be correctly read out.

[0066] Further, please refer to Figure 4, the comparison module includes a sixth NMOS transistor MN0 and a single-stage common-source amplifier 6. The gate of the sixth NMOS transistor MN0 is connected to the state measurement terminal. The drain of the sixth NMOS transistor MN0 is grounded. The source of the sixth NMOS transistor MN0 is used to obtain a second reference current Ibais. The source of the sixth NMOS transistor MN0 is connected to the input terminal of the single-stage common-source amplifier 6. The output terminal of the single-stage common-source amplifier 6 is configured as the output terminal of the comparison module 3. The turn-on voltage of the sixth NMOS transistor is equal to the preset voltage. The single-stage common-source amplifier 6 also has the functions of amplifying signals and stabilizing signals. Replacing the operational amplifier in Figure 1 can, on the one hand, reduce the design difficulty of the amplifier circuit and optimize the area, and on the other hand, change the working state. When the voltage of node vdl is greater than the threshold voltage of NMOS transistor MN0, the state can change, that is, if the voltage of node vdl is greater than the threshold voltage vth, the output state changes from "0" to "1".

[0067] The second reference current Ibais is obtained through two current mirrors, namely, the current mirror composed of NMOS transistors MN1 and MN3 and the current mirror composed of PMOS transistors MP1 and MP0. In Figure 4 , the two current mirrors share a component MN1 and the input current Iref is also the same. In other embodiments, they can be set independently, and the input currents can also be different.

[0068] Figure 4 The storage state reading circuit of the shown embodiment solves the problem of high requirement for signal duration when precharging with a simple switching element. Its advantages are as follows:

[0069] 1) It can improve the reading speed and effectively and reliably ensure that no data misreading occurs.

[0070] 2) It realizes the function with a simple and reliable structure and optimizes part of the area at the same time.

[0071] 3) It is not sensitive to process parameter changes and has high applicability.

[0072] In summary, in the storage state reading circuit and the storage state reading method provided by the present invention, the storage state reading circuit includes a state measurement terminal vd1, a constant current module 1, a pre-charge module 2, and a comparison module 3. Among them, the state measurement terminal vd1 is used to connect to a storage cell 4, and the storage cell 4 includes a state element 41 and a parasitic capacitor C1 connected in parallel. The state element 41 outputs a first current or a second current according to its own storage state; the output terminal of the constant current module 1 is connected to the state measurement terminal vd1 and outputs a negative third current to the state measurement terminal vd1; when only the first current and the third current flow through the state measurement terminal vd1, the parasitic capacitor C1 discharges at a first rate, and when only the second current and the third current flow through the state measurement terminal, the parasitic capacitor C1 charges at a second rate, and the ratio of the first rate to the second rate is between 0.9 and 1.1; when the pre-charge module 2 receives a pre-charge enable signal EN2, it charges the parasitic capacitor C1 at a third rate, and the ratio of the third rate to the first rate is greater than 5 during at least a part of the charging process; when the voltage of the state measurement terminal vd1 is higher than a preset voltage, the comparison module 3 outputs a first level; when the voltage of the state measurement terminal vd1 is lower than the preset voltage, the comparison module 3 outputs a second level, and the first level and the second level are opposite; the storage state reading circuit outputs a reading signal based on the output signal of the comparison module 3. With such a configuration, the charging process during state reading is accelerated, and the problem that the waiting time for the charging and discharging process is relatively long and the data reading speed is difficult to further improve in the prior art is solved.

[0073] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A storage state reading circuit, characterized in that, The storage state reading circuit includes a state measurement terminal, a constant current module, a pre-charge module, and a comparison module. Among them, The state measurement terminal is used to connect to a storage cell. The storage cell includes a state element and a parasitic capacitance connected in parallel. The state element outputs a first current or a second current according to its own storage state. The output terminal of the constant current module is connected to the state measurement terminal and outputs a negative third current to the state measurement terminal. When only the first current and the third current flow through the state measurement terminal, the parasitic capacitance discharges at a first rate. When only the second current and the third current flow through the state measurement terminal, the parasitic capacitance charges at a second rate. The ratio of the first rate to the second rate is between 0.9 and 1.

1. When the pre-charge module receives a pre-charge enable signal, it charges the parasitic capacitance at a third rate. During at least a part of the charging process, the ratio of the third rate to the first rate is greater than 5. When the voltage of the state measurement terminal is higher than a preset voltage, the comparison module outputs a first level. When the voltage of the state measurement terminal is lower than the preset voltage, the comparison module outputs a second level. The first level and the second level are opposite. The storage state reading circuit outputs a reading signal based on the output signal of the comparison module.

2. The storage state reading circuit according to claim 1, wherein The storage state reading circuit further includes a cache module. The input terminal of the cache module is connected to the output terminal of the comparison module. The output terminal of the cache module is configured as the output terminal of the storage state reading circuit.

3. The storage state reading circuit according to claim 1, wherein The absolute value of the third current is configured to be between 0.45 and 0.55 times a preset current value. The preset current value is the sum of the theoretical values of the first current and the second current.

4. The storage state reading circuit according to claim 1, characterized in that, The constant current module is a current mirror. The input terminal of the current mirror is used to obtain a first reference current.

5. The storage state reading circuit according to any one of claims 1 to 4, characterized in that The pre-charge module includes a switching element. The first connection terminal of the switching element is used to connect to a power supply. The second connection terminal of the switching element is connected to the state measurement terminal. The control terminal of the switching element is used to obtain the pre-charge enable signal.

6. The storage state reading circuit according to any one of claims 1 to 4, characterized in that, The comparison module is an operational amplifier. The non-inverting terminal of the operational amplifier is connected to the state measurement terminal. The inverting terminal of the operational amplifier is used to obtain a reference voltage. The voltage value of the reference voltage is equal to the preset voltage.

7. The storage state reading circuit according to any one of claims 1 to 4, characterized in that The pre-charge module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and an enable inversion element. Among them, The enable inversion element is used to obtain the pre-charge enable signal and output an inverted signal. The gate of the first PMOS transistor is connected to the output terminal of the enable inversion element. The drain of the first PMOS transistor is used to connect to a power supply. The gate of the second PMOS transistor is connected to the output terminal of the enable inversion element. The drain of the second PMOS transistor is used to connect to a power supply. The source of the first NMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first NMOS transistor is connected to its own source; The source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor is connected to its own source, and the drain of the second NMOS transistor is grounded; The source of the third NMOS transistor is connected to the source of the first PMOS transistor, and the gate of the third NMOS transistor is connected to the source of the second PMOS transistor; The source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the fourth NMOS transistor is also connected to the status measurement terminal, and the gate of the fourth NMOS transistor is used to obtain the precharge enable signal; The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the second NMOS transistor, and the drain of the fifth NMOS transistor is grounded; The precharge enable signal is a high-level signal.

8. The storage state reading circuit according to claim 7, wherein The comparison module includes a sixth NMOS transistor and a single-stage common-source amplifier. The gate of the sixth NMOS transistor is connected to the status measurement terminal, the drain of the sixth NMOS transistor is grounded, the source of the sixth NMOS transistor is used to obtain a second reference current, the source of the sixth NMOS transistor is connected to the input terminal of the single-stage common-source amplifier, the output terminal of the single-stage common-source amplifier is configured as the output terminal of the comparison module, and the turn-on voltage of the sixth NMOS transistor is equal to the preset voltage.

9. A method for reading a storage state, characterized in that, It includes a switching step, a precharging step, an amplifying and comparing step, and a reading step that are executed sequentially, where: The switching step is: connecting the storage state reading circuit as described in any one of claims 1 to 8 to the storage unit to be read; The precharging step is: the precharging module operates; The amplifying and comparing step is: the precharging module stops operating, and only the first current and the third current flow through the status measurement terminal, or only the second current and the third current flow through the status measurement terminal; The reading step is: reading the signal at the output terminal of the storage state reading circuit.

10. The storage state reading method according to claim 9, wherein The precharging step is that the precharging module operates and controls the operating duration of the precharging module so that the difference between the voltage at the status measurement terminal and the preset voltage at the end of the precharging step is within a preset difference range.

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