Method and device for synthesizing circuit description into logic units in EDA tools

Abstract

The present invention provides a method for synthesizing circuit descriptions into logic units in EDA tools, comprising: splitting the RTLIL-level unit bit by bit into a pair of lookup table units with carry signals or borrow signals; arranging and mapping the pair of lookup table units into a pair of temporary logic units; arranging and merging the pair of temporary logic units into a target logic unit with a cin port for carry or borrow input and a cout port for carry or borrow output; processing the unit-width objects of the RTLIL-level unit from low to high bits, wherein the carry output of the sum of the low bits is the carry input of the high-bit sum; and the borrow input generated by the low-bit difference is the borrow output of the high-bit difference. The synthesis module based on the domestic open source EDA tool can process addition and subtraction more efficiently, which is beneficial to saving chip resources and optimizing the process in the subsequent layout and routing process. The present invention also provides a device with corresponding advantages.

Description

Technical Field

[0001] The present invention belongs to the technical field of EDA tool design, and particularly relates to a method and corresponding device for synthesizing the operations described in a circuit into logic units containing carry chains and borrow chains by a synthesis module in an EDA tool. Background Art

[0002] In recent years, field programmable gate arrays (FPGAs) have been increasingly used in fields such as the internet, communications, image processing, automotive electronics, aerospace, and even military equipment. my country has a huge FPGA market and a growing demand for its development, and EDA software is an essential tool for FPGA design. However, currently widely used EDA tools, such as Quartus and Vivado, are foreign. Developing domestic EDA tools that can achieve the same functionality as foreign software is both necessary and urgent.

[0003] The synthesis module is a crucial component of EDA tools. Without synthesis, subsequent processes cannot proceed. Simply put, "synthesis" involves converting the hardware description language (Verilog) into a netlist file that adapts to the basic circuit unit library of the FPGA chip architecture. Carry and borrow are crucial processes in logic synthesis. For example, in addition operations, the effective use of carry chains can reduce the number of logic cells (LCs), thereby reducing chip area and reducing layout and routing complexity. However, current domestic EDA tools often synthesize more logic cells when synthesizing circuit descriptions into carry chain logic cells. More logic cells lead to a more crowded chip, more complex layout and allocation, and increased routing algorithms and complexity.

[0004] Therefore, it is necessary to study a method for synthesizing circuit descriptions into carry chain and borrow chain logic units in EDA tools, so that domestic EDA tools can be used to realize the synthesis function, thereby further promoting the in-depth development and widespread application of EDA tool design technology. Summary of the Invention

[0005] The present invention aims to solve all or part of the problems in the prior art mentioned above, and provides a method for synthesizing circuit description into logic units in EDA tools.

[0006] The present invention provides a method for synthesizing a circuit description into a logic unit in an EDA tool, comprising: splitting an RTLIL (Register Transfer Level Intermediate Language) level unit bit by bit to convert the unit into a pair of look-up table (LUT) units with a carry signal or a borrow signal; arranging and mapping the pair of look-up table units into a pair of temporary logic units; arranging and merging the pair of temporary logic units into a target logic unit with a cin port for a carry or borrow input and a cout port for a carry or borrow output; wherein the RTLIL level unit is a $add type unit or a $sub type unit; processing unit-width objects of the RTLIL level unit in sequence from low to high bits, wherein a carry output of a low-bit sum is a carry input of a high-bit sum; and a borrow input generated by a low-bit difference is a borrow output of a high-bit difference.

[0007] In the process of converting the RLTIL-level unit into a lookup table unit, the carry and borrow processing of addition and subtraction are synthesized using carry chains and borrow chains, so that the synthesis module of the domestic open source EDA tool is more efficient in processing addition and subtraction. The synthesized netlist result saves more chip resources in the subsequent layout and routing processing, and speeds up the subsequent process processing speed.

[0008] The process of converting the RTLIL level unit into a pair of lookup table units includes: dividing the output signal of the RTLIL level unit into an adder or subtractor bit by bit; creating a pair of three-input lookup table units for each bit operation, and calculating the parameter value of the lookup table unit (LUT).

[0009] The bit-by-bit division into adders or subtractors includes: the lowest bit of the output signal forms a half adder or a half subtractor, and the other bits form a full adder or a full subtractor.

[0010] The method for calculating the parameter value of the lookup table unit includes: recording the two operands of the adder or subtractor as a and b respectively, and recording the corresponding bit widths as m and n respectively; recording the number of bits of the current operation as i, the lowest bit is the zeroth bit, and i is greater than 0; recording the carry input signal or the borrow input signal as cin; comparing m and n: if m=n, starting from i=1, each bit operation result out[i]=a[i]+b[i]+cin[i-1], or out[i]=a[i]-b[i]-cin[i-1]; if m≠n, starting from i being greater than a smaller value, each bit operation result out[i] is the result of the sum operation or the difference operation of a[i] or b[i] and cin[i-1].

[0011] The method for calculating the parameter value of the lookup table unit also includes: when one of the two operands of the adder or the subtractor is a constant, converting the constant into a binary number, and judging the binary number as 0 or 1 bit by bit: before adding or subtracting 1, the operation output is the current position non-constant signal; after adding or subtracting 1, the operation output of one bit is respectively: the operation result of adding the current position non-constant signal and the previous position carry output signal, or the operation result of subtracting the current position non-constant signal from the previous position borrow output signal; or the operation result of adding the current position non-constant signal and the previous position carry output signal and then adding 1, or subtracting the current position non-constant signal from the previous position borrow output signal and then subtracting 1.

[0012] The above method can be used to calculate the parameter values of a multi-input lookup table unit from the output signals of addition and subtraction operations and the truth table corresponding to the logical operation result of 1, that is, to obtain the logical lut_mask value that represents the operation performed by the logic unit. Each bit operation is created as two $lut units, one of which contains the lut_mask of the carry or borrow and its carry or borrow signal; the other contains the lut_mask corresponding to the truth value of the sum or difference of the original bit and its carry or borrow output signal of the difference or sum.

[0013] The method for mapping the pair of lookup table units into a pair of temporary logic units includes: using Yosys open source code to map the lookup table units, defining index parameters and newly added ports; the pair of lookup table units have the same index parameters; the newly added ports include: the cout port; the index parameters include: a parameter identifying whether it is a sum or difference part, or a carry or borrow part, and a group-associated index parameter.

[0014] The method for collating and merging the temporary logical units includes: creating a temporary logical unit mapping structure, abstracting the temporary logical units into instance objects, grouping all the instance objects, and storing them in pairs in a container (i.e., a data set) according to the grouping and associated index parameters. By adding the index parameters, each lookup table unit has an index parameter, and associated lookup table units have the same index. Merging based on the index parameters is efficient and helps ensure the accuracy of the collating and merging results.

[0015] The process of arranging and merging the pair of temporary logic units into a target logic unit includes: a pair of instance objects includes a combination of a sum type temporary unit and a carry type temporary unit, or a combination of a difference type temporary unit and a borrow type temporary unit; traversing the container, extracting the instance objects in pairs according to the index parameter, and processing the pair, including: changing the name of the port (datac) connected to the carry signal in the sum type temporary unit to cin as the cin port, or changing the name of the port connected to the borrow signal in the difference type temporary unit to cin as the cin port; adding a carry result output port in the sum type temporary unit as the cout port and connecting it to the signal of the carry port in the carry type temporary unit; or adding a borrow result output port in the difference type temporary unit as the cout port and connecting it to the signal of the borrow port in the borrow type temporary unit; retaining the sum type temporary unit or the difference type temporary unit as the final target logic unit, and deleting the carry type temporary unit or the borrow type temporary unit accordingly.

[0016] After obtaining the target logic unit, the index parameter is deleted, and a target logic unit description is generated and output to a synthesis netlist file.

[0017] Before converting the RTLIL-level unit into the pair of lookup table units, the following steps are performed: reading a Verilog file; parsing the Verilog file using open source programs Flex and Bison to generate an abstract syntax tree; and generating the RTLIL-level unit from the abstract syntax tree using Yosys open source code.

[0018] Another aspect of the present invention provides an apparatus comprising a storage medium storing a plurality of instructions suitable for being loaded and executed by a processor: a method of the present invention for synthesizing circuit descriptions into logic units in an EDA tool.

[0019] Compared with the prior art, the present invention has the following main beneficial effects:

[0020] 1. The present invention provides a method for synthesizing circuit descriptions into logic units in EDA tools by using carry chains and borrow chains to achieve synthesis. The method is applicable to open-source EDA software, can efficiently perform sum and difference operations, and can greatly reduce the number of logic units, thereby reducing chip utilization, layout, and wiring complexity, and provides a feasible solution for enterprises to save chip resources and optimize processes in subsequent layout and wiring; the parameter values of the lookup table units are calculated through the truth table, which is intuitive and convenient, has high computational efficiency, and improves the overall processing speed; by adding defined index parameters for merging, the processing efficiency and the accuracy of the merged results are further improved.

[0021] 2. The device of the present invention has corresponding advantages because it can implement a method for synthesizing circuit descriptions into logic units in EDA tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention is a flowchart of a method for synthesizing a circuit description into logic units in an EDA tool according to an embodiment of the present invention.

[0023] Figure 2 Schematic diagram of the lookup table types supported in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical solutions in the specific embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0025] In the embodiment of the present invention, the description of the addition and subtraction operation circuit is processed, such as Figure 1 As shown, an exemplary method for synthesizing a circuit description into a logic unit in an EDA tool includes: using the open source programs Flex and Bison to parse a Verilog file to generate an Abstract Syntax Tree (AST), then processing the AST to generate an RTLIL-level $add type addition unit (Yosys open source code); splitting the RTLIL-level unit bit by bit into a pair of lookup table units with carry or borrow signals; arranging and mapping the pair of lookup table units into a pair of temporary logic units; and arranging and merging the pair of temporary logic units into a target logic unit with a carry or borrow input port (cin) and a carry or borrow output port (cout). In some embodiments, after obtaining the target logic unit, the index parameter is deleted, and the target logic unit description is generated and output to the synthesis netlist file. In this embodiment, the unit-width objects of the RTLIL-level unit are processed sequentially from low to high bits, and the carry output of the low-bit sum is the carry input of the high-bit sum; the borrow input generated by the low-bit difference is the borrow output of the high-bit difference. In some embodiments, other open source software may also be used to parse the Verilog file, without limitation.

[0026] The following is a Verilog circuit description of a 32-bit input addition circuit:

[0027] module add_32(a,b,clk,out);

[0028] parameter width=32;

[0029] input [width-1:0] a,b;

[0030] input clk;

[0031] output[width:0] out;

[0032] reg[width:0] out;

[0033] always@(posedge clk) begin

[0034] out<=a+b

[0035] end

[0036] endmodule

[0037] The example $add type unit is as follows:

[0038] cell $add Adder~0

[0039] parameter \Y_WIDTH 33

[0040] parameter \B_WIDTH 32

[0041] parameter \A_WIDTH 32

[0042] parameter \B_SIGNED 0

[0043] parameter \A_SIGNED 0

[0044] connect \Y \out

[0045] connect \B\b

[0046] connect \A\a

[0047] end

[0048] In an embodiment, the process of converting the RTLIL-level unit into a pair of lookup table units includes: dividing the output signal of the RTLIL-level unit into an adder or subtractor bit by bit; creating a pair of three-input lookup table units for each bit operation; and calculating parameter values of the lookup table units. The bit-by-bit division into adders or subtractors includes: forming a half adder or a half subtractor for the least significant bit of the output signal, and forming a full adder or a full subtractor for the remaining bits.

[0049] In this embodiment, during the conversion of the RTL IL-level unit into a lookup table (LUT) unit, addition and subtraction signal processing, addition and subtraction constant processing, and carry and borrow condition determination are performed. Bit-by-bit division into adders or subtractors includes: the lowest bit of the output signal forms a half adder or half subtractor, and the remaining bits form a full adder or full subtractor. Bit-by-bit division creates several processing schemes, including half adders, half subtractors, full adders, and full subtractors, for partial addition, partial subtraction, and single-bit addends, subtrahends, and carry addition and subtraction, to comprehensively process each unit-width object of the RTL IL-level unit. A serial connection is formed between the low-bit carry and borrow output ports and the high-bit carry and borrow input ports, namely, a carry chain and a borrow chain. In the exemplary approach, according to their operation rules, addition and subtraction operations are divided into multiple adders and subtractors bit by bit according to the bit width of their output signals. From the lowest bit to the highest bit, the carry output of the low-bit sum of each adder serves as the carry input for the high-bit addition operation. The subtractor is a borrow input generated by the difference between the low bit and the borrow output generated by the difference between the high bit and the low bit. Each bit is used as a lookup table with three inputs (a bit of the addend, a bit of the augend, and a carry). The types of lookup tables supported in the embodiment are as follows: Figure 2 shown. Figure 2 The figure shows that in arithmetic operations, a four-input LUT is actually composed of two three-input LUTs. The upper 8 bits represent the carry logic, while the lower 8 bits represent the sum logic. Therefore, lut_mask is also divided into two parts. Figure 2 The hexadecimal number AA represents the sum logic result, and the hexadecimal number 34 represents the carry logic result.

[0050] In the example approach, each bit operation creates a pair of lookup table units and calculates their lut_mask. Each logic unit has a lut_mask, which indicates what operation logic the logic unit performs, such as: AND or NOT operation. This embodiment provides an algorithm for calculating lut_mask. The lut_mask value of the multi-input lut can be calculated from the truth table of the input signal and its corresponding logical operation result of 1.

[0051] In some embodiments, both operands of the adder or subtractor are signals, and the calculation formula for processing signal addition and subtraction can be regarded as out=a+b or out=ab. If the sum of the lower bits is greater than 2, 1 is carried to the higher bit. For subtraction, when the lower bit is insufficient for subtraction, 1 is borrowed from the higher bit. Therefore, a carry chain and a borrow chain are generated to establish the operation relationship between the high and low bits. For the lowest bits, i.e., a[0] and b[0], there is no carry or borrow from the lower bits, so a half adder and a half subtractor are formed for the lowest bits. The truth tables of the examples are shown in Tables 1 and 2 respectively:

[0052] Table 1. Half adder truth table

[0053]

[0054] Table 2. Truth table of half subtractor

[0055]

[0056] In the example truth table, the sum and sub columns represent the results of the bitwise operation, and the cout column represents the carry or borrow after the operation. The bit widths of a and b in the example are denoted by m and n, respectively. The current bit of the operation is denoted by i, with the lowest bit being bit zero, and i greater than 0. The previous carry or borrow input signal is denoted by cin. In the example, if m = n, starting from i = 1, the result of each bit operation, out[i] = a[i] + b[i] + cin[i-1], or out[i] = a[i] - b[i] - cin[i-1]. That is, starting from bit 1, the calculation for each bit is out = a + b + cin, or out = ab - cin. Addition and subtraction with carry and borrow are represented by full adders and full subtractors, respectively, as shown in Tables 3 and 4 below.

[0057] Table 3. Full adder truth table

[0058]

[0059] Table 4. Full subtractor truth table

[0060]

[0061] If m ≠ n, starting with i being greater than the smaller value, each subsequent result, out[i], is the sum or difference of a[i] or b[i] with cin[i-1]. For this example, assume m > n, m = 10, and n = 8. The expression for bits 1 through 7 is: out = a + b + cin. Continuing with higher bits, signal b has no value, so the expression becomes: out = a + cin. The same applies to subtraction: out = a - cin.

[0062] In some other embodiments, one of the two operands of the adder or subtractor is a signal, and the other is a constant. Taking the decimal number 20 as an example, the calculation formulas for the addition and subtraction operations of the signal and the constant are out=a+20 and out=a-20. First, the decimal number 20 is converted into a binary number of 10100. The binary number is judged as 0 or 1 bit by bit: before adding or subtracting 1, the operation output is the current position non-constant signal; after adding or subtracting 1, the operation output of one bit is the result of the sum or difference of the current position non-constant signal and pre_cin, or the result of the sum or difference of the current position non-constant signal and pre_cin plus 1 or minus 1. In the example case, for the lowest bit out[0]=a[0]+0, that is, out[0]=a[0]. The first bit, out [1] = a [1]. Binary addition and subtraction will only change when 1 is encountered. After encountering 1, out [2] = a [2] + 1. Adding or subtracting 1 to a binary number is the inversion of that bit, as follows: 0 + 1 = 1, 1 + 1 = 0 and carry to the higher bit. 0 - 1 = 1 and borrow from the higher bit, 1 - 1 = 0. out [2] = ~ a [2]. In the addition or subtraction of 1, a carry or borrow will be generated. When continuing to calculate to the higher bit, the carry or borrow signal must be added. out [3] = a [3] - (borrow from the 2nd bit) cin, out [4] = a [4] - cin (borrow from the 3rd bit) + 1 until each bit of the signal a [i] is processed. For the addition operation, you can refer to it accordingly.

[0063] The pseudo code for implementing the above signal addition and subtraction operations is as follows:

[0064] int maxInputWidth = max(in_width_a, in_width_b);

[0065] int minInputWidth = min(in_width_a, in_width_b);

[0066] Singal pre_cin;

[0067] for (int i=0; i <maxInputWidth; i++)

[0068] {

[0069] if(i==0)

[0070] pre_cin=half_adder(in_a[i], in_b[i],out[i], isAdd);

[0071] else {

[0072] if (i <minInputWidth)

[0073] pre_cin=full_adder(in_a[i],in_b[i],cin,out[i], isAdd);

[0074] else

[0075] pre_cin=part_adder(in_max[i],cin,out[i], isAdd);

[0076] }

[0077] }

[0078] The pseudocode in the example above demonstrates that bit-by-bit processing is performed from lowest to highest. As described above for the adder and subtractor, the lowest bit (bit 0) is processed using half-addition and half-subtraction logic. The remaining bits are processed using full addition and full subtraction, as low-order bits can generate carries. If the in_a and in_b signals have different widths (e.g., in_a_width > in_b_width), after looping through the highest bit of in_b, partial addition and subtraction are used: the in_a signal is added or subtracted with pre_cin (the previous carry output signal).

[0079] The pseudo code for implementing the above signal and constant addition and subtraction operations is as follows:

[0080] Singal pre_cin;

[0081] bool hasAddOne;

[0082] Singal in_a; / / input signal

[0083] Singal in_const; / / Input constant

[0084] for (int i=0; i <width_a; i++)

[0085] {

[0086] if(!hasAddOne&&in_const[i] ==0)

[0087] out[i] = in_a[i];

[0088] else if (!hasAddOne&&in_const[i] ==1) / / first add or sub 1

[0089] {

[0090] out[i]=~in_a[i];

[0091] pre_cin= out[i]+1;

[0092] }

[0093] else if (hasAddOne&&in_const[i] ==0)

[0094] {

[0095] pre_cin= addConst0(in_a[i],pre_cin,out[i],isAdd);

[0096] }

[0097] else{

[0098] pre_cin=addConst1(in_a[i],pre_cin,out[i],isAdd);

[0099] }

[0100] }

[0101] In this example, the constant is checked for 0 or 1 bit by bit. Before adding or subtracting 1, the out output is the signal in_a. However, after adding or subtracting 1, a carry or borrow occurs, causing subsequent high-bit operations to require in_a + pre_cin + 0 or in_a + pre_cin + 1. Subtraction is in_a - pre_cin - 1 or in_a - pre_cin - 1. Adding or subtracting 0 can ignore the 0.

[0102] The truth table calculated for lut_mask in this embodiment is shown in Table 5 below.

[0103] Table 5. Truth table calculated for lut_mask

[0104]

[0105] An example of a portion of the lookup table unit generated in this embodiment is as follows:

[0106] cell $lut $auto$addmap.cc:76:make_lut$65

[0107] parameter \WIDTH 3

[0108] parameter\LUT_PART "Adder0~Sum"

[0109] parameter\LUT_INDEX 31

[0110] parameter\LUT 8'10010110

[0111] connect\Y \ out

[31]

[0112] connect\A { \~|add$add32.v:6$1|_MERGE_~COUT~~30 \b

[31] \a

[31] }

[0113] end

[0114] cell $lut $auto$addmap.cc:76:make_lut$64

[0115] parameter \WIDTH 3

[0116] parameter\LUT_PART "Adder0~Cout"

[0117] parameter\LUT_INDEX 31

[0118] parameter\LUT 8'11101000

[0119] connect\Y \ ~|add$add32.v:6$1|_MERGE_~COUT~~31

[0120] connect\|A{ \~|add$add32.v:6$1|_MERGE_~COUT~~30 \b

[31] \a

[31] }

[0121] end

[0122] The description of the lookup table $lut in the example, each LUT_INDEX corresponds to a pair of $lut units, and the parameter WIDTH indicates that it is a three-input lookup table. Figure 2The characteristics of the four-input LUT in the example. Each bit is processed into a sum (sum result) part and a cout (carry result) part. In the example, a __MERGE__~COUT connection signal is created for each cout part as its carry signal. After each bit is processed, the carry signal is returned to provide the cin signal as the input for the next high bit. Each $lut unit (i.e., lookup table unit) in the generated lookup table unit has a LUT parameter. The value of this LUT parameter is calculated by the lut_mask calculation code through the truth table in Table 5. In this embodiment, the parameter LUT_PART stores index information to prepare for subsequent merging processing. The parameter LUT_PART identifies whether it is the sum / difference part or the carry / borrow part; the parameter LUT_INDEX is the group association index. In this embodiment, lut_mask is derived from the truth table. Each bit is divided into two $lut units, one containing the carry / borrow lut_mask and its cout signal. A lut_mask containing the true values of the local summation and difference, along with its difference and summation comb_out signals, has the same index in pairs, enabling fast and accurate merging via indexing. Using a truth table to calculate the lut_mask value is intuitive and versatile, allowing calculations not only for addition and subtraction but also for other logic operations, improving the flexibility and scalability of the entire synthesis method.

[0123] In this embodiment, a method for mapping a pair of lookup table units into a pair of temporary logic units includes: mapping the lookup table units using Yosys open source code, defining index parameters and newly added ports, wherein the paired lookup table units have the same index parameters; the newly added ports include a cout port connected to a carry signal or a borrow signal; and the index parameters include a parameter indicating whether the sum or difference part, or the carry or borrow part, and a group-associated index parameter. In some embodiments, Yosys is not used, and other open source EDA software for integrated circuit design is used, without limitation.

[0124] The temporary logical cell is generated after mapping using Yosys open source code. The mapping requires the input file cell_map.v, as shown in the following example:

[0125] cell \lcell_comb $auto$addmap.cc:76:make_lut$64

[0126] parameter \lut_part “Adder0~Cout”

[0127] parameter \lut_index 31

[0128] parameter \operation_mode “normal”

[0129] parameter \sum_lutc_input “datac”

[0130] parameter \lut_mask 16’1110100011101000

[0131] connect \datac \~|add$add32.v:6$1|_MERGE_~COUT~~30

[0132] connect \datab \b

[31]

[0133] connect \dataa \a

[31]

[0134] connect \combout \~|add$add32.v;6$1_MERGE_~COUT~~31

[0135] end

[0136] cell \lcell_comb $auto$addmap.cc:76:make_lut$65

[0137] parameter \lut_part “Adder0~Sum”

[0138] parameter \lut_index 31

[0139] parameter \operation_mode “normal”

[0140] parameter \sum_lutc_input “datac”

[0141] parameter \lut_mask 16’1001011010010110

[0142] connect \datac \~|add$add32.v:6$1|_MERGE_~COUT~~30

[0143] connect \datab \b

[31]

[0144] connect \dataa \a

[31]

[0145] connect \combout \ out

[31]

[0146] end

[0147] The example modifies the definition of $lut, adding the parameters lut_index and lut_part. The library definition for the required temporary logic cell, \stratix_lcell_comb, is added to cell_sims.v, along with the required ports and parameter definitions. Each $lut lookup table cell is mapped to a \stratix_lcell_comb temporary logic cell. The lut_mask in the temporary logic cell is a 16-bit binary string, representing the result of multiplying the 8-bit LUT parameter in $lut by 2. The datac port is connected to the carry signal.

[0148] The temporary unit parsing structure used when collating and merging temporary logical units is as follows:

[0149] struct LCellComb{

[0150] CellGroup; / / Which $add / $sub is the record converted from?

[0151] PartType; / / The record is Sum, Cout part

[0152] SelfPtr; / / Point to the temporary logical unit

[0153] Index; / / Identify the index number of the temporary logical unit

[0154] };

[0155] In this embodiment, the method for arranging and merging temporary logical units includes: parsing parameter information in each temporary unit into the structure, abstracting it into a structure (instance) object, grouping these instance objects, and storing them in pairs into a container according to index.

[0156] In this embodiment, each pair of temporary logic unit instance objects includes a combination of a sum or difference type temporary unit and a carry or borrow type temporary unit. The container is traversed, and the temporary logic unit instance objects are retrieved in pairs according to the index parameter for processing. Example methods include:

[0157] The name of the port connected to the carry signal datac in the Sum-type temporary unit is changed to cin, while the signal connected to this port remains unchanged. A carry result output port cout is added to the Sum-type temporary unit and connected to the carry port cout signal in the Cout-type temporary unit. The Sum-type temporary unit is retained as the final target logic unit, and the Cout-type temporary unit is deleted. Some embodiments handle borrow situations, which can be understood accordingly and are not limiting.

[0158] The target logical unit description generated by the final processing in this embodiment is as follows:

[0159] stratix_lcell_comb \$auto$addmap.cc:76:make_lut$65(

[0160] .cin(\~|add$add32.v:6$1|_MERGE_~COUT~~30 ),

[0161] .combout(out

[31] ),

[0162] .cout(\~|add$add32.v:6$1|_MERGE_~COUT~~31 ),

[0163] .dataa(a

[31] ),

[0164] .datab(b

[31] ), );

[0166] defparam \$auto$addmap.cc:76:make_lut$65 .lut_mask = "9617";

[0167] defparam \$auto$addmap.cc:76:make_lut$65 .operation mode = "arithmetic";

[0168] defparam \$auto$addmap.cc:76:make_lut$65 .sum_lutc_input = “cin”;

[0169] This example traverses the container, extracting pairs of temporary unit objects pointed to by SelfPtr according to their index numbers for processing. Each pair of temporary unit objects contains a pair of PartTypes: Sum and Cout. The signal connected to the datac port is a carry signal, so the datac port description in the Sum-type temporary logic unit is replaced with the cin port. The comb_out port in the Cout-type temporary logic unit is connected to the carry signal from the current bit to the high bit. Therefore, a new port, cout, is added to the Sum-type temporary logic unit and connected to the carry signal in the Cout-type unit. Each of the two temporary units has a set of lut_masks, and the lut_masks in this pair of temporary units should be consolidated. In this example, the first 8 bits of each are taken to form a new 16-bit lut_mask, which serves as the lut_mask for the Sum-type temporary unit. At this point, the contents of the Cout-type temporary unit have been replaced, leaving the Sum-type temporary unit as the final target logical unit. The Cout-type temporary unit is then deleted. In this example, the target logical unit in the target unit library lacks the lut_index and lut_part parameters, so it is deleted. Finally, the target logic cell description is generated, which is adapted to the target logic cell library required by the FPGA chip. These results are formatted and output as a synthesis result netlist file. The target logic cell library definition of the example is as follows:

[0170] / *stratix_lcell_comb this is 4-lut input* /

[0171] module stratix_lcell_comb(clk, dataa, datab, datac, acir, aload, ena,cin, cin0, cin1,inverta, regcascin, devcirn, devpor, combout, regout, cout,cout0, cout1);

[0172] parameter operation_mod = “normal”;

[0173] parameter synch_mode = “off”;

[0174] parameter register_cascade_mode = “off”;

[0175] parameter sum_lutc_input = “datac”;

[0176] parameter lut_mask = “ffff”;

[0177] parameter power_up = “low”;

[0178] parameter cin_used = “false”;

[0179] parameter cin0_used = “false”;

[0180] parameter cin1_used = “false”;

[0181] parameter output_mode = “reg and comb”;

[0182] parameter lpum_type = “stratix_lcell”;

[0183] parameter x_on_vioiation = “on”;

[0184] parameter operation_mode= “normal”;

[0185] / / INPUT PORTS

[0186] input dataa;

[0187] input datab;

[0188] input datac;

[0189] input datad;

[0190] input clk;

[0191] input acir;

[0192] input aload;

[0193] input ena;

[0194] input cin;

[0195] input cin0;

[0196] input cin1;

[0197] input inverta;

[0198] input regcascin;

[0199] input devcirn;

[0200] input devpor ;

[0201] / / OUTPUT PORTS

[0202] output combout;

[0203] output regout;

[0204] output cout;

[0205] output cout0;

[0206] output cout1;

[0207] endmodule

[0208] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

Claims

1. A method for synthesizing a circuit description into logic units in an EDA tool, characterized by: include: Split the RTLIL level unit bit by bit and convert it into a pair of lookup table units with carry signal or borrow signal; Arrange and map the pair of lookup table units into a pair of temporary logic units; Arrange and merge the pair of temporary logic units into a target logic unit with a cin port for carry or borrow input and a cout port for carry or borrow output; Among them, the RTLIL-level unit is an $add type unit or a $sub type unit; the unit width object of the RTLIL-level unit is processed in sequence from low to high, and the carry output of the sum of the low bits is the carry input of the high-bit summation; the borrow input generated by the low-bit difference is the borrow output of the high-bit difference.

2. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 1, wherein: The process of converting the RTLIL level unit into a pair of lookup table units includes: dividing the output signal of the RTLIL level unit into an adder or subtractor bit by bit; creating a pair of three-input lookup table units for each bit operation, and calculating the parameter value of the lookup table unit.

3. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 2, wherein: The bit-by-bit division into adders or subtractors includes: the lowest bit of the output signal forms a half adder or a half subtractor, and the other bits form a full adder or a full subtractor.

4. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 3, wherein: The method for calculating the parameter value of the lookup table unit includes: The two operands of the adder or subtractor are denoted as a and b, and the corresponding bit widths are denoted as m and n respectively; The number of bits currently being operated is recorded as i, the lowest bit is the zeroth bit, and i is greater than 0; the carry input signal or the borrow input signal is recorded as cin; Compare m and n: If m=n, starting from i=1, the result of each operation is out[i]=a[i]+b[i]+cin[i-1], or out[i]=a[i]-b[i]-cin[i-1]; If m≠n, starting from the value where i is greater than the smaller value, each subsequent operation result out[i] is the result of the sum or difference operation of a[i] or b[i] and cin[i-1].

5. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 3, wherein: The method for calculating the parameter value of the lookup table unit further includes: When one of the two operands of the adder or the subtractor is a constant, the constant is converted into a binary number, and the binary number is judged as 0 or 1 bit by bit: Before adding or subtracting 1, the operation output is the local non-constant signal; After adding or subtracting 1, the corresponding outputs of the operation are: The result of the sum of the current position's non-constant signal and the previous position's carry output signal, or the result of the difference between the current position's non-constant signal and the previous position's borrow output signal; Or it is the result of adding 1 to the sum of the current position non-constant signal and the previous position carry output signal, or subtracting 1 from the previous position borrow output signal.

6. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 1, wherein: The method for mapping the pair of lookup table units into a pair of temporary logic units includes: The lookup table unit is mapped and processed using Yosys open source code to define index parameters and newly added ports; the pair of lookup table units have the same index parameters; The newly added ports include: the cout port; The index parameters include: a parameter for identifying whether it is a sum or difference part, or a carry or borrow part, and a group association index parameter.

7. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 1, wherein: The method for arranging and merging the temporary logical units includes: A temporary logic unit mapping structure is created, the temporary logic unit is abstracted into an instance object, all the instance objects are grouped, and the instance objects are stored in pairs in a container according to the group-associated index parameters.

8. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 7, wherein: The process of arranging and merging the pair of temporary logical units into a target logical unit includes: A pair of the instance objects includes a combination of a sum type temporary unit and a carry type temporary unit, or a combination of a difference type temporary unit and a borrow type temporary unit; traversing the container, taking out the instance objects in pairs according to the index parameter for processing, including: The port name connected to the carry signal in the temporary unit of the sum type is changed to cin as the cin port, or the port name connected to the borrow signal in the temporary unit of the difference type is changed to cin as the cin port; Adding a carry result output port in the sum type temporary unit as the cout port and connecting it to the signal of the carry port in the carry type temporary unit; or adding a borrow result output port in the difference type temporary unit as the cout port and connecting it to the signal of the borrow port in the borrow type temporary unit; The sum-type temporary unit or the difference-type temporary unit is retained as the final target logic unit, and the carry-type temporary unit or the borrow-type temporary unit is deleted accordingly.

9. The method for synthesizing a circuit description into logic units in an EDA tool according to claim 7, wherein: After obtaining the target logic unit, the index parameter is deleted, and a target logic unit description is generated and output to a synthesis netlist file.

10. The method for synthesizing a circuit description into logic units in an EDA tool according to any one of claims 1 to 9, wherein: Before converting the RTLIL level unit into the pair of lookup table units, the following steps are performed: reading a Verilog file; parsing the Verilog file using open source programs Flex and Bison to generate an abstract syntax tree; The RTL IL level unit is generated from the abstract syntax tree using Yosys open source code.

11. A device, characterized in that: It includes a storage medium storing a plurality of instructions, wherein the instructions are suitable for being loaded and executed by a processor: the method for synthesizing a circuit description into a logic unit in an EDA tool as described in any one of claims 1 to 9.

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