A RISC-V core based on a complex instruction set and its AI processor

Abstract

This disclosure reveals a RISC-V core based on a complex instruction set (CISC) architecture. The key feature is that the CISC-V core serves as the control core for data loading and layer-by-layer computation in a neural network accelerator. Simultaneously, under the control of the RISC-V core, the input and output data of the network are rearranged according to the hardware storage format. This disclosure improves the computational efficiency of FPGA hardware for neural networks, thereby enabling the further implementation of an FPGA neural network accelerator based on RISC-V scheduling.

Description

Technical Field

[0001] This disclosure pertains to the fields of processor and computing technology, and particularly relates to a RISC-V core based on a complex instruction set and its AI processor. Background Technology

[0002] Choosing the right computing platform is crucial for neural network-based applications. Typical CPU platforms have a computing power of approximately 10-100 GFLOPs / s, but their energy efficiency is usually below 1 GFLOP / J. Therefore, CPU platforms cannot meet the high-performance requirements of cloud applications or the low-power requirements of mobile devices. GPU platforms, on the other hand, can achieve peak computing power of 10 TOP / s, and frameworks like Caffe and TensorFlow provide interfaces for GPU acceleration, making them ideal for high-performance applications; however, their energy efficiency is relatively low. FPGA platforms, compared to CPUs and GPUs, offer significantly higher energy efficiency, greater flexibility, and lower cost and shorter development cycle compared to ASIC implementations.

[0003] However, FPGA-based neural network acceleration also faces some challenges:

[0004] (1) Compared to GPUs, FPGA platforms typically have limited storage space, I / O bandwidth, and computing resources;

[0005] (2) At present, the operating frequency of most FPGA platforms is usually between 100-300MHz, which is far lower than the operating frequency of CPU or GPU platforms;

[0006] (3) The deployment of neural network algorithms on FPGA is much more difficult than on CPU or GPU platforms.

[0007] Therefore, a simple deployment design cannot achieve high energy efficiency and high performance; optimization is required in various aspects such as storage, architecture, and data pathways. Summary of the Invention

[0008] In view of this, the present disclosure provides a RISC-V core based on a complex instruction set, characterized in that:

[0009] The RISC-V core, based on the complex instruction set (CISC), serves as the control core for data loading and layer-by-layer computation in neural network accelerators. Simultaneously, within the control system of the RISC-V core, the network's input and output data are rearranged according to the hardware storage format.

[0010] Preferred,

[0011] The storage format is used to implement the rearrangement of the organization format in data storage by FM, and needs to meet the following conditions: the format has good locality, can improve the utilization of data in the cache, and improve data transmission bandwidth and computing performance.

[0012] Preferred,

[0013] For example, the rearrangement specifically includes the following steps:

[0014] If each convolution requires m points and n channels of data, then during rearrangement:

[0015] In the first column, first arrange the m*n numbers involved from the first point to the mth point from bottom to top;

[0016] Furthermore, if the convolution stride is k, then when rearranging from left to right to the second column: the data of the n channels of the (k+1)th point are first arranged from the bottom; then, the (k+2)th point is arranged sequentially from bottom to top, all the way up to the (k+m)th point;

[0017] Furthermore, when rearranging to the (i+1)th column, the data from the n channels of the i*k+1, i*k+2, ..., i*k+m points are arranged sequentially from bottom to top.

[0018] Preferred,

[0019] If each convolution requires N data points, where N corresponds to the computational parallelism of the neural network accelerator, then when N is greater than m*n channels of data, each column from the first column to the second-to-last column can be padded with N-(m*n) zeros.

[0020] Preferred,

[0021] For the last column, add NM zeros based on the actual number M of channel data in the last column.

[0022] Furthermore, this disclosure also reveals an FPGA neural network accelerator based on RISC-V scheduling, characterized in that:

[0023] The neural network accelerator includes the RISC-V core described above.

[0024] Preferred,

[0025] The neural network accelerator includes a control layer, a computation layer, and a storage layer;

[0026] The control layer includes a CPU control core, a data memory, and a code memory;

[0027] The computation layer includes a convolution calculation core, a point-by-point processing operation core, and a data format conversion core;

[0028] The storage layer includes a BRAM storage area for feature maps, a BRAM storage area for parameters, a data storage control module, and a DDR storage area.

[0029] Preferred,

[0030] The DDR storage area stores all feature parameters of a deep neural network, the input image, the output result, and the feature map data of the intermediate layers.

[0031] The BRAM storage area uses swap-in / swap-out rules to store the feature map and parameter information required for the current calculation in the BRAM storage area of ​​the feature map and the BRAM storage area of ​​the parameters. Based on the different characteristics of the data, the BRAM area stores the feature map, the weight portion of the network parameters, and the bias portion of the network parameters in different locations. The feature map requires bidirectional operations from BRAM to DDR, while the network parameters only need to be loaded from the DDR storage area to the corresponding BRAM storage area. The data bit width of the bias portion is lower than that of the weight portion, so it is also stored separately.

[0032] In this way, the utilization of FPGA internal wiring resources is significantly reduced through refined data regional management.

[0033] Preferred,

[0034] For example, the data format conversion core is used to convert HWC format to another format; for example, the other format is HWC88 format, etc.

[0035] Preferred,

[0036] The neural network accelerator uses CISC instructions to configure parameters and control and schedule neural network computations.

[0037] VSCALE writes the parameter configuration to the DISP module through the Regmap Mgr module. The DISP module is responsible for decoupling all parameters and control instructions and sending them to the IQ queue. The IQ queue then sends them to the corresponding execution control module, which then parses and calls the corresponding computation unit to complete the calculation.

[0038] The Retire module is responsible for retiring the corresponding CISC commands, thereby enabling VSCALE to control and issue new parameters.

[0039] The Score Board is used to record all CISC instructions, thereby enabling corresponding decoupling processing.

[0040] Preferred,

[0041] The MCU uses a 32-inch RISC-V core to configure the parameters of the neural network;

[0042] Block Memory uses Mtx Reg a / zero, Mtx Reg b, Mtx Reg c, Br Reg b, and Br Reg c to store image data, weights, and BIAS parameters;

[0043] MPU and VPU are designed as independent computing modules, and the corresponding MPU_ctrl and VPU_ctrl modules are used for control, scheduling and computing.

[0044] The feature map transformation Ftrans and data transformation Dtrans modules are performed using the VPUTY module, and VPUTY_ctrl is used for control and scheduling accordingly.

[0045] The Load_MtxReg_ctrl module is mainly responsible for reading image, weight and BIAS operation instructions from DDR;

[0046] The Save_MtxReg_ctrl module mainly performs the operation instructions for writing data from Block Memory to DDR;

[0047] The DDR arbiter completes the multi-channel data read and write scheduling control;

[0048] When performing neural network acceleration processing on an image, the image is first written to DDR, and then the RISC-V core is started to perform scheduled computation. Under the scheduling of the RISC-V core, the MPU, VPU, and VPUTY work synchronously or asynchronously to complete the computation of an image. Finally, post-processing is performed to obtain the required computation results.

[0049] Preferred,

[0050] The hardware storage format is HWC88.

[0051] Preferred,

[0052] The HWC88 storage format is specifically as follows:

[0053] Divide a row or a portion of a row of FM data into 8 blocks. Place the data of the same channel group at the same position in each block at the same memory address, prioritizing the storage of all channels of the same pixel in each block.

[0054] Preferred,

[0055] FM uses the HWC88 format for convolution operations, specifically by dividing the previous row of FM data into 8 equal blocks to obtain 8 parallel points, and multiplying the data of the same position and channel group in each block with the corresponding channel of the convolution kernel.

[0056] Therefore, this disclosure reveals a RISC-V core based on a complex instruction set (CISC) that serves as the control core for loading neural network data and performing calculations at each layer. It also reassembles network input and output data according to a hardware storage format, improving the computational efficiency of the FPGA hardware for neural networks by increasing the reusability of local data and the utilization of cache data. This enables a RISC-V-based FPGA neural network accelerator (hereinafter referred to as HiPU). Furthermore, this RISC-V core can also serve as the control and scheduling core for a general-purpose processor. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of image convolution calculation decomposition in existing technology;

[0058] Figures 1A to 1C This is a single-row channel rearrangement diagram in one embodiment of this disclosure;

[0059] Figure 1D This is a schematic diagram of channel rearrangement at 80 points in one embodiment of this disclosure;

[0060] Figure 2A This is a schematic diagram of a neural network accelerator structure in one embodiment of this disclosure;

[0061] Figure 2A-1 This is a schematic diagram of the partitioning of the storage layer of a neural network accelerator in one embodiment of this disclosure;

[0062] Figure 2B This is a block diagram of the overall design of the HiPU in one embodiment of this disclosure;

[0063] Figure 3 This is a schematic diagram of the instruction processing module in one embodiment of this disclosure;

[0064] Figure 4 This is a schematic diagram illustrating the relationship between the instruction processing module and various control modules in one embodiment of this disclosure;

[0065] Figure 5 This is a schematic diagram of MPU calculation in one embodiment of this disclosure;

[0066] Figure 6 This is a schematic diagram of VPUTY calculation in one embodiment of this disclosure;

[0067] Figure 6AThis is a schematic diagram of the feature map data format output by the last layer of the neural network in one embodiment of this disclosure;

[0068] Figure 6B In one embodiment of this disclosure, Figure 6A The diagram shows the data format of the feature map data output from the last layer of the neural network after processing by the BBOX module;

[0069] Figure 7 This is a schematic diagram of a bus protocol in one embodiment of this disclosure;

[0070] Figure 8 This is a diagram of a common neural network accelerator architecture;

[0071] Figure 9 This is a diagram illustrating the storage format of HWC88 format FM data in one embodiment of this disclosure;

[0072] Figure 10 This is an example diagram of a basic HWC88 in one embodiment of this disclosure;

[0073] Figure 11 This is an example diagram of segmenting a single line of the entire input data FM in one embodiment of this disclosure;

[0074] Figure 12 This is an example diagram of an improved HWC88 in one embodiment of this disclosure;

[0075] Figure 12A This is a schematic diagram of the HWC88 storage format for multiple batches in one embodiment of this disclosure;

[0076] Figure 13 This is a diagram showing the storage format of WT data when FM performs convolution operations using the HWC88 format in one embodiment of this disclosure. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below in conjunction with the embodiments of this disclosure. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0078] Therefore, the following applies to the appendix Figures 1 to 13The detailed description of embodiments of this disclosure provided herein is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of the disclosure. All other embodiments derived by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0079] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0080] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the equipment or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0082] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0083] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0084] This disclosure is described in detail below.

[0085] The overall concept of the published book is as follows:

[0086] The RISC-V core, based on the complex instruction set (i.e., CISC instruction set), serves as the control core for loading neural network data and performing calculations at each layer. At the same time, it rearranges / reassembles the network input and output data according to the hardware storage format, thereby improving the computational efficiency of FPGA hardware for neural networks. This enables the realization of an FPGA neural network accelerator (hereinafter referred to as HiPU) based on RISC-V scheduling.

[0087] Figure 1 This illustrates the image convolution calculation decomposition process in the prior art, using... Figure 1 Taking a 3x3 convolution with a stride of 2 as an example, it shows that each convolution requires three points of three-channel data, but the stride is 2, just as... Figure 1 The gray area shown changes according to the step size. After calculating 0, 1, 2, it becomes 2, 3, 4. Because the step size is 2, it results in... Figure 1 The region represented by the gray 2 is reused. During convolution, the pixel addresses of the image become discontinuous with each convolution, leading to reduced memory utilization and frequent memory reads and writes, resulting in longer processing times. This is especially noticeable when observing... Figure 1 As shown in the lower part of the single-line input image, it can be clearly seen that: due to the convolution stride, the convolution calculation can reuse some channel data, but this will also cause the input image addresses of the two calculations to be discontinuous, resulting in branches during data scheduling and causing D Cache Miss (data cache miss). In the actual application of neural network accelerators, this will lead to a huge resource and time overhead.

[0088] against Figure 1The existing diagram of image convolution calculation decomposition in the prior art has problems. For the three color channels of three pixels in each row, in order to further improve the computational parallelism and memory utilization, this disclosure proposes an efficient neural network preprocessing method to realize a channel rearrangement scheme for input image data.

[0089] See Figures 1A to 1C This illustrates the single-lane lane rearrangement disclosed herein:

[0090] Taking single-row data as an example, the single-row data is from... Figure 1B The format shown is converted to Figure 1C The format shown is illustrated below. For example, a convolution stride of 2 is used. Please note... Figure 1A , Figure 1B , Figure 1C The CH -> arrow direction, H -> arrow direction, W -> arrow direction, and the three colors R, G, and B are described below:

[0091] The neural network preprocessing method is characterized by:

[0092] During image channel rearrangement, the original Figure 1A , Figure 1B The data from the three channels (0, 1, 2) of points 0 to 39 in the R, G, and B coordinates shown in the image are rearranged from left to right. Figure 1C The image shows the 9 channels of a point from bottom to top (where 3 times 3 equals 9, and is represented from bottom to top as 0, 0, 0, 1, 1, 1, 2, 2, 2). Furthermore, since the convolution stride is 2, the data of the original second pixel is further rearranged into three-channel data for pixels 2, 3, and 4 (represented from bottom to top as 2, 2, 2, 3, 3, 3, 4, 4, 4). Thus... Figures 1A to 1C This diagram illustrates all the input image -> single-line input image -> single-line input image channel rearrangements.

[0093] Will Figure 1C and Figure 1 By comparison, we can see that the nine channels at each point after rearrangement are exactly the same as the three-channel data from the original three points needed for each convolution. We can also see that because the stride in this embodiment is 2, and the sequence from 0, 0, 0 to 1, 1, 1 is equivalent to two three-channel sequences, therefore... Figure 1C The following characteristics are shown: 2, 2, 2; and the subsequent 4, 4, 4, etc. are all repeated once.

[0094] Therefore, for the three color channels of the three pixels in each row, the neural network preprocessing method disclosed in this disclosure can improve computational parallelism and memory utilization.

[0095] Furthermore, it is understandable that, Figures 1A to 1C Taking the illustrated embodiment as an example, the key to this neural network preprocessing method lies in: firstly, each convolution requires n-channel data down to m points (e.g., Figure 1 , Figures 1A to 1C All data consists of 3 points and 3 channels (e.g., R, G, B), which determines the second factor: the convolution stride k.

[0096] Let's combine the above... Figures 1A to 1C It can be found that:

[0097] If each convolution requires m points and n channels of data, then during rearrangement, it's similar to... Figure 1C so:

[0098] In the first column, first arrange the m*n numbers involved from the first point to the mth point from bottom to top;

[0099] Furthermore, if the convolution stride is k, then it is similar to... Figure 1C Thus, when rearranging from left to right to the second column: the data of the n channels at the (k+1)th point are arranged starting from the bottom; just as... Figure 1C Like the 2, 2, 2 pattern of the third point; then, arrange the (k+2)th point sequentially from bottom to top, all the way up to the (k+m)th point;

[0100] ...

[0101] Furthermore, when rearranging to the (i+1)th column, the data from the n channels of the i*k+1, i*k+2, ..., i*k+m points are arranged sequentially from bottom to top.

[0102] In another embodiment,

[0103] For example, a single grayscale channel can be rearranged into 8 channels, where 3 channels are data from 3 single-channel pixels and 5 channels are padded with 0s; for a 4-channel image, the data from 3 4-channel pixels reaches 12, and the nearest integer multiple of 8 is 16 channels. Therefore, it can be rearranged into 16 channels, where 12 channels are data from 3 4-channel pixels and 4 channels are padded with 0s.

[0104] By extension, in this disclosure, the stride and kernel size of the convolution are both scalable, such as:

[0105] The kernel size is 4*4. Taking a 3-channel RGB image as an example, a point after channel rearrangement will have 12 channels, containing three-channel data from 4 points. To compensate it to the nearest integer multiple of 8 channels, i.e., 16 channels, only 4 channels need to be filled with 0.

[0106] Assuming the step size changes:

[0107] When the step size was originally 2, the first point after rearrangement contained the data of three pixels: 0, 1, and 2. Now, with a step size of 1, the second point contains the data of pixels 2, 3, and 4.

[0108] If the step size is changed to 1, then the 0, 1, and 2 of the first point remain unchanged. The corresponding change is that the pixel data of the second point changes from 2, 3, and 4 to 1, 2, and 3, and so on for all subsequent points.

[0109] It should be noted that the zero-padding step can be used for the rearrangement / recombination disclosed in this disclosure. If each convolution requires N data (note: N corresponds to the computational parallelism of the neural network accelerator), when N is greater than m*n channels, then from the first column to the second-to-last column, each column should be padded with N-(m*n) zeros; for the last column, based on the actual number M of channels in the last column, NM zeros should be padded. It is understood that the actual number M of channels in the last column may be equal to or less than the second-to-last column. Further details regarding zero-padding in the last column can be found below. Figure 1D The examples revealed.

[0110] The above are examples of the rearrangement / recombination disclosed in this disclosure. It can be seen that it is not limited to the number of channels or the convolution stride. Furthermore, it is not limited to the convolution kernel size. This disclosure clearly proposes a rearrangement method for input images, including image rearrangement and image format conversion without limiting the number of channels, as well as rearrangement of input images under various convolution kernel sizes and different convolution strides. This means that this disclosure has a wide range of applications and can be used in various network acceleration solutions and various processors to improve memory utilization, reduce image convolution computation time, and improve computational efficiency.

[0111] 2 Technical Solution

[0112] 2.1 Layered Design

[0113] Deep neural networks are an implementation of the deep learning concept and a small part of artificial intelligence (AI). A RISC-V-based neural network accelerator deploys neural network algorithms on an FPGA platform and utilizes a microcontroller unit (MCU) for scheduling and computation. The accelerator can be divided into three layers: storage, computation, and control. An accelerator design block diagram is shown below. Figure 2A As shown.

[0114] The storage portion of a neural network is primarily divided into the DDR (Double Data Rate) region and the BRAM (Browser RAM) region. The DDR stores all feature parameters of a single deep neural network, the input image, the output result, and the feature map data from intermediate layers. The BRAM region, using a swap-in / swap-out rule, stores the feature maps and parameter information required for the current computation. Based on the different characteristics of the data, the BRAM region stores the feature maps, the weights of the network parameters, and the biases of the network parameters in different locations. Feature maps require bidirectional operations from BRAM to DDR, while the network parameters only need to be loaded from DDR to BRAM. The data width of the bias portion is lower than that of the weight portion, so it is also stored separately. A schematic diagram of the storage layer partitioning is shown below. Figure 2A-1 As shown, compared to Local Memory and DDR storage structures that are not organized and have cross-module data transmission, this disclosure significantly reduces the utilization of FPGA internal routing resources through refined data area management.

[0115] 2.2 Instruction Set

[0116] The proposed solution preferably includes a new instruction set. However, it may also use a suitable complex instruction set from the prior art, whether it is open source or closed source.

[0117] The new self-developed complex instruction set disclosed in this disclosure is detailed below:

[0118] Furthermore, in one embodiment, this disclosure discloses an extended VM instruction set encoding method for an edge DNN scenario based on RISC-V, comprising the following steps:

[0119] 1) Define the machine code bit width:

[0120] For example, the dedicated instruction set of this disclosure is based on the RISC-V extension, and the bus width of the data storage unit and program storage unit of the corresponding dedicated instruction set processor is 32-bits, so the width of the machine code is 32-bits.

[0121] 2) Define instruction types:

[0122] The instructions in this instruction set are defined as two main categories: vector-related instructions and matrix-related instructions. These two categories can be further subdivided, including storage input / output instructions for corresponding data formats, calculation instructions for corresponding data formats, and condition register generation instructions for corresponding data formats.

[0123] 3) Define instruction addressing modes:

[0124] Operand addressing in instruction set instructions is defined by three addressing modes: immediate addressing, register addressing, and indexed addressing. Immediate addressing is used to address immediate values, register addressing is used to address general-purpose registers and special registers, and indexed addressing is used to address memory.

[0125] 4) Encoding:

[0126] The first instruction is `vector load byte`.

[0127] Command Function:

[0128] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, and then retrieve 64 bytes of data sequentially from that address as the source operands.

[0129] Use the vector register pointed to by VR_d as the destination operand, which is a vector of 64 elements, where each element is a word.

[0130] Each byte of the source operand is placed into the lower 8 bits of the corresponding element in the destination operand.

[0131] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of vector load. Bits 11 to 14 are the type code, used to distinguish different functional types of vector instructions.

[0132] The second instruction is to load the half-word vector.

[0133] Command Function:

[0134] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, and then retrieve 128 bytes of data from that address as the source operands.

[0135] Use the vector register pointed to by VR_d as the destination operand, which is a vector of 64 elements, where each element is a word.

[0136] Place each half-word of the source operand into the lower 16 bits of the corresponding element in the destination operand.

[0137] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of vector load. Bits 11 to 14 are the type code, used to distinguish different functional types of vector instructions.

[0138] The third instruction, `vector load word`

[0139] Command Function:

[0140] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, and then retrieve 256 bytes of data from that address as the source operands.

[0141] Use the vector register pointed to by VR_d as the destination operand, which is a vector of 64 elements, where each element is a word.

[0142] Place each half-word of the source operand into the corresponding 32 bits of the destination operand.

[0143] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of vector load. Bits 11 to 14 are the type code, used to distinguish different functional types of vector instructions.

[0144] The fourth instruction is to store a byte in a vector.

[0145] Command Function:

[0146] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, which is then used as the destination address;

[0147] Use the contents of the source register VR_s2 as the source operand. The source operand is a vector containing 64 elements, where each element is a word.

[0148] Take the lower 8 bits of each element to form 64 bytes of data, and store it in the destination address of the memory.

[0149] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of the vector store. Bits 11 to 14 are the type code, used to distinguish different functional types of the vector instruction.

[0150] The fifth instruction is to store the half-word in a vector.

[0151] Command Function:

[0152] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, which is then used as the destination address;

[0153] Use the contents of the source register VR_s2 as the source operand. The source operand is a vector containing 64 elements, where each element is a word.

[0154] Take half a word from each element to form 128 bytes of data, and store it in the destination address of the memory.

[0155] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of the vector store. Bits 11 to 14 are the type code, used to distinguish different functional types of the vector instruction.

[0156] The sixth instruction is to store words using a vector.

[0157] Command Function:

[0158] Add the contents of the source register SR_s1 to the immediate value to synthesize the address of the vector memory, which is then used as the destination address;

[0159] Use the contents of the source register VR_s2 as the source operand. The source operand is a vector containing 64 elements, where each element is a word.

[0160] Extract words from each element to form 256 bytes of data, and store them in the destination address of the memory.

[0161] Machine code explanation: Bits 20 to 24 of the machine code represent bits 0 to 4 of the immediate value; bits 25 to 27 represent bits 5 to 7 of the immediate value; bits 30 to 31 represent bits 8 to 9 of the immediate value; bits 15 to 19 represent the register number SR_s1; bits 7 to 10 represent the register number VR_d. Bits 28 and 29 are the type code, used to distinguish different functional types of the vector store. Bits 11 to 14 are the type code, used to distinguish different functional types of the vector instruction.

[0162] The seventh instruction, `vector vector add`

[0163] Command Function:

[0164] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0165] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0166] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0167] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0168] Add the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to get the result of the corresponding element of the destination operand.

[0169] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0170] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0171] The eighth instruction, vector scalar add

[0172] Instruction function: Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0173] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0174] Use the contents of the source register VPR as the source operand 3, which is a vector of 64 elements, where each element is one bit; use the contents of the destination register VR_d as the destination operand, which is a vector of 64 elements, where each element is one word.

[0175] Add each element of source operand 1 to source operand 2, and then pass it through operand 3 to get the result of the corresponding element of the destination operand.

[0176] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0177] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0178] The ninth instruction, vector vector sub

[0179] Command Function:

[0180] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0181] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0182] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0183] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0184] Subtract the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the gate to get the result of the corresponding element of the destination operand.

[0185] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0186] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0187] The tenth instruction, vector scalar sub

[0188] Command Function:

[0189] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0190] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0191] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0192] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0193] Subtract each element of source operand 1 from source operand 2, and then pass it through operand 3 to obtain the result of the corresponding element of the destination operand.

[0194] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0195] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0196] The eleventh instruction, vector vector max

[0197] Command Function:

[0198] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0199] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0200] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0201] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0202] The corresponding elements of source operand 1 and source operand 2 are evaluated by taking the larger value, and then the result is obtained by using operand 3 as the gating factor for the corresponding element of the destination operand.

[0203] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0204] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0205] The twelfth instruction, vector scalar max

[0206] Command Function:

[0207] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0208] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0209] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0210] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0211] Perform a maximum value calculation on each element of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0212] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0213] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0214] The thirteenth instruction, vector vector min

[0215] Command Function:

[0216] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0217] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0218] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0219] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0220] The corresponding elements of source operand 1 and source operand 2 are used to calculate the smaller value, and then the result of the corresponding element of the destination operand is obtained by gating through operand 3.

[0221] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0222] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0223] The fourteenth instruction, vector scalar min

[0224] Command Function:

[0225] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0226] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0227] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0228] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0229] Perform a minimum value calculation on each element of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0230] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0231] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector algebra operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2. Bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0232] The fifteenth instruction, vector vector mul

[0233] Command Function:

[0234] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0235] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0236] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0237] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0238] Perform a multiplication of the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0239] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0240] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector multiplication and division operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0241] The sixteenth instruction, vector scalar mul

[0242] Command Function:

[0243] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0244] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0245] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0246] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0247] Perform a multiplication operation on each element of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0248] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0249] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector multiplication and division operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0250] The seventeenth instruction, vector vector and

[0251] Command Function:

[0252] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0253] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0254] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0255] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0256] Perform a logical AND operation on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0257] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0258] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0259] The eighteenth instruction, vector scalar and

[0260] Command Function:

[0261] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0262] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0263] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0264] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0265] Perform a logical AND operation between each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0266] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0267] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0268] The nineteenth instruction, vector vector or

[0269] Command Function:

[0270] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0271] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0272] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0273] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0274] Perform a logical OR operation on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0275] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0276] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0277] The twentieth instruction, vector scalar or

[0278] Command Function:

[0279] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0280] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0281] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0282] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0283] Perform a logical OR operation on each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0284] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0285] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0286] Instruction number twenty-one, vector vector xor

[0287] Command Function:

[0288] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0289] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0290] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0291] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0292] Perform a logical XOR operation on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0293] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0294] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0295] Instruction number twenty-two: vector scalar xor

[0296] Command Function:

[0297] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0298] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0299] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0300] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0301] Perform a logical XOR operation on each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0302] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0303] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0304] Instruction number twenty-three: vector vector nxor

[0305] Command Function:

[0306] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0307] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0308] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0309] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0310] Perform a logical XOR operation on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0311] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0312] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0313] Instruction number twenty-four: vector scalar nxor

[0314] Command Function:

[0315] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0316] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0317] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0318] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0319] Perform a logical XOR operation on each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0320] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s1; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0321] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 of the machine code are the type code, used to distinguish different functional types of vector logic operations; bits 25 and 27 of the machine code are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0322] Instruction number twenty-five: vector vector sll

[0323] Command Function:

[0324] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0325] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0326] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0327] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0328] Perform a logical left shift on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0329] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0330] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0331] Instruction number twenty-six: vector scalar sll

[0332] Command Function:

[0333] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0334] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0335] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0336] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0337] Perform a logical left shift calculation on each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0338] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0339] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0340] Instruction number twenty-seven, vector vector srl

[0341] Command Function:

[0342] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0343] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0344] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0345] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0346] Perform a logical right shift on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0347] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0348] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0349] Instruction number twenty-eight: vector scalar srl

[0350] Command Function:

[0351] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0352] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0353] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0354] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0355] Perform a logical right shift calculation on each element of source operand 1 and source operand 2, and then use operand 3 as the strobe to obtain the result of the corresponding element of the destination operand.

[0356] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0357] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0358] Instruction number twenty-nine, vector vector sla

[0359] Command Function:

[0360] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0361] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0362] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0363] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0364] Perform an algebraic left shift on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0365] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0366] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0367] The thirtieth instruction, vector scalar sla

[0368] Command Function:

[0369] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0370] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0371] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0372] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0373] Perform Boolean algebraic calculations on each element of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0374] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0375] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0376] The thirty-first instruction, vector vector sra

[0377] Command Function:

[0378] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0379] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0380] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0381] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0382] Perform an algebraic right shift on the corresponding elements of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0383] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0384] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0385] Instruction number thirty-two, vector scalar sra

[0386] Command Function:

[0387] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0388] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0389] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0390] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0391] Perform an algebraic right shift on each element of source operand 1 and source operand 2, and then use operand 3 as the gate to obtain the result of the corresponding element of the destination operand.

[0392] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0393] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector shift operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0394] Instruction number 33: vector lookup table

[0395] Command Function:

[0396] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0397] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0398] The content of each element of source operand 1 is used as the entry address of the lookup table for searching, and the result of the corresponding element of the destination operand is obtained by strobing through operand 3.

[0399] Machine code description: Bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 11 to 14 of the machine code are the type code, used to distinguish the different functional types of the vector instruction.

[0400] The thirty-fourth instruction, `vector<vector> predict equal`, is used to predict equal vectors.

[0401] Command Function:

[0402] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0403] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0404] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0405] Compare the corresponding elements of source operand 1 and source operand 2. If they are equal, return 1; if they are different, return 0. This result is used as the result of the corresponding element of the destination operand.

[0406] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VPR_d.

[0407] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0408] Instruction number 35: `vector scalar predict equal`

[0409] Command Function:

[0410] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0411] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0412] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0413] Each element of source operand 1 is compared with source operand 2. If they are equal, the result is 1; otherwise, it is 0. This result is used as the result of the corresponding element in the destination operand.

[0414] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VPR_d.

[0415] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0416] Instruction 36: vector predict not equal

[0417] Command Function:

[0418] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0419] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0420] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0421] Compare the corresponding elements of source operand 1 and source operand 2. If they are not equal, return 1; if they are equal, return 0. This result is used as the result of the corresponding element of the destination operand.

[0422] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 are the register number VR_s1; bits 7 to 10 are the register number VPR_d; bits 28 to 29 are the type code, used to distinguish different functional types of vector condition code operations; bits 25 to 27 are the type code, used to distinguish different types of source operand 2; bits 11 to 14 are the type code, used to distinguish different functional types of vector instructions.

[0423] Instruction number 37: vector scalar predict not equal

[0424] Command Function:

[0425] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0426] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0427] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0428] Each element of source operand 1 is compared with source operand 2. If they are not equal, the result is 1; if they are equal, the result is 0. This result is used as the result of the corresponding element in the destination operand.

[0429] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VPR_d.

[0430] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0431] Instruction number 38: vector vector predicts letter than

[0432] Command Function:

[0433] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0434] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0435] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0436] Compare the corresponding elements of source operand 1 and source operand 2, and calculate the result. If the result is less than 1, the result is 1, and if the result is greater than 0, the result is used as the result of the corresponding element of the destination operand.

[0437] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VPR_d.

[0438] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0439] Instruction number 39: Vector scalar predicts letter than

[0440] Command Function:

[0441] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0442] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0443] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0444] Each element of source operand 1 is compared with source operand 2; if less than, it is 1, and if greater than, it is 0. This result is used as the corresponding element of the destination operand.

[0445] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VPR_d.

[0446] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0447] Instruction number 40: `vector<vector>` predicts greater than...

[0448] Command Function:

[0449] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0450] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0451] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0452] Compare the corresponding elements of source operand 1 and source operand 2, and calculate the result. If the result is greater than 1, the result is less than 0. This result is used as the result of the corresponding element of the destination operand.

[0453] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VPR_d.

[0454] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0455] Instruction number 41: vector scalar predict greater than

[0456] Command Function:

[0457] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0458] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0459] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0460] Each element of source operand 1 is compared with source operand 2; if it is greater than 1, it is 0, and this result is used as the corresponding element of the destination operand.

[0461] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VPR_d.

[0462] Bits 28 and 29 of the machine code are type codes used to distinguish different functional types of vector condition code operations; bits 25 to 27 of the machine code are type codes used to distinguish different types of the source operand 2; bits 11 to 14 of the machine code are type codes used to distinguish different functional types of the vector instruction.

[0463] Instruction number 42, vector predict and

[0464] Command Function:

[0465] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0466] Use the contents of the source register VPR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is one bit.

[0467] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0468] Perform a logical AND operation on the corresponding elements of source operand 1 and source operand 2, and use the result as the corresponding element of the destination operand.

[0469] Machine code description: Bits 20 to 24 of the machine code are the register number VPR_s2; bits 15 to 19 of the machine code are the register number VPR_s1; bits 7 to 10 of the machine code are the register number VPR_d; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0470] Instruction number 43, vector predict or

[0471] Command Function:

[0472] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0473] Use the contents of the source register VPR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is one bit.

[0474] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0475] Perform a logical OR operation on the corresponding elements of source operand 1 and source operand 2, and use the result as the corresponding element of the destination operand.

[0476] Machine code description: Bits 20 to 24 of the machine code are the register number VPR_s2; bits 15 to 19 of the machine code are the register number VPR_s1; bits 7 to 10 of the machine code are the register number VPR_d; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0477] Instruction number 44: vector predict xor

[0478] Command Function:

[0479] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0480] Use the contents of the source register VPR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is one bit.

[0481] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0482] Perform a logical XOR operation on the corresponding elements of source operand 1 and source operand 2, and use the result as the corresponding element of the destination operand.

[0483] Machine code description: Bits 20 to 24 of the machine code are the register number VPR_s2; bits 15 to 19 of the machine code are the register number VPR_s1; bits 7 to 10 of the machine code are the register number VPR_d; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0484] Instruction number 45: vector predict nxor

[0485] Command Function:

[0486] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0487] Use the contents of the source register VPR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is one bit.

[0488] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0489] Perform a logical XOR operation on the corresponding elements of source operand 1 and source operand 2, and use the result as the corresponding element of the destination operand.

[0490] Machine code description: Bits 20 to 24 of the machine code are the register number VPR_s2; bits 15 to 19 of the machine code are the register number VPR_s1; bits 7 to 10 of the machine code are the register number VPR_d; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0491] Instruction number 46: vector predict not

[0492] Command Function:

[0493] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0494] The contents of the destination register VPR_d are used as the destination operand, which is a vector of 64 elements, where each element is one bit.

[0495] Invert the corresponding element of the source operand 1, and use it as the result of the corresponding element of the destination operand.

[0496] Machine code description: Bits 15 to 19 of the machine code are the register number VPR_s1; bits 7 to 10 of the machine code are the register number VPR_d; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0497] Instruction number 47: vector predict swap

[0498] Command Function:

[0499] Use the contents of the source register VPR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is one bit.

[0500] Use the contents of the source register VPR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is one bit.

[0501] Swap the corresponding elements of source operand 1 and source operand 2.

[0502] Machine code description: Bits 20 to 24 of the machine code are the register number VPR_s2; bits 15 to 19 of the machine code are the register number VPR_s1; bits 28 to 29 of the machine code are the type code, used to distinguish different functional types of vector condition code operations; bits 11 to 14 of the machine code are the type code, used to distinguish different functional types of vector instructions.

[0503] Instruction number 48: vector vector fuse add

[0504] Command Function:

[0505] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0506] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0507] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0508] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0509] Perform a shift and addition operation on the corresponding elements of source operand 1 and source operand 2. The shift operation method is defined by the CSR register and is selected by operand 3, which is used as the result of the corresponding element of the destination operand.

[0510] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0511] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector floating-point operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0512] Instruction number 49: vector scalar fuse add

[0513] Command Function:

[0514] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0515] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0516] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0517] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0518] Perform a shift and addition operation on each element of source operand 1 and source operand 2. The shift operation method is defined by the CSR register and is strobed by operand 3, which is used as the result of the corresponding element of the destination operand.

[0519] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 are the register number VR_s1; bits 7 to 10 are the register number VR_d; bits 30 to 31 are the register number VPR; bits 28 to 29 are the type code, used to distinguish different function types of vector floating-point operations; bits 25 to 27 are the type code, used to distinguish different types of source operand 2; bits 11 to 14 are the type code, used to distinguish different function types of vector instructions.

[0520] Instruction number 50, vector vector fuse sub

[0521] Command Function:

[0522] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0523] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0524] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0525] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0526] Perform a shift and subtraction operation on the corresponding elements of source operand 1 and source operand 2. The shift operation method is defined by the CSR register and is selected by operand 3, which is used as the result of the corresponding element of the destination operand.

[0527] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0528] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector floating-point operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0529] Instruction number fifty-one: vector scalar fuse sub

[0530] Command Function:

[0531] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0532] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0533] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0534] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0535] Perform a shift-subtraction operation on each element of source operand 1 and source operand 2. The shift calculation method is defined by the CSR register and is strobed by operand 3, which serves as the result of the corresponding element of the destination operand.

[0536] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0537] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector floating-point operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0538] Instruction number 52, vector vector fuse mul

[0539] Command Function:

[0540] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0541] Use the contents of the source register VR_s2 as source operand 2. Source operand 2 is a vector containing 64 elements, where each element is a word.

[0542] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0543] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0544] Perform a shift multiplication on the corresponding elements of source operand 1 and source operand 2. The shift calculation method is defined by the CSR register and is strobed by operand 3, which is used as the result of the corresponding element of the destination operand.

[0545] Machine code description: Bits 20 to 24 of the machine code are the register number VR_s2; bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d.

[0546] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector floating-point operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0547] Instruction number 53: vector scalar fuse mul

[0548] Command Function:

[0549] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0550] Use the contents of the source register SR_s2 as the source operand 2, and the source operand 2 is a scalar;

[0551] Use the contents of the source register VPR as the source operand 3. The source operand 3 is a vector containing 64 elements, where each element is one bit.

[0552] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0553] Perform a shift multiplication on each element of source operand 1 and source operand 2. The shift calculation method is defined by the CSR register and is strobed by operand 3, which is used as the result of the corresponding element of the destination operand.

[0554] Machine code description: Bits 20 to 24 of the machine code are the numbers of register SR_s2; bits 15 to 19 of the machine code are the numbers of register VR_s1; bits 7 to 10 of the machine code are the numbers of register VR_d.

[0555] Bits 30 and 31 of the machine code are the register VPR number; bits 28 and 29 are the type code, used to distinguish different functional types of vector floating-point operations; bits 25 and 27 are the type code, used to distinguish different types of the source operand 2; bits 11 and 14 of the machine code are the type code, used to distinguish different functional types of the vector instruction.

[0556] Instruction 54: vector fuse Iook-up-table

[0557] Command Function:

[0558] Use the contents of the source register VR_s1 as source operand 1. Source operand 1 is a vector containing 64 elements, where each element is a word.

[0559] The contents of the destination register VR_d are used as the destination operand, which is a vector of 64 elements, where each element is a word;

[0560] The content of each element of the source operand 1 is used as the entry address of the floating-point lookup table for searching. The search result is then shifted. The shifting method is defined by the CSR register and is strobed by operand 3, serving as the result of the corresponding element of the destination operand.

[0561] Machine code description: Bits 15 to 19 of the machine code are the register number VR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 11 to 14 of the machine code are the type code, used to distinguish the different functional types of the vector instruction.

[0562] Similarly, in another embodiment, the following instructions can also be encoded:

[0563] The first instruction is: matrix matrix multiply-add

[0564] Command Function:

[0565] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0566] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0567] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0568] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0569] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0570] Read matrix operand 1 and matrix operand 2 from memory, perform matrix multiplication, add the result to the corresponding element of operand 3, and then select the result of the corresponding element of the destination operand through operand 4.

[0571] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0572] The second instruction is: matrix matrix align-up multiply-add

[0573] Command Function:

[0574] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0575] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0576] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0577] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0578] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0579] Read matrix operand 1 and matrix operand 2 from memory. Shift matrix operand 2 left by 8 words, fill the low bits with 0, perform matrix multiplication, add the result to the corresponding element of operand 3, and select it through operand 4 as the result of the corresponding element of the destination operand.

[0580] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0581] The third instruction is: matrix matrix align-down multiply-add

[0582] Command Function:

[0583] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0584] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0585] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0586] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0587] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0588] Read source operand 1 and source operand 2 from memory. Shift source operand 2 right by 8 words and fill the high-order bits with 0. Perform matrix multiplication. Add the result to the corresponding element of operand 3. Then, select the result of the corresponding element of the destination operand through operand 4.

[0589] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0590] The fourth instruction is matrix multiply-accumulate.

[0591] Command Function:

[0592] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0593] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0594] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0595] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0596] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0597] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence, matrix multiplication is performed, the calculation results are continuously accumulated, and the final calculation result is added to the element at the corresponding position of operand 3. Then, it is selected by operand 4 as the result of the element corresponding to the destination operand.

[0598] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0599] The fifth instruction is: matrix align-up multiply-accumulate

[0600] Command Function:

[0601] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0602] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0603] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0604] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0605] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0606] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence. Matrix operand 2 is shifted left by 8 words and padded with 0s in the low bits. Matrix multiplication is performed and the calculation results are continuously accumulated. The final calculation result is added to the element at the corresponding position of operand 3 and then selected by operand 4 as the result of the element corresponding to the destination operand.

[0607] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0608] The sixth instruction is: matrix align-down multiply-accumulate.

[0609] Command Function:

[0610] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0611] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0612] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0613] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0614] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0615] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence. Matrix operand 2 is shifted right by 8 words and padded with 0 in the high bits. Matrix multiplication is performed and the calculation results are continuously accumulated. The final calculation result is added to the element at the corresponding position of operand 3 and then selected by operand 4 as the result of the element corresponding to the destination operand.

[0616] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0617] The seventh instruction is: matrix matrix dot multiply-add

[0618] Command Function:

[0619] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0620] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0621] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0622] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0623] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0624] Read matrix operand 1 and matrix operand 2 from memory, perform element-wise multiplication between the matrices, add the result to the corresponding element of operand 3, and then select the result of the corresponding element of the destination operand through operand 4.

[0625] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0626] The eighth instruction is: matrix matrix align-down dot multiply-add

[0627] Command Function:

[0628] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0629] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0630] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0631] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0632] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0633] Read matrix operand 1 and matrix operand 2 from memory. Shift matrix operand 2 left by 8 words and fill the low bits with 0. Perform multiplication of corresponding elements between the matrices. Add the result to the corresponding element of operand 3 and select it through operand 4 as the result of the corresponding element of the destination operand.

[0634] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0635] The ninth instruction is: matrix align-down dot multiply-add

[0636] Command Function:

[0637] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0638] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0639] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0640] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0641] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0642] Read matrix operand 1 and matrix operand 2 from memory. Shift matrix operand 2 right by 8 words and fill the high bits with 0. Perform multiplication of corresponding elements between the matrices. Add the result to the corresponding element of operand 3 and select it through operand 4 as the result of the corresponding element of the destination operand.

[0643] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0644] The tenth instruction is: matrix dot multiply-accumulate.

[0645] Command Function:

[0646] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0647] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0648] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0649] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0650] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0651] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence, and multiplication calculations are performed between corresponding elements of the matrix. The calculation results are continuously accumulated, and the final calculation result is added to the element at the corresponding position of operand 3. Then, it is selected by operand 4 as the result of the element corresponding to the destination operand.

[0652] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0653] The eleventh instruction is: matrix align-up dot multiply-accumulate

[0654] Command Function:

[0655] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0656] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0657] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0658] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0659] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0660] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence. Matrix operand 2 is shifted left by 8 words and padded with 0s in the low bits. Multiplication calculations are performed between corresponding elements of the matrix. The calculation results are continuously accumulated. The final calculation result is added to the element at the corresponding position of operand 3 and then selected by operand 4 as the result of the element corresponding to the destination operand.

[0661] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0662] The twelfth instruction is: matrix align-down dot multiply-accumulate.

[0663] Command Function:

[0664] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of matrix operand 1. Matrix operand 1 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0665] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 64 elements, where each element is a word, and the size of the matrix is ​​8*8.

[0666] The contents of the source register VR_s are used as source operand 3. Source operand 3 contains 64 elements, each of which is a word. It is treated as an 8*8 matrix.

[0667] Use the contents of the source register VPR as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. Treat it as an 8*8 matrix.

[0668] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as an 8*8 matrix.

[0669] The matrix multiplication and accumulation process is controlled by a special CSR register. Matrix operand 1 and matrix operand 2 are read from memory in sequence. Matrix operand 2 is shifted right by 8 words and padded with 0 in the high bits. Multiplication calculations are performed between corresponding elements of the matrix. The calculation results are continuously accumulated. The final calculation result is added to the element at the corresponding position of operand 3 and then selected by operand 4 as the result of the element corresponding to the destination operand.

[0670] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0671] The thirteenth instruction, vector matrix multiply-add

[0672] Command Function:

[0673] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0674] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0675] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0676] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0677] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0678] Read vector operand 1 and matrix operand 2 from memory, perform vector-matrix multiplication, add the result to the corresponding element of operand 3, and then select it through operand 4 as the result of the corresponding element of the destination operand.

[0679] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0680] The fourteenth instruction is: vector matrix align-up multiply-add.

[0681] Command Function:

[0682] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0683] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0684] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0685] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0686] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0687] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is left-shifted by 64 words and padded with 0s in the low bits. Perform vector-matrix multiplication. Add the result to the corresponding element of operand 3. Then, select the result of the corresponding element of the destination operand through operand 4.

[0688] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0689] The fifteenth instruction is: vector matrix align-down multiply-add.

[0690] Command Function:

[0691] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0692] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0693] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0694] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0695] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0696] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is right-shifted by 64 words and padded with 0s in the high bits. Perform vector-matrix multiplication. Add the result to the corresponding element of operand 3. Then, select the result of the corresponding element of the destination operand through operand 4.

[0697] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0698] The sixteenth instruction is: vector matrix multiply-accumulate.

[0699] Command Function:

[0700] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0701] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0702] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0703] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0704] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0705] The matrix multiplication and accumulation process is controlled by a special CSR register. Vector operand 1 and matrix operand 2 are read from memory, and vector-matrix multiplication is performed. The calculation results are continuously accumulated. The final calculation result is added to the element at the corresponding position of operand 3, and then selected by operand 4 as the result of the element corresponding to the destination operand.

[0706] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0707] The seventeenth instruction is: vector matrix align-up multiply-accumulate.

[0708] Command Function:

[0709] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0710] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0711] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0712] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0713] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0714] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is left-shifted by 64 words and padded with 0s in the low bits. Perform vector-matrix multiplication. The calculation results are continuously accumulated. The final calculation result is added to the corresponding element of operand 3 and then selected through operand 4 as the result of the corresponding element of the destination operand.

[0715] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0716] The eighteenth instruction: vector matrix align-down multiply-accumulate

[0717] Command Function:

[0718] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word, and the size of the vector is 1*64.

[0719] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​64*64.

[0720] Use the contents of the source register VR_s as source operand 3. Source operand 3 contains 64 elements, each of which is a word. Treat it as a vector of size 1*64.

[0721] The contents of the source register VPR are used as source operand 4. Source operand 4 contains 64 elements, each of which is one bit. It is treated as a vector of size 1*64.

[0722] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word, and is treated as a vector of size 1*64.

[0723] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is right-shifted by 64 words and padded with 0s in the high bits. Perform vector-matrix multiplication. The calculation results are continuously accumulated. The final calculation result is added to the corresponding element of operand 3 and then selected through operand 4 as the result of the corresponding element of the destination operand.

[0724] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0725] The nineteenth instruction is: vector matrix bundle multiply-add.

[0726] Command Function:

[0727] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word. The size of the vector is 1*8, and it is assumed that there are 8 vectors of the same size.

[0728] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​8*8, which is considered to be 8 matrices of the same size.

[0729] The contents of the source register VR_s are used as the source operand 3. The source operand 3 contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0730] The contents of the source register VPR are used as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0731] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0732] Read vector operand 1 and matrix operand 2 from memory, perform vector-matrix multiplication on the corresponding vector and matrix, and the result is 8 vectors of size 1*8. Add them to the corresponding elements of operand 3, and then select them through operand 4 as the result of the corresponding element of the destination operand.

[0733] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0734] The twentieth instruction: vector matrix align-up bundle multiply-add

[0735] Command Function:

[0736] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word. The size of the vector is 1*8, and it is assumed that there are 8 vectors of the same size.

[0737] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​8*8, which is considered to be 8 matrices of the same size.

[0738] The contents of the source register VR_s are used as the source operand 3. The source operand 3 contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0739] The contents of the source register VPR are used as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0740] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0741] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is left-shifted by 64 words and padded with 0s in the low bits. The vector and matrix at the corresponding positions are multiplied by vector-matrix, and the result is 8 vectors of size 1*8. These are added to the corresponding elements of operand 3 and then selected by operand 4 as the result of the corresponding element of the destination operand.

[0742] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0743] Instruction number twenty-one: vector matrix align-down bundle multiply-add

[0744] Command Function:

[0745] The contents of the source register SR_s1 are used as source operand 1, and source operand 1 is used as the memory entry address of vector operand 1. Vector operand 1 contains 64 elements, where each element is a word. The size of the vector is 1*8, and it is assumed that there are 8 vectors of the same size.

[0746] The contents of the source register SR_s2 are used as the source operand 2, and the source operand 2 is used as the memory entry address of matrix operand 2. Matrix operand 2 contains 4096 elements, where each element is a word, and the size of the matrix is ​​8*8, which is considered to be 8 matrices of the same size.

[0747] The contents of the source register VR_s are used as the source operand 3. The source operand 3 contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0748] The contents of the source register VPR are used as the source operand 4. The source operand 4 contains 64 elements, each of which is one bit. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0749] The contents of the destination register VR_d are used as the destination operand. The destination operand contains 64 elements, each of which is a word. It is regarded as a vector of size 1*8, and is considered to have 8 vectors of the same size.

[0750] Read vector operand 1 and matrix operand 2 from memory. Matrix operand 2 is shifted right by 64 words and padded with 0s in the high bits. The vector and matrix at the corresponding positions are multiplied by vector-matrix, and the result is 8 vectors of size 1*8. These are added to the corresponding elements of operand 3 and then selected by operand 4 as the result of the corresponding element of the destination operand.

[0751] Machine code description: Bits 20 to 24 of the machine code are the register number SR_s2; bits 15 to 19 of the machine code are the register number SR_s1; bits 7 to 10 of the machine code are the register number VR_d; bits 30 to 31 of the machine code are the register number VPR; bits 25 to 28 of the machine code are the register number VR_s; bits 11 to 14 of the machine code are the type code, used to distinguish the different function types of matrix instructions.

[0752] 2.3 FPGA Implementation of AI Processor

[0753] The HiPU, deployed on an FPGA, is the core of the hardware accelerator design. Its detailed design block diagram is shown below. Figure 2B As shown, the HiPU employs a multi-core design, with multiple cores working in parallel while the hardware accelerator is operational. The HiPU utilizes a CISC instruction set, using CISC instructions for parameter configuration and neural network computation control scheduling. The RISC-V core writes the parameter configuration to the DISP (Dispatch) module via the Regmap Mgr (Register Map Manager) module. The DISP module decouples all parameters and control instructions and sends them to the distributed IQ queues (ALU, LDMR, SVMR), which then forward them to the corresponding execution control modules. The execution control modules then parse and call the appropriate computational units to complete the computation. This distributed IQ significantly simplifies the selection circuit design compared to a centralized IQ where all functional modules share a single issue queue. The Retire module is responsible for retiring corresponding CISC instructions, allowing new parameters to be issued by the RISC-V core. The Score Board records all CISC instructions, enabling corresponding decoupling processing.

[0754] See Figure 2BThe MCU uses a 32-inch RISC-V core for neural network parameter configuration. BlockMemory uses Mtx Reg a / zero, Mtx Reg b, Mtx Reg c, Br Reg b, and Br Reg c to store image data, weights, and BIAS parameters. The MPU and VPU are designed as independent computation modules, controlled and scheduled using corresponding MPUctrl and VPUctrl modules. The feature map transformation (Ftrans) and data transformation (Dtrans) modules are implemented using the VPUTY module, with VPUTY_ctrl used for control and scheduling. The Load_MtxReg_ctrl module primarily reads image, weight, and BIAS operation instructions from DDR. The Save_MtxReg_ctrl module primarily writes data from BlockMemory to DDR. The DDR arbiter handles multi-channel data read / write scheduling control. When performing neural network acceleration processing on an image, the image is first written to DDR, and then the RISC-V core is started to perform scheduled computation. Under the scheduling of the RISC-V core, the MPU, VPU, and VPUTY work synchronously or asynchronously to complete the computation of an image. Finally, post-processing is performed to obtain the required computation results.

[0755] 2.3.1 RISC-V Processor

[0756] The RISC-V processor uses the Harvard architecture, and the processor here can be any RISC-V 32IM processor.

[0757] 2.3.2 Regmap Module

[0758] The Regmap module primarily contains a memory space accessible by the RISC-V processor's Load and Store instructions. This memory space mainly consists of 4-byte read / write access areas. This space is divided into the following subspaces, as shown in Table 1:

[0759] Table 1

[0760]

[0761]

[0762] 2.3.3 Complex Instruction Set Processing

[0763] The instruction set processing mainly comprises four modules: the IQ (Issue Queue) instruction cache queue, the instruction write-back maintenance module (Retire module), the instruction dispatch module (DISP module), and the Scoreboard module, which records the dependencies between the source and destination of each instruction. Figure 3 As shown.

[0764] The relationship between the instruction processing module and the various control modules is as follows: Figure 4 As shown.

[0765] The DISP stores a string of CISC instructions (which can be dynamically generated by the processor). When an instruction is available in the DISP, the DISP identifies the type of the instruction and distributes it to the issue queue of the ALU, LDMR, and SVMR. At the same time, the instruction is sent to the Retire module.

[0766] These three IQs store instructions of different categories: LDMR stores all LDMR instructions; SVMR stores all SVMR instructions; and ALU stores all other instructions. All three IQs are in ln-order, meaning they can be executed out of order.

[0767] The `OP_param_table` stores the parameters of all operators. The `Retire` module accepts instructions to be executed from `DISP` and receives signals indicating the completion of instruction execution from the three `IQ` blocks, thus completing the instruction retire operation. Once all instructions have been retired, a signal indicating that `DISP` is empty is sent.

[0768] 2.3.4 Mtx Reg a, Mtx Reg b, Mtx Reg c, Br Reg b, Br Reg c

[0769] Mtx Reg a, Mtx Reg b, Mtx Reg c, Br Reg b, and Br Reg c are all BRAMs in the FPGA, used to store Weight, Bias, Feature Map data, and intermediate layer calculation results during neural network computation. In the actual FPGA implementation, Mtx Reg a stores the input and output feature map data of each layer, which is used by the MPU, VPU, and VPUTY modules for computation; Mtx Reg b and Br Reg b store the Weight and Bias data required for Convolution operations, respectively, which are used by the MPU and VPU modules for computation; Mtx Reg c and Br Reg c store the Weight and Bias data required for Depthwise Convolution operations, respectively, which are used by the VPUTY module for computation.

[0770] 2.3.5 Download_data module

[0771] The main function of the Download_data module is to receive and download the Weight, Bias, and image data required for calculation from external sources to the corresponding addresses in the DDR. The process is as follows: First, the RISC-V core sends a download parameter configuration command through the Regmap module. In the Download_data module, the interface signals are parsed to obtain parameters related to the download process, such as the starting address and total length of Weight and Bias to be written to the DDR. Then, the external Weight, Bias, and image data are input, processed by FIFO (First Input First Output) in the Download_data module, and integrated into 512-bit wide data (DDR data width) before being written to the configured DDR address for subsequent HiPU calculations.

[0772] 2.3.6 Upload_data module

[0773] The main function of the Upload_data module is to output the calculation results stored at the corresponding address in DDR to the external HiPU_TOP for further use. The process is as follows: after the calculation is completed, the RISC-V core first issues the upload parameter configuration command through the Regmap module. In the Upload_data module, the interface signal from Regmap is parsed to obtain the DDR starting address and total length of the data to be uploaded. Then, a read command is issued to DDR to obtain the required data and write it to the FIFO. After the external device is ready, the data is sent out from the FIFO to the outside.

[0774] 2.3.7 Load_MtxReg_ctrl

[0775] The Load_MtxReg_ctrl module moves the Weight, Bias, and feature map data required for each layer's computation from the corresponding DDR address to the designated on-chip Local Memory before the neural network computation, for use by the HiPU computation core. Its execution process is as follows: The RISC-V core issues a load data command through the Regmap module. The LDMR instruction is sent to the Load_MtxReg_ctrl module via DISP and IQ (LDMR) through interface signals. Within this module, the interface signals are parsed to obtain the parameters shown in Table 2. Subsequently, this module moves data of length LDMR_TRANS_LEN to the target MR of the target HiPU_CORE according to the DDR starting address in the parameters. Simultaneously, it selects whether to perform format rearrangement when loading the input image data based on the parameter configuration. The parameter configuration table is shown in Table 2 below.

[0776] Table 2

[0777]

[0778]

[0779] 2.3.8 Save_MtxReg_ctrl

[0780] The Save_MtxReg_ctrl module's function is to move the calculated output feature maps stored in LocalMemory to the corresponding DDR address after each layer's computation in the neural network, so that the HiPU core can call them for the next layer's computation. Its execution process is as follows: The RISC-V core issues a Save data command through the Regmap module. The SVMR instruction is sent to the Save_MtxReg_ctrl module via DISP and IQ (SVMR) through interface signals. Within this module, the interface signals are parsed to obtain the parameters shown in Table 3. Subsequently, this module moves the intermediate layer results from the indexed LocalMemory to the corresponding DDR starting address using data of length SVMR_TRANS_LEN. The parameter configuration table is shown in Table 3 below.

[0781] Table 3

[0782] parameter describe SVMR_MR_IND_SRC Data source: MR index address SVMR_MR_ADDR_SRC Data source: MR's internal address SVMR_CORE_SRC Within which HiPU_CORE is the data source MR? SVMR_PIC_REORDER_EN Does the image data need to be rearranged during saving? SVMR_ADDR_DEST The starting address of the save data in DDR SVMR_TRANS_LEN The length of the saved data (in 64 bytes)

[0783] 2.3.9 HiPU Computing Core Design

[0784] HiPU_CORE is a module that performs complex neural network operations. Multiple modules can operate in parallel within HiPU. Each CORE mainly contains modules such as MPU, VPU, and VPUTY that process different data formats, as well as partitioned Block Memory for storing temporary data.

[0785] At the start of computation, the RISC-V core issues instructions via Regmap, configuring parameters such as the width and number of channels of the input feature map, and the width and height of Weights and Bias, into the memory `param_table` that stores computational parameters, thereby controlling the computational operations in HPU_CORE. The VPU primarily implements vector multiplication, addition, comparison, and shift operations for convolution computation; the MPU primarily implements matrix multiplication and accumulation for convolution computation, and its functions include... Figure 5 As shown, the element-wise convolution operation in the neural network is computed by this module.

[0786] VPUTY primarily implements depth-wise convolution operations and pooling operations. The parameters required for these operations, related to input / output feature maps, weights, and bias, are pre-configured in the `param_table` via instructions. The specific implementations of depth-wise and pooling operations are as follows: Figure 6 As shown.

[0787] 2.3.10 VR

[0788] VR stands for Vector Register, which is also composed of Block Memory. Its function is to store the intermediate results of matrix multiplication and accumulation operations performed by the MPU in convolution, so that the VPU can call them when performing the next vector operation related to Bias.

[0789] 2.3.11 BBOX

[0790] The BBOX module transforms the results of the final layer of a neural network into the required data format. For example, assuming the feature map output from the final layer has the data format shown in the figure, the feature map size is 8*8*32 channels. The first 16 channels contain information about the confidence level of the detected target, with each pre-selected box representing conf, class1, class2, and zero, respectively. The last 16 channels contain information about the coordinates of the detected target boxes, with each pre-selected box representing Δx, Δy, Δw, and Δh, respectively. All output data is 8-bit signed data.

[0791] See Figure 6Aand Figure 6B , Figure 6A This illustrates the data format of the feature map output from the last layer of the neural network. Figure 6B This illustrates the data format after processing by the BBOX module:

[0792] Figure 6A In this algorithm, the first 16 channels contain information about object detection probabilities. The data `conf` is scaled and passed through a sigmoid function to obtain the probability that an object is contained in the preselected bounding box. The data `cls1` and `cls2` are scaled and used as input to a softmax function to obtain the probabilities of the object being class 1 and class 2, respectively. The output of the softmax function is multiplied by the output of the sigmoid function to obtain the probabilities of class 1 and class 2 being detected in the preselected bounding box. The larger of these two probabilities is taken as the final output probability of the detected object. If the probability of class 1 is greater than that of class 2, the detected object class `type` is 8 bits of data 0; otherwise, the detected object class `type` is 8 bits of data 1. The last 16 channels contain information about the coordinates of the target detection box. The data Δx, Δy, Δw, and Δh are used to obtain the coordinates of the center point of the preselected box, as well as the width and height of the preselected box, using the following formula. Here, anchor_x, anchor_y, anchor_w, and anchor_h are pre-defined anchor box parameters:

[0793] x = anchor_x + Δx * anchor_w

[0794] y = anchor_y + Δy * anchor_h

[0795]

[0796]

[0797] Using the coordinates of the center point, width, and height of the preselected box, calculate the coordinates (xmin, ymin) of the top-left vertex and the coordinates (xmax, ymax) of the bottom-right vertex. Note: To protect w and h from exponential explosion and exceeding their range, the function y = e^x is used when Δw and Δh are less than 1, and the proportional function y = e^x is used when Δw and Δh are greater than 1. The data format obtained after processing the output of the last layer of the neural network by this module is as follows. Figure 6B As shown.

[0798] 2.3.12 Interface Design

[0799] Except for the DDR interface, which uses the AXI4 bus interface protocol, all internal interfaces are designed using the following custom bus protocol. See [link / reference] Figure 7 As shown.

[0800] When the read and write channels are merged, the bus transmission becomes two types of signal groups: the Master sends requests to the Slave, and the Slave sends feedback to the Master.

[0801] After read and write commands are merged, the `we` signal indicates whether the current command is a read or write operation. If there are requirements for bus locking, atomic operations, etc., these need to be agreed upon by both parties and implemented through the `user_defined` signal.

[0802] Regarding ordering, returned data and response information must be strictly ordered. Writing data also requires receiving a response signal, and the data must be in complete order with the data returned by the read command.

[0803] The CLB signals are summarized in Table 4 below:

[0804] Table 4

[0805]

[0806]

[0807] 2.3.13 Neural Network Post-processing Design

[0808] Typical neural network processor architectures include Figure 8As shown, the control scheduling logic controls the data transfer between Global Memory and DDR, and performs corresponding PE array calculations. After the calculations are complete, the final layer result of the neural network is written to DDR, and then the host is notified to read the data from DDR. Post-processing operations are then performed on the host. Common post-processing operations for target recognition networks include calculating target coordinates and performing non-maximum suppression calculations. For a powerful host, such post-processing will take less than 1ms; however, for edge devices, most processors cannot compare to x86 hosts and are at the embedded processor level. In this case, the post-processing time may reach about 2-7ms, severely impacting the frame rate of target recognition. Therefore, in applications requiring high frame rates, this post-processing computation needs to be accelerated. A common acceleration method is to directly embed it into hardware. However, this method is very inflexible. If the network or the computation method changes, modifying the embedded hardware will require a huge investment. This disclosure adopts the following structure, adding a microprocessor on top of Global Memory. Typically, such a microprocessor occupies very few resources on an FPGA. By utilizing the programmability of the microprocessor, this disclosure can handle a large number of post-processing tasks.

[0809] In this disclosure, we first establish a data path between the microprocessor and Local Memory, enabling the microprocessor to access Global Memory in 4B or B-level operations. After the neural network computation is completed, the control scheduling module writes the computation result of the last layer of the neural network into Global Memory and notifies the microprocessor to perform post-processing computation. After the microprocessor performs the post-processing computation, it writes the post-processing computation result back into Global Memory and notifies the host processor to retrieve it from Global Memory, or directly sends the post-processing computation result to the host processor through interface logic for the host processor to make a decision.

[0810] The specific FPGA implementation process described in this disclosure is as follows: After the HiPU_CORE computing core writes the calculation result of the last layer of the neural network into Mtx Reg a, it notifies the RISC-V core to perform the next nonmaximum suppression post-processing calculation (NMS); the RISC-V core calls the last layer data stored in it through the direct interface with Mtx Reg a to perform post-processing calculation, and after the calculation is completed, it writes the result back to Mtx Reg a for further use.

[0811] The hardware storage formats disclosed in the three publications

[0812] Regarding the storage format disclosed in this disclosure, which is used to implement the rearrangement of the organization format in data storage by FM, it needs to meet the following conditions: the format has good locality, can improve the utilization of data in the cache, and improve data transmission bandwidth and computing performance.

[0813] For example, the storage format is a new format named HWC88 format.

[0814] For example, the HWC88 storage format is specifically as follows:

[0815] Divide a row or a portion of a row of FM data into 8 blocks. Place the data of the same channel group at the same position in each block at the same memory address, prioritizing the storage of all channels of the same pixel in each block.

[0816] For example, FM uses the HWC88 format for convolution operations as follows: the previous row of FM data is divided into 8 equal blocks to obtain 8 parallel points, and the data of the same channel group at the same position in each block is multiplied by the corresponding channel of the convolution kernel.

[0817] For example, FM uses the HWC88 format for depthwise convolution operations as follows: the 8 parallel points on FM are multiplied with the corresponding channels of the convolution kernel, the convolution kernel is copied into 8 copies and stored in the Block Memory for computation, and the data format before and after copying is the HWC8 format.

[0818] In other words, the HWC88 format disclosed in this disclosure is a new data storage format defined independently based on the HWC format.

[0819] Definition 1: Select 8 points with different W values ​​in the same row of the feature map. Each point has 8 channels, stored in one memory unit (64 bytes), and C and W are both multiples of 8. This explains the meaning of the last two "8"s in HWC88 compared to the HWC format, and provides one definition of the HWC format.

[0820] From another perspective, for FM data, the HWC88 format divides a line or a portion of a line of FM data into 8 equal blocks. Each block contains wi (wi = W / 8) data points. Then, the data of the same channel group (8 channels per group) at the same position in each block, a total of ci groups (ci = C / 8), are placed at the same memory address. Priority is given to storing all channels of the same pixel in each block.

[0821] The storage format of HWC88 format FM data is as follows: Figure 9 As shown.

[0822] An example of HWC88: Figure 9 As shown, in this example, W=48 and C=16. After splitting in the W and C directions, each block of data contains 6 numbers in the W direction (wi=6) and 2 groups in the C direction (ci=2).

[0823] The advantage of the HWC88 data storage format is that it has fewer restrictions on the C value compared to the HWC format, saving data storage space in most cases where padding with zeros is required. For example, for an RGB image with C=3, if W=60 and H=1, storing it in the HWC format requires 60 memory units; while storing it in the HWC88 format only requires 8 memory units.

[0824] Furthermore, the HWC88 format disclosed in this disclosure can also be defined as follows:

[0825] Definition 2: For FM data, firstly, the entire input data fm is divided into segments, such as... Figure 11 As shown, the data between the two baffles in the figure represents a segment of data to be processed. Then, following the method described in Definition 1, in the W direction, this segment of data fm is divided into 8 equal blocks, each containing wi (wi = W / 8). In the C direction, it is divided into ci groups based on 8 (ci = C / 8). Data from the same position and channel group in each block is placed in the same memory unit, prioritizing the storage of all channels of pixels at the same position in each block. In the example figure, Wp = 48, C = 8, and the values ​​are variable. According to the requirements of the HWC88 format, both Wp and C are multiples of 8.

[0826] To distinguish them, the HWC88 format described in Definition 1 is called the basic HWC88 format, and the HWC88 format described in Definition 2 is called the improved HWC88 format.

[0827] like Figure 12 As shown, in this example, W = 144, C = 16, and after being divided into 3 segments, each segment has Wp = 48. After being divided in the W and C directions, each block of data contains 6 numbers in the W direction (wi = 6) and 2 groups in the C direction (ci = 2).

[0828] The advantage of the improved HWC88 format is that once the algorithm network is determined, the limitation on the image or feature map size is smaller. Taking a feature map with W=712 as an example, if stored in the basic HWC88 format, the wi of each block is calculated (wi=W / 8=712 / 8=89), and then data from the same position and channel group in each block are placed in the same memory unit. However, this block wi may not be suitable for the convolution operation of subsequent layers of the network, which will introduce additional data storage format conversion requirements. With the improved HWC88 format, the Wp of each segment and the corresponding wi of the blocks within the segment can be determined from the algorithm before the blocks are divided. For example, if Wp=128 (corresponding to wi=128 / 8=16), then the segments are divided according to Wp=128 for each segment. The first 5 segments are complete segments, and the last segment has only 72 valid points. The missing parts are padded with 0, and then the data within the segment is divided into blocks, and data from the same position and channel group in each block are placed in the same memory unit. The key point is that, regardless of its definition, the HWC88 format is used to implement the rearrangement of the organization format in data storage by FM, and it needs to meet the following conditions: the format has good locality, can improve the utilization of data in the cache, and improve data transmission bandwidth and computing performance.

[0829] Furthermore, the HWC88 storage format can also be defined as follows:

[0830] If multiple images are processed in parallel during convolution, first take 8 images to be processed in parallel, and divide each row of the input data FM in the same row of each image into segments, such as... Figure 12A As shown, the data between the two gray baffles represents a segment of data to be processed. Each image is then divided into ci groups (ci = C / 8) along the C direction with a base of 8. Data from the same channel group at the same position in each image is placed in the same memory location, prioritizing the storage of all channels for pixels at the same position within each block. In the part_M-1 and part_M+1 portions of the image, all channels for points with the same n and w values ​​(as shown in the dashed box, all channels with n = 7 and w = 47) have been merged into a simplified representation. This HWC88 format is called the multi-batch HWC88 format, and its advantage is that there are no restrictions on the W direction of FM, as long as C is a multiple of 8.

[0831] Furthermore, it can be observed that the basic HWC88 format is a special case of the improved HWC88 format, where one line of data in an FM is divided into one segment, and Wp = W. The improved HWC88 format is an extension of the basic HWC88 format, especially for larger FMs.

[0832] In another embodiment, 8 channels are grouped together.

[0833] In another embodiment, the FM uses the HWC88 format for convolution operations as follows: the previous row of FM data is divided into 8 equal blocks to obtain 8 parallel points, and the data of the same channel group at the same position in each block is multiplied by the corresponding channel of the Kernel.

[0834] In this embodiment, Weight data (i.e., WT data) is stored in memory in HWC88 format, but the format of Weight may vary depending on the FM data format used during calculation and the type of calculation. Typically, WT data is formatted offline.

[0835] If FM uses the HWC88 format for convolution operations, the parallelism in the CH direction is 8, meaning 8 channels are grouped together. Simultaneously, the parallelism in the N direction is also 8, meaning 8 kernels are grouped together. WT stores the 8 channels of a corresponding group of kernels at a single address, such as... Figure 13 As shown, first store the 4 channels of the P0 point (H=0, W=0) of the first group of 8 kernels, until all 9 points of the first group of 8 kernels are stored, then start storing the data of the second group of 8 kernels.

[0836] 4 publicly available scalability and application scope

[0837] 2.4 Scalability

[0838] This disclosure is highly scalable. This is mainly reflected in the following aspects:

[0839] (1) Since RISC-V is an open architecture, the RISC-V control core in HiPU can be replaced with different cores according to the actual application requirements;

[0840] (2) The HiPU neural network accelerator can expand the HiPU_CORE computing core according to the FPGA resource availability, power consumption requirements, and processing speed requirements. In specific neural network calculations, this is manifested by dividing the height direction of the feature map into 2 equal parts. N The data is sent to each core for parallel computing, thus allowing for smooth scaling of computing power;

[0841] (3) The number of sub-operation cores and function allocation in HiPU_CORE can be optimized for different operators, thereby improving the overall computation efficiency.

[0842] 2.5 Application Scope

[0843] This disclosure has a wide range of applications, mainly including the following aspects:

[0844] (1) It can be efficiently applied to computation of neural networks such as ShuffleNet and MobileNet. It only requires the use of the matching toolchain to generate different parameters and configuration data such as result access addresses according to different network structures. At the same time, it can be specially adapted and adjusted for different neural networks, removing some unnecessary functions, reducing power consumption and hardware resource consumption;

[0845] (2) The HiPU's computational core HiPU_CORE and its Local Memory can be flexibly allocated according to the characteristics of different neural networks to increase the efficiency of core collaborative computation.

[0846] In summary, the features of this disclosure are as follows:

[0847] (1) The RISC-V core is used as the control center of the neural network accelerator to schedule the FPGA to perform neural network operations;

[0848] (2) Propose the overall control system design for HiPU;

[0849] (3) Propose corresponding interface design and computing core design;

[0850] (4) Propose a corresponding neural network post-processing design;

[0851] (5) A new complex instruction set and its encoding method were proposed.

[0852] Although the embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this disclosure is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this disclosure, and all of these are within the scope of protection of this disclosure.

Claims

1. A RISC-V core system based on a complex instruction set, characterized in that: The RISC-V core, based on the complex instruction set, i.e., the CISC instruction set, serves as the control core for data loading and computation of each layer in the neural network accelerator. At the same time, under the control of the RISC-V core, the input and output data of the network are rearranged according to the hardware storage format. in, The rearrangement specifically includes the following steps: If each convolution requires m points and n channels of data, then during rearrangement: In the first column, first arrange the m*n numbers involved from the first point to the mth point from bottom to top; Furthermore, if the convolution stride is k, then when rearranging from left to right to the second column: the data of the n channels of the (k+1)th point are first arranged from the bottom; then, the (k+2)th point is arranged sequentially from bottom to top, all the way up to the (k+m)th point; Furthermore, when rearranging to the (i+1)th column, the data from the n channels at the i*k+1, i*k+2, …, i*k+m points are arranged sequentially from bottom to top.

2. The RISC-V core system according to claim 1, wherein, If each convolution requires N data points, where N corresponds to the computational parallelism of the neural network accelerator, then when N is greater than m*n channels of data, each column from the first column to the second-to-last column can be padded with N-(m*n) zeros.

3. The RISC-V core system according to claim 2, wherein, For the last column, add NM zeros based on the actual number M of channel data in the last column.

4. An FPGA neural network accelerator based on RISC-V scheduling, characterized in that: The neural network accelerator includes the RISC-V core system as described in claim 1.

5. The neural network accelerator according to claim 4, wherein, The neural network accelerator includes a control layer, a computation layer, and a storage layer; The control layer includes a CPU control core, a data memory, and a code memory; The computation layer includes a convolution calculation core, a point-by-point processing operation core, and a data format conversion core; The storage layer includes a BRAM (Block Random Access Memory) storage area for feature maps, a BRAM storage area for parameters, a data storage control module, and a DDR storage area.

6. The neural network accelerator according to claim 5, wherein, The DDR storage area stores all feature parameters of a deep neural network, the input image, the output result, and the feature map data of the intermediate layers. The BRAM storage area uses swap-in / swap-out rules to store the feature map and parameter information required for the current calculation in the BRAM storage area of ​​the feature map and the BRAM storage area of ​​the parameters. Based on the different characteristics of the data, the BRAM area stores the feature map, the weight portion of the network parameters, and the bias portion of the network parameters in different locations. The feature map requires bidirectional operations from BRAM to DDR, while the network parameters only need to be loaded from the DDR storage area to the corresponding BRAM storage area. The data bit width of the bias portion is lower than that of the weight portion, so it is also stored separately. In this way, the utilization of FPGA internal wiring resources is significantly reduced through refined data regional management.

7. The neural network accelerator according to claim 5, wherein, The data format conversion core is used to convert HWC format to another format; the other format is HWC88 format.

8. The neural network accelerator according to claim 5, wherein, The neural network accelerator uses CISC instructions to configure parameters and control and schedule neural network computations. VSCALE writes the parameter configuration to the DISP module through the Regmap Mgr module. The DISP module is responsible for decoupling all parameters and control instructions and sending them to the IQ queue. The IQ queue then sends them to the corresponding execution control module, which then parses and calls the corresponding computation unit to complete the calculation. The Retire module is responsible for retiring the corresponding CISC commands, thereby enabling VSCALE to control and issue new parameters. The Score Board is used to record all CISC instructions, thereby enabling corresponding decoupling processing.

Images