Memory device and method of operating the same

Abstract

The present disclosure provides a memory device and an operation method thereof. The memory device includes: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors, and a plurality of inverters, the plurality of first transistors and the plurality of second transistors being paired; and a controller coupled to the decoding circuit, wherein each pair of the plurality of first transistors and the plurality of second transistors of the paired first transistors and second transistors are respectively coupled to one of the plurality of inverters, and are respectively coupled to one of a plurality of regional bit lines or one of a plurality of regional source lines; the plurality of first transistors are coupled to a global bit line; and the plurality of second transistors are coupled to a global source line.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operation method thereof. Background Art

[0002] In modern people's life, electronic products are ubiquitous. In electronic products, memories are also important components. Recently, the demand for high storage density memories has been increasing. To increase the storage density, three-dimensional architecture memories have gradually become the focus of memory manufacturers.

[0003] However, to meet future system requirements, it is imperative to improve memory performance.

[0004] Disclosure

[0005] According to an example of the present disclosure, a memory device is provided, including: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors, and a plurality of inverters, the plurality of first transistors and the plurality of second transistors being paired; and a controller coupled to the decoding circuit, wherein each pair of the plurality of first transistors and the plurality of second transistors of the pair are respectively coupled to one of the plurality of inverters, and respectively coupled to one of a plurality of regional bit lines or one of a plurality of regional source lines; the plurality of first transistors are coupled to a global bit line; and the plurality of second transistors are coupled to a global source line.

[0006] According to another example of the present disclosure, an operation method of a memory device is provided, including: controlling a plurality of regional source lines and a plurality of regional bit lines by a plurality of paired first transistors and a plurality of second transistors, wherein the plurality of first transistors and the plurality of second transistors are triode transistors; the plurality of first transistors are coupled to a global bit line; and the plurality of second transistors are coupled to a global source line.

[0007] To better understand the above and other aspects of the present disclosure, specific embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows: Brief Description of the Drawings

[0008] Figure 1 A functional block diagram of a memory device according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A circuit architecture diagram of a memory device according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A schematic diagram of a read operation of a memory device according to an embodiment of the present disclosure is shown.

[0011] Figure 4 Shows a schematic diagram of a first programming operation of a memory device according to an embodiment of the present disclosure.

[0012] Figure 5A And Figure 5B Schematic diagrams of five types of cells respectively showing a selected layer and an unselected layer.

[0013] Figure 6 Shows a schematic diagram of a second programming operation of a memory device according to an embodiment of the present disclosure.

[0014] Figure 7 Shows a schematic diagram of a byte erase operation of a memory device according to an embodiment of the present disclosure.

[0015] Figure 8 Shows a schematic diagram of a block erase operation of a memory device according to an embodiment of the present disclosure.

[0016] Description of reference numerals

[0017] 100: Memory device

[0018] 110: Memory array

[0019] 120: Decoding circuit

[0020] 130: Controller

[0021] 210: Decoding unit

[0022] 230: Inverter unit

[0023] 210A: Region source line decoder

[0024] 210B: Region bit line decoder

[0025] BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P, MNS0[0] to MNS0[3] and MPS0[0] to MPS0[3], MNS1[0] to MNS1[3] and MPS1[0] to MPS1[3]: Transistors

[0026] IN_B0 to IN_B3 and IN_S0 to IN_S3: Inverters

[0027] LBL0 to LBL3: Region bit lines

[0028] LSL0 to LSL3: Region source lines

[0029] GSL, GSLN: Global source lines

[0030] GBL, GBLN: Global bit lines

[0031] WL0_0, WL0_1, WL1_0, WL1_1: Word lines

[0032] MC: Memory cell

[0033] SMC: Target memory cell Detailed implementation manners

[0034] The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the explanations or definitions of these terms shall prevail. Each embodiment of the present disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0035] Figure 1 Show a functional block diagram of a memory device according to an embodiment of the present disclosure. A memory device 100 according to an embodiment of the present disclosure includes: a memory array 110, a decoding circuit 120, and a controller 130. The decoding circuit 120 is coupled to the memory array 110 and the controller 130. The controller 130 controls the memory array 110 and the decoding circuit 120 to perform read operations, programming operations, byte erase operations, sector erase operations, etc. The details will be described below.

[0036] Figure 2 Show a circuit architecture diagram of a memory device according to an embodiment of the present disclosure. The decoding circuit 120 includes: a decoding unit 210 and an inverter unit 230.

[0037] The decoding unit 210 includes a plurality of bit line transistors and a plurality of source line transistors. The decoding unit 210 includes a regional source line decoder 210A and a regional bit line decoder 210B. In Figure 2 it, the decoding unit 210 is described by taking the decoding unit 210 including 8 bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and 8 source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P as an example, but it should be understood that the present disclosure is not limited thereto. The regional source line decoder 210A includes source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P. The regional bit line decoder 210B includes bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P.

[0038] In one embodiment of the present disclosure, the multiple bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and the multiple source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P are manufactured by triple well technology.

[0039] The inverter unit 230 includes multiple inverters. In Figure 2 , taking the inverter unit 230 including 8 inverters IN_B0 to IN_B3 and IN_S0 to IN_S3 as an example for illustration, it should be understood that the present disclosure is not limited thereto. The multiple inverters IN_B0 to IN_B3 and IN_S0 to IN_S3 include transistors MNS0[0] to MNS0[3] and MPS0[0] to MPS0[3], MNS1[0] to MNS1[3] and MPS1[0] to MPS1[3].

[0040] In Figure 2 , the multiple bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P are respectively coupled to the memory array 110 through the regional bit lines LBL0 to LBL3.

[0041] In Figure 2 , the multiple source line transistors SLT0_N to SLT3_N and SLT0_P to SLT3_P are respectively coupled to the memory array 110 through the regional source lines LSL0 to LSL3.

[0042] That is to say, in the embodiment of the present disclosure, each regional source line LSL0 to LSL3 and each regional bit line LBL0 to LBL3 are controlled by a pair of MOS transistors (bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P).

[0043] The bit line transistor BLT0_N has one end coupled to the global source line GSL, the other end coupled to the regional bit line LBL0, and the control end coupled to the output of the inverter IN_B0. The coupling relationships of the bit line transistors BLT1_N to BLT3_N are similar and will not be elaborated here.

[0044] The bit line transistor BLT0_P has one end coupled to the global bit line GBL, the other end coupled to the regional bit line LBL0, and the control end coupled to the output of the inverter IN_B0. The coupling relationships of the bit line transistors BLT1_P to BLT3_P are similar and will not be elaborated here.

[0045] Similarly, the source line transistor SLT0_N has one end coupled to the global source line GSL, the other end coupled to the regional source line LSL0, and the control end coupled to the output of the inverter IN_S0. The coupling relationships of the source line transistors SLT1_N to SLT3_N are similar and will not be elaborated here.

[0046] The source line transistor SLT0_P has one end coupled to the global bit line GBL, the other end coupled to the regional source line LSL0, and the control end coupled to the output of the inverter IN_S0. The coupling relationships of the source line transistors SLT1_P to SLT3_P are similar and will not be elaborated here.

[0047] In the inverter unit 230, the gates of the transistors MNS0[0] to MNS0[3] receive the control signals ZS0 to ZS3 respectively. The sources of the transistors MNS0[0] to MNS0[3] are coupled to the bias voltage Vns. The drains of the transistors MNS0[0] to MNS0[3] are coupled to the output terminals SPN0 to SPN3.

[0048] Similarly, in the inverter unit 230, the gates of the transistors MPS0[0] to MPS0[3] receive the control signals ZS0 to ZS3 respectively. The sources of the transistors MPS0[0] to MNP0[3] are coupled to the bias voltage Vps. The drains of the transistors MPS0[0] to MPS0[3] are coupled to the output terminals SPN0 to SPN3.

[0049] In the inverter unit 230, the gates of the transistors MNS1[0] to MNS1[3] receive the control signals ZB0 to ZB3 respectively. The sources of the transistors MNS1[0] to MNS1[3] are coupled to the bias voltage Vnb. The drains of the transistors MNS1[0] to MNS1[3] are coupled to the output terminals BPN0 to BPN3.

[0050] Similarly, in the inverter unit 230, the gates of the transistors MPS1[0] to MPS1[3] receive the control signals ZB0 to ZB3 respectively. The sources of the transistors MPS1[0] to MNP1[3] are coupled to the bias voltage Vpb. The drains of the transistors MPS1[0] to MPS1[3] are coupled to the output terminals BPN0 to BPN3.

[0051] The control signals ZB0 to ZB3 are decoding information. In the selected tier, BPN0 to BPN3 control the gate voltages of the transistors BLT0_N to BLT3_N and the gate voltages of the transistors BLT0_P to BLT3_P.

[0052] Similarly, the control signals ZS0 to ZS3 are decoding information. In the selected layer, SPN0 to SPN3 control the gate voltages of transistors SLT0_N to SLT3_N and the gate voltages of transistors SLT0_P to SLT3_P.

[0053] The bases of transistors MNS0[0] to MNS0[3] are coupled to the well voltage Vpwell_s. The bases of transistors MNS1[0] to MNS1[3] are coupled to the well voltage Vpwell_b.

[0054] The bases of transistors MPS0[0] to MPS0[3] are coupled to the well voltage Vnwell_s. The bases of transistors MPS1[0] to MPS1[3] are coupled to the well voltage Vnwell_b.

[0055] In an embodiment of the present disclosure, the plurality of transistors MNS0[0] to MNS0[3] share the P well PW_SLT; the plurality of transistors MPS0[0] to MPS0[3] share the N well NW_SLT; the plurality of transistors MNS1[0] to MNS1[3] share the P well PW_BLT; and the plurality of transistors MPS1[0] to MPS1[3] share the N well NW_BLT.

[0056] In an embodiment of the present disclosure, the overall source line GSL can be selectively coupled to the well voltage Vpwell_b. Alternatively, in an embodiment of the present disclosure, the overall source line GSL can be selectively coupled to the well voltage Vpwell_s.

[0057] In an embodiment of the present disclosure, the overall bit line GBL can be selectively coupled to the well voltage Vnwell_b. Alternatively, in an embodiment of the present disclosure, the overall bit line GBL can be selectively coupled to the well voltage Vnwell_s.

[0058] The overall bit line GBL is coupled to the plurality of PMOS transistors SLT0_P to SLT3_P and BLT0_P to BLT3_P. The overall source line GSL is coupled to the plurality of NMOS transistors SLT0_N to SLT3_N and BLT0_N to BLT3_N.

[0059] In an embodiment of the present disclosure, to avoid a forward diode, the voltage setting conditions can be as shown in Table 1 below:

[0060] Table 1

[0061]

[0062]

[0063] In "S / B common" of Table 1, S represents source, B represents body, and "S / B common" represents that the source is coupled to the body, and the source and the body have the same voltage (Vsb = 0V) to avoid the body effect. As can be seen from Table 1, in the embodiments of the present disclosure, the voltages of these multiple nodes should be lower than the N-well voltages Vnwell_b and Vnwell_s in principle, and, the voltages of these multiple nodes should be higher than the P-well voltages Vpwell_b and Vnwell_s in principle. Or rather, in the embodiments of the present disclosure, the P-well voltages Vpwell_b and Vnwell_s should be set to be the lowest voltages among these voltages, while the N-well voltages Vnwell_b and Vnwell_s should be set to be the highest voltages among these voltages.

[0064] Figure 3 Shows a schematic diagram of a read operation of a memory device according to an embodiment of the present disclosure. When performing a read operation, the voltage setting conditions are as shown in Table 2 below.

[0065] Table 2

[0066] Voltage (V) GBLN 1 GSLN 0 Selected Word Line 5～7 Unselected Word Line 0 Vps 1.8 Vns 0 Vnwell_s 1.8 Vpwell_s 0 Vpb 1.8 Vnb 0 Vnwell_b 1.8 Vpwell_b 0

[0067] In Figure 3 Take the word line WL0_0 as the selected word line and other word lines (such as WL0_1, WL1_0, WL1_1) as unselected word lines as an example for illustration.

[0068] As for the voltage settings of the bit line transistors BLT0_N~BLT3_N and BLT0_P~BLT3_P, and the source line transistors SLT0_N~SLT3_N, SLT0_P~SLT3_P, they will be described as follows.

[0069] When the gate voltages of the NMOS source line transistors SLT0_N~SLT3_N are set to a high potential (such as 1.8V), for example but not limited to, the NMOS source line transistors SLT0_N~SLT3_N are turned on; conversely, when the gate voltages of the NMOS source line transistors SLT0_N~SLT3_N are set to a low potential (such as 0V), for example but not limited to, the NMOS source line transistors SLT0_N~SLT3_N are turned off.

[0070] When the gate voltages of the PMOS source line transistors SLT0_P~SLT3_P are set to a high potential (such as 1.8V), for example but not limited to, the PMOS source line transistors SLT0_P~SLT3_P are turned off; conversely, when the gate voltages of the PMOS source line transistors SLT0_P~SLT3_P are set to a low potential (such as 0V), for example but not limited to, the PMOS source line transistors SLT0_P~SLT3_P are turned on.

[0071] When the gate voltages of the NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, to a high potential (such as 1.8 V), the NMOS bit line transistors BLT0_N to BLT3_N are turned on; conversely, when the gate voltages of the NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, to a low potential (such as 0 V), the NMOS bit line transistors BLT0_N to BLT3_N are turned off.

[0072] When the gate voltages of the PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, to a high potential (such as 1.8 V), the PMOS bit line transistors BLT0_P to BLT3_P are turned off; conversely, when the gate voltages of the PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, to a low potential (such as 0 V), the PMOS bit line transistors BLT0_P to BLT3_P are turned on.

[0073] Through the above voltage control, the target memory cell SMC can be read. Specifically, during reading, the bit line transistors BLT0_N to BLT2_N are turned on and the bit line transistor BLT3_N is turned off; the bit line transistors BLT0_P to BLT2_P are turned off, and the bit line transistor BLT3_P is turned on. Thereby, the voltage of the overall bit line GBLN (= 1 V) can be transmitted to the target memory cell SMC through the turned-on bit line transistor BLT3_P.

[0074] Similarly, during reading, the source line transistors SLT0_N to SLT3_N are turned on; the source line transistors SLT0_P to SLT3_P are turned off. Thereby, the voltage of the overall source line GSLN (= 0 V) can be transmitted to the target memory cell SMC through the turned-on source line transistor SLT3_N.

[0075] During reading, the regional bit lines (such as LBL0 to LBL2) and the regional source line LSL (such as LSL0 to LSL2) coupled to the unselected memory cells are, for example but not limited to, 0 V; and the regional bit line (such as LBL3) coupled to the selected memory cell is, for example but not limited to, 1 V, and the regional source line LSL (such as LSL3) coupled to the selected memory cell is, for example but not limited to, 0 V.

[0076] Since the gate voltage of the target memory cell SMC is 5V to 7V, while its source voltage is 1V (the voltage of LBL3), VGS = 5V to 7V, the target memory cell SMC can be turned on and read. In addition, since all the regional source lines LSL0 to LSL3 are forced to 0V by the global source line GSL, only the target memory cell SMC coupled to the selected regional bit line LBL3 and the selected word line (WL0_0) can be accessed, while other memory cells MC cannot be turned on.

[0077] When current flows through the target memory cell SMC, the current will flow to the sense amplifier and be converted into a voltage signal, which is compared with a reference voltage. If the voltage signal is higher than the reference voltage, the target memory cell SMC is determined to be in a low threshold state. Conversely, if the voltage signal is lower than the reference voltage, the target memory cell SMC is determined to be in a high threshold state.

[0078] That is to say, in an embodiment of the present disclosure, during reading, the regional source line decoder 210A conducts the global source line voltage to a first target memory cell of the plurality of memory cells; and the regional bit line decoder 210B conducts a global bit line voltage to the first target memory cell.

[0079] Figure 4 Shows a schematic diagram of the first programming operation of a memory device according to an embodiment of the present disclosure. During the first programming, the voltage setting conditions are as shown in Table 3 below.

[0080] Table 3

[0081]

[0082]

[0083] In Figure 4 taking the word line WL0_0 as the selected word line and other word lines (such as WL0_1, WL1_0, WL1_1) as the unselected word lines as an example for illustration.

[0084] As for the voltage settings of the bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and the source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P, they will be described later.

[0085] When the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, a high potential (such as 4V), the NMOS source line transistors SLT0_N to SLT3_N are turned on; conversely, when the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, a low potential (such as -10V), the NMOS source line transistors SLT0_N to SLT3_N are turned off.

[0086] When the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, a high potential (such as 4V), the PMOS source line transistors SLT0_P to SLT3_P are turned off; conversely, when the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, a low potential (such as -10V), the PMOS source line transistors SLT0_P to SLT3_P are turned on.

[0087] When the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, a high potential (such as 4V), the NMOS bit line transistors BLT0_N to BLT3_N are turned on; conversely, when the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, a low potential (such as -10V), the NMOS bit line transistors BLT0_N to BLT3_N are turned off.

[0088] When the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, a high potential (such as 4V), the PMOS bit line transistors BLT0_P to BLT3_P are turned off; conversely, when the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, a low potential (such as -10V), the PMOS bit line transistors BLT0_P to BLT3_P are turned on.

[0089] Through the above voltage control, the first programming operation can be performed on the target memory cell SMC. Specifically, when performing the first programming operation, the bit line transistors BLT0_N to BLT2_N are turned off and the bit line transistor BLT3_N is turned on; the bit line transistors BLT0_P to BLT2_P are turned on, and the bit line transistor BLT3_P is turned off. Therefore, the turned-on bit line transistor BLT3_N transfers the voltage of the overall source line GSLN (= -10V) to the target memory cell SMC through the regional bit line LBL3.

[0090] Similarly, during the first programming, the source line transistors SLT0_N to SLT2_N are turned off; the source line transistor SLT3_N is turned on; the source line transistors SLT0_P to SLT2_P are turned on while the source line transistor SLT3_P is turned off. Therefore, the turned-on source line transistor SLT3_N transfers the voltage of the overall source line GSLN (= -10V) to the target memory cell SMC through the local source line LSL3.

[0091] During the first programming, the local bit lines (such as LBL0 to LBL2) coupled to the unselected memory cells and the local source lines LSL (such as LSL0 to LSL2) are, for example but not limited to, 4V; and, the local bit line (such as LBL3) coupled to the selected memory cell is, for example but not limited to, -10V, while the local source line LSL (such as LSL3) coupled to the selected memory cell is, for example but not limited to, -10V.

[0092] Hereinafter, for convenience of explanation, the memory cells are classified into five types: T cells, A cells, B cells, C cells, and D cells. A T cell represents a memory cell coupled to a selected word line and a selected local bit line / local source line. An A cell represents a memory cell coupled to an unselected word line and a selected local bit line / local source line (on the same layer as the T cell). A B cell represents a memory cell coupled to a selected word line and an unselected local bit line / local source line. A C cell represents a memory cell coupled to an unselected word line and a selected local bit line / local source line (on a different layer from the T cell). A D cell represents a memory cell coupled to an unselected word line and an unselected local bit line / local source line. That is, the T cell is the selected cell, while the A cells, B cells, C cells, and D cells are unselected cells.

[0093] For ease of understanding, please refer to Figure 5A and Figure 5B 。 Figure 5A and Figure 5B which respectively show schematic diagrams of the five types of cells in the selected layer and the unselected layer.

[0094] Based on the above definitions, in the embodiments of the present disclosure, during the first programming operation, the VGS voltage across the selected T cell is 23V (13V - (-10V)); the VGS voltage across the unselected A cell is 9V (-1V - (-10V)); the VGS voltage across the unselected B cell is 9V (13V - (4V)); the VGS voltage across the unselected C cell is 9V (-1V - (-10V)); and, the VGS voltage across the unselected D cell is -5V (-1V - (4V)).

[0095] That is to say, in an embodiment of the present disclosure, during the first programming, the regional source line decoder 210A conducts the overall source line voltage to a second target memory cell among the multiple memory cells; and the regional bit line decoder 210B conducts the overall source line voltage to the second target memory cell.

[0096] In the embodiments of the present disclosure, since each regional bit line and each regional source line are coupled to paired PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the overall source line can send a very low voltage (such as -10V) to the selected regional bit line and the selected regional source line, while the voltages of the unselected regional bit line and the unselected regional source line can be relatively high (such as 4V, as long as it is not higher than the CMOS breakdown voltage (14V)). Therefore, in the embodiments of the present disclosure, PMOS transistors can be used to transmit high voltages (without body effect). In contrast, in the prior art, since NMOS transistors with body effect are used to transmit high voltages, the body effect in the prior art is relatively serious.

[0097] In addition, in the embodiments of the present disclosure, during the first programming operation, since each regional bit line and each regional source line are coupled to paired PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the voltages of the selected regional bit line and the selected regional source line can be transmitted simultaneously through the transistors. Therefore, in an embodiment of the present disclosure, the speed of the programming operation can be increased, and there will be no short-time transient stress issue at the start of the programming pulse.

[0098] Figure 6 Shows a schematic diagram of the second programming operation of a memory device according to an embodiment of the present disclosure. During the second programming, the voltage setting conditions are as shown in Table 4 below.

[0099] Table 4

[0100] Voltage (V) GBLN 6 GSLN -8 WL0_0 13 Other WLs -1 Vps 6 Vns -8 Vnwell_s 6 Vpwell_s -8 Vpb 6 Vnb -8 Vnwell_b 6 Vpwell_b -8

[0101] In Figure 6 taking the word line WL00 as the selected word line and other word lines (such as WL0_1, WL1_0, WL1_1) as unselected word lines as an example for illustration.

[0102] Regarding the voltage settings of bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, as well as source line transistors SLT0_N to SLT3_N and SLT0_P to SLT3_P, they are described as follows.

[0103] When the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, to a high potential (such as 6V), the NMOS source line transistors SLT0_N to SLT3_N are turned on; conversely, when the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, to a low potential (such as -8V), the NMOS source line transistors SLT0_N to SLT3_N are turned off.

[0104] When the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, to a high potential (such as 6V), the PMOS source line transistors SLT0_P to SLT3_P are turned off; conversely, when the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, to a low potential (such as -8V), the PMOS source line transistors SLT0_P to SLT3_P are turned on.

[0105] When the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, to a high potential (such as 6V), the NMOS bit line transistors BLT0_N to BLT3_N are turned on; conversely, when the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, to a low potential (such as -8V), the NMOS bit line transistors BLT0_N to BLT3_N are turned off.

[0106] When the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, to a high potential (such as 6V), the PMOS bit line transistors BLT0_P to BLT3_P are turned off; conversely, when the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, to a low potential (such as -8V), the PMOS bit line transistors BLT0_P to BLT3_P are turned on.

[0107] Through the above voltage control, a second programming operation can be performed on the target memory cell SMC. Specifically, when performing the second programming operation, the bit line transistors BLT0_N to BLT2_N are turned off and the bit line transistor BLT3_N is turned on; the bit line transistors BLT0_P to BLT2_P are turned on, and the bit line transistor BLT3_P is turned off. Therefore, the turned-on bit line transistor BLT3_N transfers the voltage of the overall source line GSLN (= -8V) to the target memory cell SMC through the regional bit line LBL3.

[0108] Similarly, when performing the second programming, the source line transistors SLT0_N to SLT2_N are turned off; the source line transistor SLT3_N is turned on; the source line transistors SLT0_P to SLT2_P are turned on and the source line transistor SLT3_P is turned off. Therefore, the turned-on source line transistor SLT3_N transfers the voltage of the overall source line GSLN (= -8V) to the target memory cell SMC through the regional source line LSL3.

[0109] When performing the second programming, the regional bit lines (such as LBL0 to LBL2) and the regional source line LSL (such as LSL0 to LSL2) coupled to the unselected memory cells are, for example but not limited to, 6V; and the regional bit line (such as LBL3) coupled to the selected memory cell is, for example but not limited to, -8V, and the regional source line LSL (such as LSL3) coupled to the selected memory cell is, for example but not limited to, -8V.

[0110] From the above definitions, in the embodiments of the present disclosure, when performing the second programming operation, the VGS voltage difference of the selected T cell is 21V (13V - (-8V)); the VGS voltage difference of the unselected A cell is 7V (-1V - (-8V)); the VGS voltage difference of the unselected B cell is 7V (13V - (6V)); the VGS voltage difference of the unselected C cell is 7V (-1V - (-8V)); and the VGS voltage difference of the unselected D cell is -7V (-1V - (6V)).

[0111] That is to say, in an embodiment of the present disclosure, when performing the second programming, the regional source line decoder 210A conducts the overall source line voltage to a third target memory cell of the plurality of memory cells; and the regional bit line decoder 210B conducts the overall source line voltage to the third target memory cell.

[0112] In the embodiments of the present disclosure, since each regional bit line and each regional source line are coupled to paired PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the overall source line can send a very low voltage (such as -8V) to the selected regional bit line and the selected regional source line, while the voltages of the unselected regional bit line and the unselected regional source line can be relatively high (such as 6V, as long as it is not higher than the CMOS breakdown voltage (14V)). Therefore, in the embodiments of the present disclosure, PMOS transistors can be used to transmit high voltages (without the body effect). In contrast, in the prior art, since NMOS transistors with the body effect are used to transmit high voltages, the body effect in the prior art is relatively serious.

[0113] In addition, in the embodiments of the present disclosure, during the second programming operation, since each regional bit line and each regional source line are coupled to paired PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the voltages of the selected regional bit line and the selected regional source line can be transmitted simultaneously through the transistors. Therefore, in an embodiment of the present disclosure, the speed of the programming operation can be increased, and there will be no short-term transient pressure problem at the start of the programming pulse.

[0114] Figure 7 The schematic diagram of the byte erasure operation of a memory device according to an embodiment of the present disclosure is shown. When performing byte erasure, the voltage setting conditions are as shown in Table 5 below.

[0115] Table 5

[0116] Voltage (V) GBLN 10 GSLN -4 WL0_0 -10 Other WLs 4 Vps 10 Vns -4 Vnwell_s 10 Vpwell_s -4 Vpb 10 Vnb -4 Vnwell_b 10 Vpwell_b -4

[0117] In Figure 7 taking the word line WL0_0 as the selected word line and other word lines (such as WL0_1, WL1_0, WL1_1) as unselected word lines as an example for illustration.

[0118] As for the voltage settings of the bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and the source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P, they will be described as follows.

[0119] When the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, a high potential (such as 10V), the NMOS source line transistors SLT0_N to SLT3_N are turned on; conversely, when the gate voltages of NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, a low potential (such as -4V), the NMOS source line transistors SLT0_N to SLT3_N are turned off.

[0120] When the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, a high potential (such as 10V), the PMOS source line transistors SLT0_P to SLT3_P are turned off; conversely, when the gate voltages of PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, a low potential (such as -4V), the PMOS source line transistors SLT0_P to SLT3_P are turned on.

[0121] When the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, a high potential (such as 10V), the NMOS bit line transistors BLT0_N to BLT3_N are turned on; conversely, when the gate voltages of NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, a low potential (such as -4V), the NMOS bit line transistors BLT0_N to BLT3_N are turned off.

[0122] When the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, a high potential (such as 10V), the PMOS bit line transistors BLT0_P to BLT3_P are turned off; conversely, when the gate voltages of PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, a low potential (such as -4V), the PMOS bit line transistors BLT0_P to BLT3_P are turned on.

[0123] Through the above voltage control, a byte erase operation can be performed on the target memory cell SMC. Specifically, during the byte erase operation, the bit line transistors BLT0_N to BLT2_N are turned on while the bit line transistor BLT3_N is turned off; the bit line transistors BLT0_P to BLT2_P are turned off, while the bit line transistor BLT3_P is turned on. Therefore, the turned-on bit line transistor BLT3_P transfers the voltage of the overall bit line GBLN (= 10V) to the target memory cell SMC through the regional bit line LBL3.

[0124] Similarly, during byte erasure, the source line transistors SLT0_N to SLT2_N are turned on; the source line transistor SLT3_N is turned off; the source line transistors SLT0_P to SLT2_P are turned off and the source line transistor SLT3_P is turned on. Therefore, the turned-on source line transistor SLT3_P transfers the voltage of the overall bit line GBLN (= 10V) to the target memory cell SMC through the local source line LSL3.

[0125] During byte erasure, the local bit lines (such as LBL0 to LBL2) coupled to the unselected memory cells and the local source lines LSL (such as LSL0 to LSL2) are, for example but not limited to, -4V; and, the local bit line (such as LBL3) coupled to the selected memory cell is, for example but not limited to, 10V, and the local source line LSL (such as LSL3) coupled to the selected memory cell is, for example but not limited to, 10V.

[0126] From the above definitions, in the embodiments of the present disclosure, during the byte erasure operation, the VGS voltage across the selected T cell is -20V (-10V - (10V)); the VGS voltage across the unselected A cell is -6V (4V - (10V)); the VGS voltage across the unselected B cell is -6V (-10V - (-4V)); the VGS voltage across the unselected C cell is -6V (4V - (10V)); and, the VGS voltage across the unselected D cell is 8V (4V - (-4V)).

[0127] That is to say, in an embodiment of the present disclosure, during the byte erasure operation, the local source line decoder 210A conducts the overall bit line voltage to a fourth target memory cell of the plurality of memory cells; and the local bit line decoder 210B conducts the overall bit line voltage to the fourth target memory cell.

[0128] In the embodiments of the present disclosure, since each local bit line and each local source line are coupled to pairs of PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the overall source line can send a very low voltage (such as -4V) to the selected local bit line and the selected local source line, while the voltages of the unselected local bit line and the unselected local source line can be higher (such as 10V, as long as it is not higher than the CMOS breakdown voltage (14V)). Therefore, in the embodiments of the present disclosure, PMOS transistors can be used to transfer high voltages (and without the body effect). In contrast, in the prior art, since NMOS transistors with the body effect are used to transfer high voltages, the body effect in the prior art is more serious.

[0129] In addition, in the embodiments of the present disclosure, during the byte erasing operation, since the bit lines and source lines of each region are coupled to paired PMOS and NMOS transistors (BLT0_N to BLT3_N and BLT0_P to BLT3_P, SLT0_N to SLT3_N, SLT0_P to SLT3_P), the voltages of the selected bit lines and source lines of the selected region can be transmitted through the transistors simultaneously. Therefore, in an embodiment of the present disclosure, the speed of the erasing operation can be increased, and there will be no short-time transient pressure problem at the start of the erasing pulse.

[0130] Figure 8 FIG. shows a schematic diagram of a block erasing operation of a memory device according to an embodiment of the present disclosure. When performing byte erasing, the voltage setting conditions are as shown in Table 6 below.

[0131] Table 6

[0132]

[0133]

[0134] In Figure 8 , taking the word lines WL0_0 and WL0_1 as the selected word lines and other word lines (such as WL1_0, WL1_1) as the unselected word lines as an example for illustration.

[0135] As for the voltage settings of the bit line transistors BLT0_N to BLT3_N and BLT0_P to BLT3_P, and the source line transistors SLT0_N to SLT3_N, SLT0_P to SLT3_P, they are as described later.

[0136] During block erasing, the gate voltages of the NMOS source line transistors SLT0_N to SLT3_N are set, for example but not limited to, a high potential (such as -4V) to turn off the NMOS source line transistors SLT0_N to SLT3_N; the gate voltages of the PMOS source line transistors SLT0_P to SLT3_P are set, for example but not limited to, a low potential (such as -4V) to turn on the PMOS source line transistors SLT0_P to SLT3_P; the gate voltages of the NMOS bit line transistors BLT0_N to BLT3_N are set, for example but not limited to, a high potential (such as -4V) to turn off the NMOS bit line transistors BLT0_N to BLT3_N; and the gate voltages of the PMOS bit line transistors BLT0_P to BLT3_P are set, for example but not limited to, a low potential (such as -4V) to turn on the PMOS bit line transistors BLT0_P to BLT3_P.

[0137] Through the above voltage control, a block erasure operation can be performed on the target memory cell SMC. Specifically, during the block erasure operation, the bit line transistors BLT0_N to BLT3_N are turned off; the bit line transistors BLT0_P to BLT3_P are turned on. Therefore, the turned-on bit line transistors BLT0_P to BLT3_P transfer the voltage of the overall bit line GBLN (= 10V) to the plurality of target memory cells SMC through the local bit lines LBL1 to LBL3.

[0138] Similarly, during the block erasure, the source line transistors SLT0_N to SLT3_N are turned off; the source line transistors SLT0_P to SLT3_P are turned on. Therefore, the turned-on source line transistors SLT0_P to SLT3_P transfer the voltage of the overall bit line GBLN (= 10V) to the plurality of target memory cells SMC through the local source lines LSL1 to LSL3.

[0139] During the block erasure, the local bit lines (such as LBL1 to LBL3) coupled to the selected memory cells are, for example but not limited to, 10V, and the local source line LSL (such as LSL1 to LSL3) coupled to the selected memory cells is, for example but not limited to, 10V.

[0140] From the above definitions, in the embodiments of the present disclosure, during the block erasure operation, the VGS voltage difference of the selected T cell is -20V (-10V - (10V)); the VGS voltage difference of the unselected A cell is -6V (4V - (10V)); the VGS voltage difference of the unselected B cell is -20V (-10V - (10V)); the VGS voltage difference of the unselected C cell is -20V (-10V - (10V)); and the VGS voltage difference of the unselected D cell is -6V (4V - (10V)).

[0141] That is, in an embodiment of the present disclosure, during the block erasure operation, the local source line decoder 210A conducts the overall bit line voltage to at least one fifth target memory cell of the plurality of memory cells; and the local bit line decoder 210B conducts the overall bit line voltage to the at least one fifth target memory cell.

[0142] Table 7 below shows the VGS voltage differences of the 5 types of cells under various operations in an embodiment of the present disclosure.

[0143] Table 7

[0144] Operation Read First Programming Second Programming Byte Erase Block Erase T Cell 4V to 6V 23V 21V -20V -20V A Cell -1V 9V 7V -6V -6V B Cell 5V to 7V 9V 7V -6V -20V C Cell -1V 9V 7V -6V -20V D Cell 0V -5V -7V 8V -6V

[0145] As can be seen from Table 7 above, in the embodiments of the present disclosure, during the first programming operation, the VGS voltage difference of the selected T cell can be increased (compared with the prior art). Therefore, the programming operation can be accelerated in the embodiments of the present disclosure.

[0146] In addition, during the second programming operation, the maximum stress disturbance of the B cell can be reduced.

[0147] Up to the byte erasure operation, the stress of the B cell can be mitigated, from -8V to -6V, and there will be no problem of the body effect.

[0148] Therefore, in the embodiments of the present disclosure, compared with the prior art, the programming operation and the erasure operation can improve the write / erase speed of the 3D AND memory array.

[0149] In summary, although the present disclosure has been disclosed as above with embodiments, it is not intended to limit the present disclosure. Those skilled in the art in the technical field to which the present disclosure pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the appended claims.

Claims

1. A memory device, comprising: A memory array; A decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors, and a plurality of inverters, wherein the plurality of first transistors and the plurality of second transistors are paired; And A controller coupled to the decoding circuit, Wherein, Each pair of the plurality of paired first transistors and the plurality of second transistors is respectively coupled to one of these inverters, and respectively coupled to one of a plurality of regional bit lines or one of a plurality of regional source lines; The plurality of first transistors are coupled to a global bit line; The plurality of second transistors are coupled to a global source line; The plurality of first transistors and the plurality of second transistors form a regional source line decoder and a regional bit line decoder; And During a first programming operation, the regional source line decoder conducts a global source line voltage to a second target memory cell of a plurality of memory cells; and the regional bit line decoder conducts the global source line voltage to the second target memory cell.

2. The memory device according to claim 1, wherein, The plurality of first transistors and the plurality of second transistors are respectively coupled to the memory array through a plurality of regional bit lines or a plurality of regional source lines; And The plurality of regional source lines and the plurality of regional bit lines are controlled by the plurality of paired first transistors and the plurality of second transistors.

3. The memory device according to claim 2, wherein, During a read operation, the regional source line decoder conducts a global source line voltage to a first target memory cell of the plurality of memory cells; and the regional bit line decoder conducts a global bit line voltage to the first target memory cell.

4. The memory device according to claim 2, wherein, During a second programming operation, the regional source line decoder conducts a global source line voltage to a third target memory cell of the plurality of memory cells; and the regional bit line decoder conducts the global source line voltage to the third target memory cell.

5. The memory device according to claim 2, wherein, During a byte erase operation, the regional source line decoder conducts a global bit line voltage to a fourth target memory cell of the plurality of memory cells; and the regional bit line decoder conducts the global bit line voltage to the fourth target memory cell.

6. The memory device according to claim 2, wherein, During a block erase operation, the regional source line decoder conducts a global bit line voltage to at least one fifth target memory cell of the plurality of memory cells; and the regional bit line decoder conducts the global bit line voltage to the at least one fifth target memory cell.

7. An operation method of a memory device, comprising: Controlling a plurality of regional source lines and a plurality of regional bit lines by a plurality of paired first transistors and a plurality of second transistors, Wherein, the plurality of first transistors and the plurality of second transistors are triode transistors; The plurality of first transistors are coupled to a global bit line; The plurality of second transistors are coupled to a global source line; The plurality of first transistors and the plurality of second transistors form a regional source line decoder and a regional bit line decoder; and During a first programming operation, the regional source line decoder conducts a global source line voltage to a second target memory cell of a plurality of memory cells; and the regional bit line decoder conducts the global source line voltage to the second target memory cell.

8. The method of operating a memory device according to claim 7, wherein, The plurality of first transistors and the plurality of second transistors are respectively coupled to the memory array through a plurality of regional bit lines or a plurality of regional source lines.

9. The method of operating a memory device according to claim 8, wherein, During a read operation, the regional source line decoder conducts a global source line voltage to a first target memory cell of a plurality of memory cells; and the regional bit line decoder conducts a global bit line voltage to the first target memory cell.

10. The method of operating a memory device according to claim 8, wherein, During a second programming operation, the regional source line decoder conducts a global source line voltage to a third target memory cell of a plurality of memory cells; and the regional bit line decoder conducts the global source line voltage to the third target memory cell.

11. The method of operating a memory device according to claim 8, wherein, During a byte erase operation, the regional source line decoder conducts a global bit line voltage to a fourth target memory cell of a plurality of memory cells; and the regional bit line decoder conducts the global bit line voltage to the fourth target memory cell.

12. The method of operating a memory device according to claim 8, wherein, During a block erase operation, the regional source line decoder conducts a global bit line voltage to at least one fifth target memory cell of a plurality of memory cells; and the regional bit line decoder conducts the global bit line voltage to the at least one fifth target memory cell.

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