Method for reducing on-resistance by backside optimization

Abstract

The present invention belongs to the field of semiconductor device processing technology, and specifically relates to a method for reducing on-resistance by optimizing the back of a wafer, comprising the following steps: substrate thinning: using a thinning machine to thin a SiC wafer substrate; evaporation of ohmic contact material: forming an ohmic contact material layer on the back of the substrate by an evaporation process; laser etching: laser etching of the ohmic contact material layer and the SiC wafer substrate; back annealing: annealing the back of the etched substrate; reduction of SiO2: reducing SiO2 on the back of the substrate to Si by using H2 or CO at high temperature; evaporation of a transition layer: forming a Mo layer or a W layer on the back of the substrate by an evaporation process; evaporation of an external layer: forming an external metal layer on the back of the substrate by an evaporation process. The present invention can reduce the on-resistance of a SiC wafer substrate, and under the same on-resistance condition, can reduce the consumables of a diamond grinding wheel in disguised form.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device processing, and in particular relates to a method for reducing on-resistance by optimizing the backside of a wafer. Background Art

[0002] SiC is a wide bandgap semiconductor material that has developed rapidly in the past decade. Compared with other semiconductor materials, such as Si, GaN and GaAs, SiC has the advantages of wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. SiC can be thermally oxidized to generate silicon dioxide, making it possible to realize power devices and circuits such as SiCMOSFET and SBD. Since the 1990s, power devices such as SiCMOSFET and SBD have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers. In SiC power SBD and power MOSFET devices, the resistance of the back of the crystal, that is, the substrate part, is a large part of the on-resistance of the entire device. Especially for devices with a withstand voltage below 900V, the resistance of the substrate part can reach more than 20% of the on-resistance of the entire device. Reducing the resistance of the substrate part is extremely important for reducing the on-resistance of the device, optimizing the chip area, reducing the device cost, and reducing the power loss of the device.

[0003] The existing mainstream technology is to apply a protective film after the front device process is completed, and then use a diamond grinding wheel thinning machine from manufacturers such as DISCO\Okamoto to grind and thin the back of the SiC wafer substrate. The 350um SiC wafer needs to be thinned to 150um or even thinner, which can reduce the resistance of the substrate part by more than 60%, while reducing the thermal resistance of the chip and enhancing the high-temperature reliability of the device. However, due to the extremely high hardness and chemical stability of SiC wafers, the use of diamond grinding wheels to thin the 200um SiC substrate layer is very expensive. At the same time, when thinning to less than 150um, the stress and damage of the SiC wafer are high, the curvature of the wafer is very large, and further thinning is very difficult, which can easily cause cracks, and the reliability and yield of the process are reduced. Summary of the invention

[0004] The present invention aims to provide a method for reducing on-resistance by backside optimization, so as to reduce the on-resistance of a SiC wafer substrate portion.

[0005] In order to achieve the above object, the scheme of the present invention is: a method for reducing on-resistance by backside optimization, comprising the following steps:

[0006] Substrate thinning: Use a thinning machine to thin the SiC wafer substrate;

[0007] Evaporation of ohmic contact material: forming an ohmic contact material layer on the back side of the substrate by evaporation process;

[0008] Laser etching: Laser etching the ohmic contact material layer and SiC wafer substrate;

[0009] Back annealing: annealing the back side of the etched substrate;

[0010] Reducing SiO2: Using H2 or CO at high temperature to reduce SiO2 on the back of the substrate to Si;

[0011] Evaporation transition layer: a Mo layer or a W layer is formed on the back of the substrate by an evaporation process;

[0012] Evaporation external layer: An external metal layer is formed on the back of the substrate through an evaporation process.

[0013] Optionally, in the substrate thinning step, the substrate is ground and thinned from the back side, and the thickness of the substrate after thinning is as thin as 150 um at most.

[0014] Optionally, in the step of evaporating the ohmic contact material, a Ti layer is evaporated first, and then a Ni layer is evaporated.

[0015] Optionally, in the laser etching step, one or a combination of holes or grooves are etched and formed.

[0016] Optionally, in the laser etching step, the etching depth does not exceed 30 um.

[0017] Optionally, the etching density is 1000-4000 / cm 2 .

[0018] Optionally, the annealing process is laser annealing or high temperature annealing, or a combination of the two.

[0019] Optionally, the thickness of the Ag layer is 1 um to 100 um.

[0020] Optionally, the thickness of the transition layer is 5 nm to 10 nm.

[0021] The principles and beneficial effects of the present invention are:

[0022] In the prior art SiC wafer substrate thinning process, grinding with a diamond wheel will cause damage to the crystal surface of the wafer substrate. In order to repair the damage, annealing repair is usually required. However, during the annealing repair process, SiO2 will be formed in the recessed area etched on the back of the substrate. SiO2 prevents the substrate and the metal from forming an ohmic contact, which is not conducive to reducing the on-resistance through the thinning process. To address this defect, the present invention allows SiO2 to react with H2 at high temperature to form a layer of Si on the surface of the etched recessed area. The ohmic contact formed by doped Si and metal is better than that between SiC and metal, which is beneficial to reducing the on-resistance. However, if an external Ag layer is deposited directly in the recessed area at this time, Ag will diffuse into Si and easily form voids, affecting the reliability of the device. Therefore, before depositing the Ag layer, a Mo layer or a W layer is first deposited on the Si surface as a transition to prevent Ag from diffusing into Si. It can also significantly reduce the stress of subsequent wafer slicing. Finally, after the Ag layer is deposited, the SiC substrate is further lowered in disguise, and compared with SiC substrates of the same thickness, it has a lower on-resistance. Even under the same on-resistance conditions, the thickness that the thinning machine needs to wear is smaller, which can reduce the consumables of the diamond grinding wheel in disguise. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a process flow chart of the method for reducing on-resistance by backside optimization in Embodiment 1 of the present invention;

[0024] Figure 2 A schematic diagram of the structure of a product prepared by the method of reducing on-resistance through backside optimization in Embodiment 1 of the present invention;

[0025] Figure 3 The substrate slice V in the first embodiment, the second embodiment and the comparative example of the present invention is F -I F Forward characteristic test curve. DETAILED DESCRIPTION

[0026] The following is further described in detail through specific implementation methods:

[0027] The symbols in the drawings of the specification include: substrate 1, Si layer 2, Ti layer 3, Ni layer 4, Mo layer 5, BP protective film 6, and Ag layer 7.

[0028] Embodiment 1

[0029] This embodiment is basically Figure 1 , Figure 2 As shown: A method for reducing on-resistance by backside optimization includes the following steps:

[0030] S1: Front protection: After the front device process is completed, a BP protection film 6 is applied to the front of the wafer;

[0031] S2: Substrate thinning: A thinning machine is used to grind and thin the back side of the SiC wafer substrate 1 to thin the substrate to 150um;

[0032] S3: evaporation of ohmic contact material: a Ti layer 3 is firstly evaporated on the back side of the substrate 1 by an evaporation process, and then a Ni layer 4 is evaporated. The thickness of the Ti layer 3 and the Ni layer 4 is 10 nm.

[0033] S4: Laser etching: Laser etching the ohmic contact material layer and the SiC wafer substrate 1 to form a groove with a depth of 30 um and a width of 5 um;

[0034] S5: back side annealing: high temperature annealing is performed on the back side of the etched substrate 1;

[0035] S6: Reducing SiO2: placing the substrate 1 into an electric heating furnace under a H2 atmosphere to reduce the SiO2 on the back side of the substrate 1 into a Si layer 2;

[0036] S7: Evaporation transition layer: forming a Mo layer 5 (molybdenum layer) on the back side of the substrate 1 by an evaporation process, so as to fill the Mo layer 5 in the groove, and the thickness of the Mo layer 5 is 5 nm;

[0037] S8: Evaporation of external layer: An external metal layer is formed on the back side of the substrate 1 by an evaporation process. The external metal layer can be an Ag layer, an Al layer, or a Cu layer. In this embodiment, the Ag layer 7 is selected, which is cheap, has low resistance, and has good welding performance. The thickness of the Ag layer 7 relative to the Ni layer 4 is 20um.

[0038] Embodiment 2

[0039] The only difference from the first embodiment is that the reducing gas in step S6 is CO, and the transition layer in step S7 is a W layer (tungsten layer).

[0040] Comparative Example

[0041] S1: Front protection: After the front device process is completed, a BP protection film 6 is applied to the front of the wafer;

[0042] S2: Substrate thinning: A thinning machine is used to grind and thin the back side of the SiC wafer substrate 1 to thin the substrate to 150um;

[0043] S3: evaporation of ohmic contact material: a Ti layer 3 is firstly evaporated on the back side of the substrate 1 by an evaporation process, and then a Ni layer 4 is evaporated. The thickness of the Ti layer 3 and the Ni layer 4 is 10 nm.

[0044] S4: Evaporation of external contact layer: An Ag layer 7 is formed on the back side of the substrate 1 by an evaporation process. The thickness of the Ag layer 7 relative to the Ni layer 4 is 20 um.

[0045] The substrate 1 in the first embodiment, the second embodiment and the comparative example was sliced, and good products of each were taken for V F -I F Forward characteristic test, the test results are as attached Figure 3 .from Figure 3 It can be seen that the substrates 1 in Example 1 and Example 2, after being optimized and reduced in on-resistance by the present invention, have lower on-resistance and better forward characteristics than the substrate 1 in the comparative example which has not been optimized.

[0046] In summary, compared with the traditional simple thinning chip, the etched groove can effectively reduce VF, but if it is reduced to Si with CO or H2, compared with the doped SiC and metal contact, the doped Si and metal can form a lower contact resistance ohmic contact, which can further reduce V to a certain extent. F In addition, the embedding of Mo and W can effectively support SiC and adjust the release of internal stress of SiC, thereby greatly reducing the risk of fragmentation.

[0047] The above are only embodiments of the present invention. The invention is not limited to the fields involved in this implementation case. The common knowledge of the known specific structures, materials and characteristics in the scheme is not described in detail here. The ordinary technicians in the relevant field know all the common technical knowledge in the technical field to which the invention belongs before the application date or priority date, can obtain all the existing technologies in the field, and have the ability to apply the conventional experimental means before that date. The ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the protection scope of the present invention, which will not affect the effect of the implementation of the present invention and the practicality of the patent. The protection scope required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to explain the content of the claims.

Claims

1. A method for reducing on-resistance by backside optimization, comprising the following steps: Substrate thinning: Use a thinning machine to thin the SiC wafer substrate; The substrate is ground and thinned from the back side, and the thickness of the substrate after thinning is as thin as 150μm; Evaporation of ohmic contact material: forming an ohmic contact material layer on the back side of the substrate by evaporation process; First, evaporate a Ti layer, and then evaporate a Ni layer; Laser etching: Laser etching the ohmic contact material layer and SiC wafer substrate; Etching to form one or a combination of holes or grooves; Back annealing: annealing the back of the etched substrate. During the annealing repair process, SiO2 is formed in the recessed area etched on the back of the substrate. Features: Reducing SiO2: Using H2 or CO at high temperature to reduce SiO2 on the back of the substrate to Si; Evaporation transition layer: a Mo layer or a W layer is formed on the back of the substrate by an evaporation process; the thickness of the transition layer is 5nm to 10nm; Evaporation external layer: an external metal layer is formed on the back of the substrate by an evaporation process; the external metal layer is an Ag layer, and the thickness of the Ag layer is 1μm to 100μm.

2. The method for reducing on-resistance by backside optimization according to claim 1, characterized in that: In the laser etching step, the etching depth does not exceed 30 μm.

3. The method for reducing on-resistance by backside optimization according to claim 2, characterized in that: The etching density is 1000-4000 / cm.

4. The method for reducing on-resistance by backside optimization according to claim 1, characterized in that: The annealing process is laser annealing or high temperature annealing, or a combination of the two.

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