Non-volatile memory element and method of manufacturing the same

Abstract

A non-volatile memory element and a method of manufacturing the same are disclosed. The non-volatile memory element includes a substrate, an interconnect structure, a plurality of memory cells, a plurality of conductive vias, and a plurality of dummy vias. The substrate has a memory region and a dummy region, wherein the dummy region surrounds the memory region. The interconnect structure is disposed on the substrate and located in the memory region. The plurality of memory cells is disposed on the interconnect structure and arranged in an array from a top-down view, wherein the plurality of memory cells includes a plurality of first memory cells located in the memory region and a plurality of second memory cells located in the dummy region. The plurality of conductive vias is disposed in the memory region and located between the plurality of first memory cells and the interconnect structure to electrically connect each of the first memory cells and the interconnect structure, respectively. The plurality of dummy vias is disposed in the dummy region and surrounds the memory region.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a non-volatile memory device and a manufacturing method thereof. BACKGROUND

[0002] In a general manufacturing process of a magnetoresistive random access memory (MRAM), during a patterning process of forming memory cells, an optical effect will affect the pattern profile of the memory cells located at the edge of a memory region, so that the size of the memory cells located at the edge of the memory region is smaller than the size of other memory cells.

[0003] In order to avoid the above phenomenon, a dummy region is currently disposed around the memory region, and dummy memory cells are disposed in the dummy region. In this way, the optical effect will only affect the dummy memory cells around the memory region, so that the memory cells in the memory region can have the same size.

[0004] In addition, in order to avoid the dummy memory cells in the dummy region from being electrically connected to other lines to affect the device performance, a conductive via is not disposed under the dummy memory cells. At this time, the pattern profile of the conductive via located at the edge of the memory region for electrically connecting the memory cells to the line pattern will be affected by the optical effect and have a smaller aperture, thereby affecting the device performance. For example, the conductive via with a smaller aperture will have a larger resistance, resulting in a substantial reduction in the tunneling magnetoresistance (TMR) of the MRAM. SUMMARY

[0005] The present application provides a non-volatile memory device, wherein a dummy via is disposed around a memory region.

[0006] The present application provides a manufacturing method of a non-volatile memory device, wherein a dummy via is formed around a memory region.

[0007] The non-volatile memory element of the present invention includes a substrate, an interconnect structure, a plurality of memory cells, a plurality of conductive vias, and a plurality of dummy vias. The substrate has a memory region and a dummy region, wherein the dummy region surrounds the memory region. The interconnect structure is disposed on the substrate and located in the memory region. The plurality of memory cells is disposed on the interconnect structure and arranged in an array from a top view, wherein the plurality of memory cells includes a plurality of first memory cells located in the memory region and a plurality of second memory cells located in the dummy region. The plurality of conductive vias is disposed in the memory region and located between the plurality of first memory cells and the interconnect structure to electrically connect each of the first memory cells and the interconnect structure, respectively. The plurality of dummy vias is disposed in the dummy region and surrounds the memory region.

[0008] In an embodiment of the non-volatile memory element of the present invention, from a top view, the conductive vias in two adjacent rows are aligned with each other, and the conductive vias in two adjacent columns are aligned with each other.

[0009] In an embodiment of the non-volatile memory element of the present invention, from a top view, the plurality of dummy vias are misaligned with the plurality of conductive vias in a row direction, and the plurality of dummy vias are misaligned with the plurality of conductive vias in a column direction.

[0010] In an embodiment of the non-volatile memory element of the present invention, a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are less than a distance between adjacent dummy vias and conductive vias.

[0011] In an embodiment of the non-volatile memory element of the present invention, from a top view, the conductive vias in two adjacent rows are misaligned with each other, and the conductive vias in two adjacent columns are misaligned with each other.

[0012] In an embodiment of the non-volatile memory element of the present invention, a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are greater than a distance between adjacent dummy vias and conductive vias.

[0013] In an embodiment of the non-volatile memory element of the present invention, the interconnect structure includes a dummy portion located in the dummy region, and the plurality of second memory cells are not electrically connected with the dummy portion.

[0014] In an embodiment of the non-volatile memory element of the present invention, the plurality of dummy vias are not connected with the dummy portion.

[0015] In an embodiment of the non-volatile memory element of the present invention, the plurality of dummy vias are connected with the dummy portion.

[0016] In an embodiment of the non-volatile memory element of the present invention, an aperture of the dummy via is smaller than an aperture of the conductive via.

[0017] A method of manufacturing a non-volatile memory element of the present invention includes the following steps. A substrate having a memory region and a dummy region is provided, wherein the dummy region surrounds the memory region. An interconnect structure is formed on the substrate, wherein the interconnect structure is located in the memory region. A plurality of memory cells is formed on the interconnect structure, wherein the plurality of memory cells is arranged in an array from a top-down view, and the plurality of memory cells includes a plurality of first memory cells located in the memory region and a plurality of second memory cells located in the dummy region. A plurality of conductive vias is formed in the memory region, wherein the plurality of conductive vias is located between the plurality of first memory cells and the interconnect structure to electrically connect each of the first memory cells with the interconnect structure, respectively. A plurality of dummy vias is formed in the dummy region, wherein the plurality of dummy vias surrounds the memory region.

[0018] In an embodiment of the method of manufacturing a non-volatile memory element of the present invention, the conductive vias in two adjacent rows are aligned with each other from a top-down view, and the conductive vias in two adjacent columns are aligned with each other.

[0019] In an embodiment of the method of manufacturing a non-volatile memory element of the present invention, the plurality of dummy vias are misaligned with the plurality of conductive vias in a row direction from a top-down view, and the plurality of dummy vias are misaligned with the plurality of conductive vias in a column direction from a top-down view.

[0020] In an embodiment of the method of manufacturing a non-volatile memory element of the present invention, a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are smaller than a distance between adjacent dummy vias and conductive vias.

[0021] In an embodiment of the method of manufacturing a non-volatile memory element of the present invention, the conductive vias in two adjacent rows are misaligned with each other from a top-down view, and the conductive vias in two adjacent columns are misaligned with each other from a top-down view.

[0022] In an embodiment of the method of manufacturing a non-volatile memory element of the present invention, a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are greater than a distance between adjacent dummy vias and conductive vias.

[0023] In one embodiment of the method of fabricating a non-volatile memory element of the present application, the interconnect structure includes a dummy portion in the dummy region, and the plurality of second memory cells are not electrically connected to the dummy portion.

[0024] In one embodiment of the method of fabricating a non-volatile memory element of the present application, the plurality of dummy vias are not connected to the dummy portion.

[0025] In one embodiment of the method of fabricating a non-volatile memory element of the present application, the plurality of dummy vias are connected to the dummy portion.

[0026] In one embodiment of the method of fabricating a non-volatile memory element of the present application, the dummy via has a smaller aperture than the conductive via.

[0027] Based on the above, in the present application, a dummy via is disposed around the memory region. Therefore, when defining the positions of the conductive vias connected to the memory cells and the positions of the dummy vias in a photolithography fabrication process, the profile of a photoresist pattern used to define the positions of the conductive vias surrounded by the dummy vias can be prevented from being reduced due to optical effects, and the performance of the memory element can be ensured.

[0028] In order to make the above features and advantages of the present application more apparent, specific embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figures 1A-1C A top view schematic diagram of the fabrication process of a non-volatile memory element according to an embodiment of the present application;

[0030] Figures 2A-2C A cross-sectional schematic diagram of the fabrication process of the I-I' section in Figures 1A-1C

[0031] Figures 3A-3C A cross-sectional schematic diagram of the fabrication process of the II-II' section in Figures 1A-1C

[0032] Figure 4 A top view schematic diagram of a non-volatile memory element according to another embodiment of the present application;

[0033] Figure 5 A top view schematic diagram of a non-volatile memory element according to another embodiment of the present application. DETAILED DESCRIPTION

[0034] ​​Embodiments are illustrated in the following detailed description and in conjunction with the figures, which are by way of illustration. Since the embodiments provided are not meant to limit the scope of the application, other embodiments can be utilized, and other changes can be made, without departing from the scope of the present application. In addition, the drawings are not drawn to scale for the sake of clarity. For ease of understanding, identical elements are marked with the same reference numerals throughout the various figures.

[0035] The terms "comprise", "include", "have", and the like, as used herein, are meant to be open-ended. That is, when the phrases "comprises", "includes", "has", and the like are used, these phrases are meant to include items of the specified list, but not exclude items not expressed in the specific list.

[0036] When an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. Like numbers refer to like elements throughout.

[0037] Figures 1A-1C A top view schematic diagram of a manufacturing process of a non-volatile memory element according to an embodiment of the present application. Figures 2A-2C A top view schematic diagram of a manufacturing process of a non-volatile memory element according to an embodiment of the present application. Figures 1A-1C A cross-sectional view schematic diagram of a manufacturing process according to the I-I' section line in Figures 3A-3C A cross-sectional view schematic diagram of a manufacturing process according to the II-II' section line in Figures 1A-1C A cross-sectional view schematic diagram of a manufacturing process according to the II-II' section line in

[0038] First, referring to Figure 1A , Figure 2A and Figure 3A simultaneously, a substrate 100 is provided. The substrate 100 has a memory region 100a and a dummy region 100b surrounding the memory region 100a. The memory region 100a is a region for disposing memory cells. The memory cells can be memory cells of magnetoresistive random access memory or memory cells of other types of memory, which are not limited by the present application. The dummy region 100b is a region for disposing dummy elements that are not electrically connected to the memory cells. In the present embodiment, the substrate 100 is a silicon substrate on which various semiconductor elements have been formed. For example, the substrate 100 can include a silicon substrate, transistors formed on a surface of the silicon substrate, and a dielectric layer covering the transistors, but the present application is not limited thereto. Then, an interconnect structure 102 is formed in the dielectric layer. In the present embodiment, for the sake of clarity and ease of explanation, the various semiconductor elements described above are not shown, and only the uppermost wiring layer in the interconnect structure 102 is shown. The wiring layer can be located in the dielectric layer or on a surface of the dielectric layer, as desired. The interconnect structure 102 is electrically connected to the various semiconductor elements on the silicon substrate. Then, a dielectric layer 104 is formed on the substrate 100 to cover the interconnect structure 102. The formation methods of the various semiconductor elements and the interconnect structure 102 described above are well known to those skilled in the art, and are not described here again.

[0039] In the present embodiment, the interconnect structure 102 includes main portions 102a in the memory region 100a as the electrical connection members and dummy portions 102b in the dummy region 100b not as the electrical connection members, but the present application is not limited thereto. In other embodiments, the interconnect structure 102 can include only the main portions 102a in the memory region 100a depending on the actual layout requirement.

[0040] Then, with reference to Figure 1B , Figure 2B and Figure 3B , a plurality of vias are formed in the dielectric layer 104. The method of forming the vias is well known to those skilled in the art and will not be described here. In detail, in the present embodiment, conductive vias 106a are formed in the dielectric layer 104 in the memory region 100a, and dummy vias 106b are formed in the dielectric layer 104 in the dummy region 100b. The dummy vias 106b surround the conductive vias 106a in the memory region 100a. In the present embodiment, the conductive vias 106a are connected to the main portions 102a of the interconnect structure 102, and the dummy vias 106b are connected to the dummy portions 102b of the interconnect structure 102. In this way, the conductive vias 106a can serve as the electrical connection members, and the dummy vias 106b do not serve as the electrical connection members. In other embodiments, the dummy vias 106b can not be connected to the dummy portions 102b of the interconnect structure 102.

[0041] In the present embodiment, the conductive vias 106a are arranged in an array from a top view. In the array, the conductive vias 106a in adjacent two rows are aligned with each other, and the conductive vias 106a in adjacent two columns are aligned with each other. That is, in the present embodiment, the conductive vias 106a in the memory region 100a are arranged in a rectangular array, and the dummy vias 106b surround the conductive vias 106a arranged in the rectangular array. In addition, the dummy vias 106b are misaligned with the conductive vias 106a in the row direction and misaligned with the conductive vias 106a in the column direction from a top view. Further, the distance Dl between the conductive vias 106a in adjacent two rows is smaller than the distance D3 between the adjacent dummy via 106b and the conductive via 106a, and the distance D2 between the conductive vias 106a in adjacent two columns is also smaller than the distance D3.

[0042] Based on the above layout, in the process of forming the conductive via 106a and the dummy via 106b, when the positions of the conductive via 106a and the dummy via 106b are defined by a photolithography process, only the profile of the photoresist pattern used to define the position of the dummy via 106b will be affected by the optical effect to make the dummy via 106b have a smaller aperture, while the profile of the photoresist pattern used to define the position of the conductive via 106a surrounded by the dummy via 106b will not be affected by the optical effect. Therefore, all the conductive vias 106a in the memory region 100a can have the same aperture to ensure that the performance of the memory element is not affected. In addition, since the dummy via 106b does not serve as an electrical connection member, even if the dummy via 106b has a non-uniform aperture and / or a reduced aperture, the performance of the memory element will not be affected. For example, when the memory element to be formed is a magnetoresistive random access memory, since all the conductive vias 106a in the memory region 100a can have the same and non-reduced aperture, the resistance of the conductive via 106a can be prevented from being too large and non-uniform, thereby preventing the tunneling magnetoresistance of the magnetoresistive random access memory from being greatly reduced.

[0043] Thereafter, with reference to Figure 1C , Figure 2C and Figure 3C , a memory cell 108 is formed on the dielectric layer 104 to form the non-volatile memory element 10 of the present embodiment. The memory cell 108 can be a memory cell of a magnetoresistive random access memory or a memory cell of another type of memory, which is not limited in the present application. The method of forming the memory cell 108 is well known to those skilled in the art and will not be described here. Based on the arrangement of the conductive via 106a, the memory cell 108 is arranged in an array from a top view. In detail, the memory cell 108 includes a first memory cell 108a located in the memory region 100a and a second memory cell 108b located in the dummy region 100b. Each first memory cell 108a is formed above and connected to a corresponding conductive via 106a. In other words, the conductive via 106a is located between the corresponding first memory cell 100a and the interconnect structure 102 to electrically connect the corresponding first memory cell 100a and the interconnect structure 102. The second memory cell 108b is formed on the dielectric layer 104 in the dummy region 100b and is not connected to the dummy via 106b. Therefore, the second memory cell 108b can be regarded as a dummy memory cell.

[0044] Since the second memory cell 108b is formed around the first memory cell 108a, during the formation of the first memory cell 108a and the second memory cell 108b, when defining the positions of the first memory cell 108a and the second memory cell 108b using photolithography, only the outline of the photoresist pattern used to define the position of the second memory cell 108b is affected by optical effects, resulting in a smaller size for the second memory cell 108b. The outline of the photoresist pattern used to define the position of the first memory cell 108a surrounded by the second memory cell 108b is not affected by optical effects. Therefore, all first memory cells 108a in the memory region 100a can have the same size to ensure that the performance of the memory element is not affected. Furthermore, since the second memory cell 108b is a dummy memory cell, even if the second memory cell 108b has a non-uniform size and / or a reduced size, the performance of the memory element will not be affected.

[0045] Furthermore, in the dummy region 100b, since the second memory cell 108b is not connected to the dummy via 106b, the second memory cell 108b is not electrically connected to the interconnect structure 102, and therefore does not affect the operation of the first memory cell 108a in the memory region of 100a.

[0046] In this embodiment, viewed from a top-down direction, as... Figure 1C As shown, a ring of second memory cells 108b surrounds the memory region 100a, and a dummy through-hole 106b is located between the second memory cells 108b and the first memory cell 108a, thus surrounding the first memory cell 108a. However, the invention is not limited to this. In other embodiments, viewed from the top, multiple rings of second memory cells 108b can be arranged around the memory region 100a, and the dummy through-hole 106b, in addition to being located between the second memory cells 108b and the first memory cell 108a, can also be located between two adjacent rings of second memory cells 108b, such as... Figure 4 As shown.

[0047] Figure 5 This is a top view schematic diagram illustrating a non-volatile memory element according to another embodiment of the present invention. In this embodiment, with Figure 1C Components identical to those in this embodiment will be represented by the same symbols and will not be described further. Furthermore, the manufacturing process of the non-volatile memory components in this embodiment is similar to... Figures 1A-1C The manufacturing process is the same, so it will not be described again.

[0048] Reference Figure 5In the present embodiment, from a plan view, the conductive vias 106a in the memory region 100a are misaligned with each other in adjacent rows and misaligned with each other in adjacent columns. That is, in the present embodiment, the conductive vias 106a in the memory region 100a are arranged in a manner similar to an octagonal array, and the dummy vias 106b are arranged around the conductive vias 106a arranged in a manner similar to an octagonal array. In addition, the distance D5 between the conductive vias 106a in adjacent rows and in adjacent columns is greater than the distance D6 between adjacent dummy vias 106b and the conductive vias 106a.

[0049] Based on the above-described layout, in forming the conductive vias 106a and the dummy vias 106b, only the profile of the photoresist pattern used to define the positions of the dummy vias 106b is affected by the optical effect to cause the dummy vias 106b to have a smaller aperture, while the profile of the photoresist pattern used to define the positions of the conductive vias 106a surrounded by the dummy vias 106b is not affected by the optical effect. Thus, all of the conductive vias 106a in the memory region 100a can have the same aperture, so as to ensure that the performance of the memory elements is not affected. In addition, since the dummy vias 106b do not serve as electrical connection members, even if the dummy vias 106b have a non-uniform aperture and / or a reduced aperture, the performance of the memory elements is not affected. For example, when the formed memory elements are magnetoresistive random access memories, since all of the conductive vias 106a in the memory region 100a can have the same and reduced aperture, the resistance of the conductive vias 106a is not excessively large and non-uniform, and thus the tunneling magnetoresistance of the magnetoresistive random access memories is not substantially reduced.

[0050] In addition, since the second memory cell 108b is formed around the first memory cell 108a, in the process of forming the first memory cell 108a and the second memory cell 108b, only the profile of the photoresist pattern used to define the position of the second memory cell 108b is affected by the optical effect to make the second memory cell 108b have a smaller size, while the profile of the photoresist pattern used to define the position of the first memory cell 108a surrounded by the second memory cell 108b is not affected by the optical effect. Therefore, all the first memory cells 108a in the memory region 100a can have the same size, so as to ensure that the performance of the memory element is not affected. In addition, since the second memory cell 108b is a dummy memory cell, even if the second memory cell 108b has a non-uniform size and / or a reduced size, the performance of the memory element will not be affected.

[0051] In addition, as mentioned above, in other embodiments, from the top view, multiple circles of the second memory cells 108b can be arranged around the memory region 100a, and the dummy via 106b can be located between two adjacent circles of the second memory cells 108b in addition to being located between the second memory cell 108b and the first memory cell 108a.

[0052] Although the present application is disclosed in connection with the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: a substrate having a memory region and a dummy region, wherein the dummy region surrounds the memory region; an interconnect structure disposed on the substrate and located in the memory region; a plurality of memory cells disposed on the interconnect structure and arranged in an array from a top-down view, wherein the plurality of memory cells include a plurality of first memory cells located in the memory region and a plurality of second memory cells located in the dummy region; a plurality of conductive vias disposed in the memory region and located between the plurality of first memory cells and the interconnect structure to respectively electrically connect each of the first memory cells and the interconnect structure; and a plurality of dummy vias disposed in the dummy region and surrounding the memory region, wherein a hole diameter of the dummy vias is smaller than a hole diameter of the conductive vias.

2. The non-volatile memory device of claim 1, wherein the conductive vias in two adjacent rows are aligned with each other and the conductive vias in two adjacent columns are aligned with each other from a top-down view.

3. The non-volatile memory device of claim 2, wherein the plurality of dummy vias are misaligned with the plurality of conductive vias in a row direction and misaligned with the plurality of conductive vias in a column direction from a top-down view.

4. The non-volatile memory device of claim 3, wherein a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are smaller than a distance between adjacent dummy vias and conductive vias.

5. The non-volatile memory device of claim 1, wherein the conductive vias in two adjacent rows are misaligned with each other and the conductive vias in two adjacent columns are misaligned with each other from a top-down view.

6. The non-volatile memory device of claim 5, wherein a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are greater than a distance between adjacent dummy vias and conductive vias.

7. The non-volatile memory device of claim 1, wherein the interconnect structure includes a dummy portion located in the dummy region, and the plurality of second memory cells are not electrically connected with the dummy portion.

8. The non-volatile memory device of claim 7, wherein the plurality of dummy vias are not connected with the dummy portion.

9. The non-volatile memory device of claim 7, wherein the plurality of dummy vias are connected with the dummy portion.

10. A method of manufacturing a non-volatile memory device, comprising: providing a substrate having a memory region and a dummy region, wherein the dummy region surrounds the memory region; forming an interconnect structure on the substrate, wherein the interconnect structure is located in the memory region; and forming a plurality of memory cells on the interconnect structure and arranged in an array from a top-down view, wherein the plurality of memory cells include a plurality of first memory cells located in the memory region and a plurality of second memory cells located in the dummy region. forming a plurality of memory cells over the interconnect structure, wherein the plurality of memory cells are arranged in an array from a top-down view, and the plurality of memory cells include a plurality of first memory cells in the memory region and a plurality of second memory cells in the dummy region; forming a plurality of conductive vias in the memory region, wherein the plurality of conductive vias are between the plurality of first memory cells and the interconnect structure to respectively electrically connect each of the first memory cells and the interconnect structure; and forming a plurality of dummy vias in the dummy region, wherein the plurality of dummy vias surround the memory region, wherein an aperture of the dummy vias is smaller than an aperture of the conductive vias.

11. The method of claim 10, wherein the conductive vias in two adjacent rows are aligned with each other and the conductive vias in two adjacent columns are aligned with each other from a top-down view.

12. The method of claim 11, wherein the plurality of dummy vias are misaligned with the plurality of conductive vias in a row direction and misaligned with the plurality of conductive vias in a column direction from a top-down view.

13. The method of claim 12, wherein a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are smaller than a distance between adjacent dummy vias and conductive vias.

14. The method of claim 10, wherein the conductive vias in two adjacent rows are misaligned with each other and the conductive vias in two adjacent columns are misaligned with each other from a top-down view.

15. The method of claim 14, wherein a distance between the conductive vias in two adjacent rows and a distance between the conductive vias in two adjacent columns are larger than a distance between adjacent dummy vias and conductive vias.

16. The method of claim 10, wherein the interconnect structure includes a dummy portion in the dummy region, and the plurality of second memory cells are not electrically connected with the dummy portion.

17. The method of claim 16, wherein the plurality of dummy vias are not connected with the dummy portion.

18. The method of claim 16, wherein the plurality of dummy vias are connected with the dummy portion.

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