MOS device, manufacturing method and application thereof

Abstract

The application provides a MOS device, a manufacturing method and an application thereof. The MOS device comprises a P-base region, a P++ region and a substrate. The substrate has opposite first and second sides. The P-base region is doped with low ion concentration, and the P++ region is doped with high ion concentration. The P++ region comprises a first P++ region and a second P++ region, and the P-base region comprises a first P-base region and a second P-base region. The first P-base region is arranged on the first side in the substrate, the second P-base region is arranged on the second side in the substrate, the first P++ region is arranged in the substrate and connects to the lower edge of the first P-base region, and the second P++ region is arranged in the substrate and connects to the lower edge of the second P-base region. The first P-base region and the first P++ region are aligned with each other on the side close to the gap, and the second P-base region and the second P++ region are aligned with each other on the side close to the gap. The application can avoid the latch-up effect of the MOS device, thereby improving the avalanche tolerance, reliability and use effect of the MOS device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic devices, in particular to a MOS device and a manufacturing method and application thereof.

BACKGROUND

[0002] In the related art, the structure of a MOS (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) device has defects, which causes the MOS device to be prone to latch-up effect, and further causes the MOS device to burn out and fail, so that the avalanche tolerance of the MOS device is low, and the reliability and use effect are poor, which limits the application of the MOS device in the field of motor drive and the like. In addition, the manufacturing process of the MOS device adopts photoetching alignment technology, and the channel length is greatly affected by the photoetching process error, so that the on-resistance and threshold voltage of the MOS device change greatly, the controllability of the manufacturing process is poor, and the quality of the MOS device is affected to a certain extent.

[0003] Therefore, it is necessary to improve the structure of the MOS device.

SUMMARY

[0004] The present application provides a MOS device and a manufacturing method and application thereof, and aims to solve the problem that the MOS device is prone to latch-up effect in the related art.

[0005] In order to solve the above technical problems, the first aspect of the embodiments of the present application provides a MOS device, which comprises a substrate, a P+ region, an N+ region, a P-base region with low ion concentration doping and a P++ region with high ion concentration doping; wherein the P++ region comprises a first P++ region and a second P++ region, the P-base region comprises a first P-base region and a second P-base region, the N+ region comprises a first N+ region and a second N+ region, the P+ region comprises a first P+ region and a second P+ region, the surface of the substrate has a first side and a second side opposite to the first side, and a preset direction from the first side to the second side.

[0006] The first P+ region and the first N+ region, which are interconnected, are disposed on the surface of the substrate at a position on the first side along the preset direction. The second N+ region and the second P+ region, which are interconnected, are disposed on the surface of the substrate at a position on the second side along the preset direction. The first P-base region is disposed within the substrate and covers the first P+ region and the first N+ region. The side of the first N+ region away from the first P+ region is spaced apart from the periphery of the first P-base region. The second P-base region is disposed within the substrate and covers the second P+ region and the second N+ region. The side of the second N+ region away from the second P+ region is spaced apart from the periphery of the first P-base region. The peripheries of the second P-base regions are spaced apart from each other. The first P++ region is disposed within the substrate and connected to the side of the first P-base region away from the first N+ region. The second P++ region is disposed within the substrate and connected to the side of the second P-base region away from the second N+ region. A gap is formed between the interconnected first P-base regions, the first P++ region and the interconnected second P-base regions, the second P++ region and the second P++ region. The sides of the first P-base regions and the first P++ regions near the gap are aligned with each other, and the sides of the second P-base regions and the second P++ regions near the gap are aligned with each other.

[0007] The second aspect of this application provides a method for fabricating a MOS device, comprising:

[0008] Obtain the substrate;

[0009] P-base and P++ regions are implanted within the substrate;

[0010] P+ and N+ regions are formed by implantation on the surface of the substrate;

[0011] The surface of the substrate has opposite first and second sides and a preset direction from the first side to the second side; the P-base region is low ion concentration doping, the P++ region is high ion concentration doping, the P++ region includes a first P++ region and a second P++ region, the P-base region includes a first P-base region and a second P-base region, the N+ region includes a first N+ region and a second N+ region, and the P+ region includes a first P+ region and a second P+ region; the first P+ region and the first N+ region in mutual connection are arranged on the surface of the substrate at the first side along the preset direction, the second N+ region and the second P+ region in mutual connection are arranged on the surface of the substrate at the second side along the preset direction, the first P-base region is arranged in the substrate and covers the first P+ region and the first N+ region, one side of the first N+ region away from the first P+ region is spaced from the periphery of the first P-base region, the second P-base region is arranged in the substrate and covers the second P+ region and the second N+ region, one side of the second N+ region away from the second P+ region is spaced from the periphery of the second P-base region, the first P++ region is arranged in the substrate and connected to one side of the first P-base region away from the first N+ region, the second P++ region is arranged in the substrate and connected to one side of the second P-base region away from the second N+ region, a gap is formed between the first P-base region, the first P++ region in mutual connection and the second P-base region, the second P++ region in mutual connection, one side of the first P-base region and the first P++ region close to the gap is aligned with each other, and one side of the second P-base region and the second P++ region close to the gap is aligned with each other.

[0012] The third aspect of the embodiments of the present application provides an application of the MOS device in the first aspect of the embodiments of the present application or the MOS device manufactured by the manufacturing method of the MOS device in the second aspect of the embodiments of the present application in a power electronic device.

[0013] From the above description, compared with the related art, the beneficial effects of the present application are that:

[0014] The MOS device is composed of a substrate (with opposite first and second sides), a low-ion-concentration doped P-base region and a high-ion-concentration doped P++ region; wherein the P++ region comprises a first P++ region and a second P++ region, the P-base region comprises a first P-base region and a second P-base region, the first P-base region is arranged at the first side in the substrate, the second P-base region is arranged at the second side in the substrate, the first P++ region is arranged in the substrate and connected to the lower edge of the first P-base region, the second P++ region is arranged in the substrate and connected to the lower edge of the second P-base region, the first P-base region and the first P++ region connected to each other, and the second P-base region and the second P++ region connected to each other form a gap, the side of the first P-base region and the first P++ region close to the gap is aligned with each other, and the side of the second P-base region and the second P++ region close to the gap is aligned with each other. As can be seen, the high-ion-concentration doped P++ region is introduced below the low-ion-concentration doped P-base region, which not only does not require additional photolithography process, but also effectively avoids the latch-up effect of the MOS device, thereby improving the avalanche tolerance of the MOS device, so that the MOS device can have better reliability and use effect, and further expand the application of the MOS device in the field of motor driving. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the related art or the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and not all embodiments. Those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.

[0016] Figure 1 The first structure schematic diagram of the MOS device provided by the embodiments of the present application;

[0017] Figure 2 The second structure schematic diagram of the MOS device provided by the embodiments of the present application;

[0018] Figure 3 The flowchart of the manufacturing method of the MOS device provided by the embodiments of the present application;

[0019] Figure 4 The first structure schematic diagram of the MOS device in the manufacturing process provided by the embodiments of the present application; Figure 3 The flowchart of step 302 in the middle;

[0020] Figure 5 The first structure schematic diagram of the MOS device in the manufacturing process provided by the embodiments of the present application;

[0021] Figure 6 A second structural schematic diagram of the MOS device in a manufacturing process is provided for the embodiment of the present application;

[0022] Figure 7 A third structural schematic diagram of the MOS device in a manufacturing process is provided for the embodiment of the present application; Figure 3 A flowchart of step 303 in the method is provided for the embodiment of the present application;

[0023] Figure 8 A fourth structural schematic diagram of the MOS device in a manufacturing process is provided for the embodiment of the present application.

[0024] Figure 9 A fourth structural schematic diagram of the MOS device in a manufacturing process is provided for the embodiment of the present application.

DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present application more obvious and easy to understand, the present application will be described clearly and completely below in combination with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only used to explain the present application and do not limit the present application, that is, all other embodiments obtained by those skilled in the art without creative labor based on the various embodiments of the present application belong to the scope of protection of the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0026] SiC (Silicon Carbide, carbonized silicon) is a typical representative of the third generation of semiconductor materials. Because its band gap, critical breakdown field, thermal conductivity and carrier saturation drift speed and other characteristic indicators are more than three times that of Si (Silicon, silicon), it has become an excellent material for making power electronic devices, such as making LDMOS (Laterally Double-Diffused Metal-Oxide-Semiconductor, lateral double-diffused metal-oxide-semiconductor) devices and MOS (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field-effect transistor) devices. The power electronic devices using SiC are suitable for high temperature, high voltage, high power and radiation resistant application scenarios, and they have a significant effect on reducing power consumption. MOS devices are basic energy conversion devices in power electronic equipment, which determine the size, efficiency and weight of power electronic equipment. MOS devices using SiC have excellent frequency characteristics, low on-resistance, high switching speed and low switching loss, which makes them widely used in industrial control, motor drive, automotive electronics, inverters and various fields. In recent years, as the requirement for the power density of SiC MOS devices (i.e. MOS devices using SiC) is getting higher and higher, the limitation on the power consumption of SiC MOS devices is increasing.

[0027] In related technologies, the structure of the SiC MOS device itself has certain defects, which can cause the SiC MOS device to easily occur latch-up effect, and further cause the SiC MOS device to burn out and fail, so that the avalanche tolerance of the SiC MOS device is low, and the reliability and use effect are poor, which limits the application of the SiC MOS device in the field of motor drive and the like. In addition, the manufacturing process of the SiC MOS device uses photolithography alignment technology, and the channel length of the SiC MOS device is greatly affected by the photolithography process error, so that the on-resistance and threshold voltage of the SiC MOS device change greatly, and the controllability of the manufacturing process is poor, and further the quality of the SiC MOS device is affected to a certain extent. Therefore, the MOS device provided in the embodiments of the present application can be applied to various power electronic equipment, such as motors, inverters and switching power supplies.

[0028] Please refer to Figure 1 , Figure 1A first structure diagram of a MOS device is provided in the embodiments of the present application. The MOS device provided in the embodiments of the present application comprises a substrate 10, a P+ region 40, an N+ region 50, a P-base region 30 with low ion concentration and a P++ region 20 with high ion concentration; wherein the P++ region 20 comprises a first P++ region 21 and a second P++ region 22, the P-base region 30 comprises a first P-base region 31 and a second P-base region 32, the N+ region 50 comprises a first N+ region 51 and a second N+ region 52, the P+ region 40 comprises a first P+ region 41 and a second P+ region 42, the surface of the substrate 10 has a first side U and a second side V opposite to the first side U, and a preset direction F from the first side U to the second side V.

[0029] Specifically, the first P+ region 41 and the first N+ region 51 which are connected to each other are arranged on the surface of the substrate 10 at a position of the first side U along the preset direction F, the second N+ region 52 and the second P+ region 42 which are connected to each other are arranged on the surface of the substrate 10 at a position of the second side V along the preset direction F, the first P-base region 31 is arranged in the substrate 10 and covers the first P+ region 41 and the first N+ region 51, the side of the first N+ region 51 away from the first P+ region 41 is spaced apart from the periphery of the first P-base region 31, the second P-base region 32 is arranged in the substrate 10 and covers the second P+ region 42 and the second N+ region 52, the side of the second N+ region 52 away from the second P+ region 42 is spaced apart from the periphery of the second P-base region 32, the first P++ region 21 is arranged in the substrate 10 and connected to the side of the first P-base region 31 away from the first N+ region 51, the second P++ region 22 is arranged in the substrate 10 and connected to the side of the second P-base region 32 away from the second N+ region 52, the first P-base region 31 and the first P++ region 21 which are connected to each other and the second P-base region 32 and the second P++ region 22 which are connected to each other form a gap JX, the sides of the first P-base region 31 and the first P++ region 21 close to the gap JX are aligned with each other, and the sides of the second P-base region 32 and the second P++ region 22 close to the gap JX are aligned with each other.

[0030] The embodiment of the present application forms a MOS device with a substrate 10 (having opposite first and second sides U and V), a low-ion-concentration-doped P-base region 30, and a high-ion-concentration-doped P++ region 20; wherein the P++ region 20 includes a first P++ region 21 and a second P++ region 22, the P-base region 30 includes a first P-base region 31 and a second P-base region 32, the first P-base region 31 is arranged at the first side U of the substrate 10, the second P-base region 32 is arranged at the second side V of the substrate 10, the first P++ region 21 is arranged in the substrate 10 and connected to the lower edge of the first P-base region 31, the second P++ region 22 is arranged in the substrate 10 and connected to the lower edge of the second P-base region 32, the first P-base region 31 and the first P++ region 21 connected to each other, and the second P-base region 32 and the second P++ region 22 connected to each other form a gap JX between them, the side of the first P-base region 31 and the first P++ region 21 close to the gap JX is aligned with each other, and the side of the second P-base region 32 and the second P++ region 22 close to the gap JX is aligned with each other. As can be seen, the embodiment of the present application introduces a high-ion-concentration-doped P++ region 20 below the low-ion-concentration-doped P-base region 30, which not only does not require additional photolithography process, but also effectively avoids the latch-up effect of the MOS device, thereby improving the avalanche tolerance of the MOS device, enabling the MOS device to have better reliability and use effect, and further expanding the application of the MOS device in the field of motor driving. In addition, the formation of the P++ region 20 in the embodiment of the present application can also control the expansion direction of the PN junction depletion layer in the MOS device, thereby effectively improving the punch-through voltage of the MOS device.

[0031] As an implementation form, please further refer to Figure 2 , Figure 2 The second structure diagram of the MOS device provided by the embodiment of the present application is shown. The substrate 10 can adopt a double-base region structure, that is, the substrate 10 can include an N+ base 11, an N-type buffer layer 12, and an N- epitaxial layer 13; wherein the N-type buffer layer 12 is covered on the surface of the N+ base 11, and the N- epitaxial layer 13 is covered on the surface of the N-type buffer layer 12. In this article, the material of the substrate 10 can be SiC, that is, the materials of the N+ base 11, the N-type buffer layer 12, and the N- epitaxial layer 13 are all SiC.

[0032] It should be noted that the present embodiment is only a preferred implementation of the embodiment of the present application, and is not the only limitation on the specific composition of the substrate 10; for this, those skilled in the art can flexibly set according to the actual application scene on the basis of the embodiment of the present application.

[0033] In some embodiments, still referring to Figure 2The MOS device provided by the embodiment of the present application can further include a back metal electrode 60 arranged on the side of the N+ substrate 11 away from the N-type buffer layer 12.

[0034] In some embodiments, still referring to Figure 2 The MOS device provided by the embodiment of the present application can further include a gate oxide layer 70 covering the surface of the substrate 10, i.e. the surface of the N- epitaxial layer 13. Specifically, the gate oxide layer 70 in the embodiment includes a first gate oxide layer 71, a second gate oxide layer 72 and a third gate oxide layer 73; wherein the first gate oxide layer 71 corresponds to the gap JX, the second gate oxide layer 72 is located on the first side U of the surface of the substrate 10, and the third gate oxide layer 73 is located on the second side V of the surface of the substrate 10.

[0035] Further, the MOS device provided by the embodiment of the present application can further include a polysilicon gate 80 arranged on the surface of the first gate oxide layer 71.

[0036] In some embodiments, still referring to Figure 2 The MOS device provided by the embodiment of the present application can further include an ILD insulating layer 90 covering the surface of the gate oxide layer 70. Specifically, the ILD insulating layer 90 in the embodiment includes a first ILD insulating layer 91, a second ILD insulating layer 92 and a third ILD insulating layer 93; wherein the first ILD insulating layer 91 covers the first gate oxide layer 71 and the polysilicon gate 80, the second ILD insulating layer 92 covers the surface of the second gate oxide layer 72, and the third ILD insulating layer 93 covers the surface of the third gate oxide layer 73.

[0037] In some embodiments, still referring to Figure 2 The MOS device provided by the embodiment of the present application can further include a front metal electrode JS arranged on the ILD insulating layer 90, between the first ILD insulating layer 91 and the second ILD insulating layer 92, and between the first ILD insulating layer 91 and the third ILD insulating layer 93. Specifically, the front metal electrode JS located between the first ILD insulating layer 91 and the second ILD insulating layer 92 forms an ohmic contact with the first P+ region 41 and the first N+ region 51, and the front metal electrode JS located between the first ILD insulating layer 91 and the third ILD insulating layer 93 forms an ohmic contact with the second P+ region 42 and the second N+ region 52.

[0038] Please refer to Figure 3 , Figure 3A flowchart of a method for manufacturing a MOS device is provided in the embodiments of the present application. The embodiments of the present application also provide a method for manufacturing a MOS device, which is used to manufacture the MOS device provided in the embodiments of the present application, and the method for manufacturing the MOS device comprises the following steps 301-303.

[0039] In step 301, a substrate is obtained.

[0040] In the embodiments of the present application, when manufacturing the MOS device, some preliminary preparation work is needed, that is, obtaining the substrate 10, the surface of the substrate 10 has a first side U and a second side V opposite to the first side U, and a preset direction F from the first side U to the second side V. As described above, the substrate 10 can be composed of an N+ substrate 11, an N-type buffer layer 12 and an N- epitaxial layer 13; wherein the N-type buffer layer 12 is coated on the surface of the N+ substrate 11, and the N- epitaxial layer 13 is coated on the surface of the N-type buffer layer 12.

[0041] In step 302, a P-base region and a P++ region are formed by implanting in the substrate.

[0042] In the embodiments of the present application, after obtaining the substrate 10, the P-base region 30 and the P++ region 20 are formed by implanting in the substrate 10; wherein the P-base region 30 is a low ion concentration doping, the P++ region 20 is a high ion concentration doping, and the P++ region 20 includes a first P++ region 21 and a second P++ region 22, and the P-base region 30 includes a first P-base region 31 and a second P-base region 32.

[0043] In step 303, a P+ region and an N+ region are formed by implanting on the surface of the substrate.

[0044] In the embodiments of the present application, after forming the P-base region 30 and the P++ region 20 by implanting in the substrate 10, the P+ region 40 and the N+ region 50 are formed by implanting on the surface of the substrate 10; wherein the N+ region 50 includes a first N+ region 51 and a second N+ region 52, and the P+ region 40 includes a first P+ region 41 and a second P+ region 42.

[0045] The MOS device made by the above steps 301 to 303 should have the following structure: the first P+ region 41 and the first N+ region 51 abutting each other are arranged on the surface of the substrate 10 at the first side U along the preset direction F, the second N+ region 52 and the second P+ region 42 abutting each other are arranged on the surface of the substrate 10 at the second side V along the preset direction F, the first P-base region 31 is arranged in the substrate 10 and covers the first P+ region 41 and the first N+ region 51, the side of the first N+ region 51 away from the first P+ region 41 is spaced apart from the periphery of the first P-base region 31, the second P-base region 32 is arranged in the substrate 10 and covers the second P+ region 42 and the second N+ region 52, the side of the second N+ region 52 away from the second P+ region 42 is spaced apart from the periphery of the second P-base region 32, the first P++ region 21 is arranged in the substrate 10 and abuts the side of the first P-base region 31 away from the first N+ region 51, the second P++ region 22 is arranged in the substrate 10 and abuts the side of the second P-base region 32 away from the second N+ region 52, the first P-base region 31, the first P++ region 21, the second P-base region 32 and the second P++ region 22 form a gap JX therebetween, the side of the first P-base region 31 and the first P++ region 21 close to the gap JX is aligned with each other, and the side of the second P-base region 32 and the second P++ region 22 close to the gap JX is aligned with each other.

[0046] As an implementation, please further refer to Figure 4 , Figure 4 The flowchart of step 302 in the method for manufacturing the MOS device provided in the embodiment of the present application is shown in FIG. 3B. Step 302 can specifically include the following steps 3021 to 3023. Figure 3

[0047] Step 3021: growing a polysilicon film on the surface of the substrate.

[0048] In the embodiment, please refer to Figure 5 , Figure 5 The first structure diagram of the MOS device provided in the embodiment of the present application in the manufacturing process is shown in FIG. 2B. When the P-base region 30 and the P++ region 20 are formed by implanting ions in the substrate 10, a polysilicon film needs to be grown on the surface of the substrate 10, i.e., a polysilicon film is grown on the surface of the N-epitaxial layer 13.

[0049] Step 3022: taking the polysilicon film as a mask, and forming the ion implantation region of the P-base region and the P++ region by photolithography and etching on the polysilicon film.

[0050] In the embodiment, please refer to Figure 6 , Figure 6 ​A second structure schematic diagram of the MOS device in the manufacturing process is provided in the embodiment of the present application. After the polycrystalline silicon film is grown on the surface of the substrate 10, the ion implantation area of the P-base region 30 and the P++ region 20 is formed by photoetching and etching the polycrystalline silicon film with the grown polycrystalline silicon film as a mask.

[0051] Specifically, the polycrystalline silicon film after photoetching and etching is converted into a polycrystalline silicon film segment (the part of the polycrystalline silicon film other than the polycrystalline silicon film segment is removed due to photoetching and etching), which is located at the position corresponding to the gap JX on the surface of the substrate 10, and the position of the surface of the substrate 10 without the polycrystalline silicon film segment serves as the ion implantation area.

[0052] Step 3023, implanting P-type ions of different energies and doses through the ion implantation area to form the P-base region and the P++ region in the substrate.

[0053] In the embodiment, still referring to Figure 6 , after the ion implantation area of the P-base region 30 and the P++ region 20 is formed, implantation of P-type ions (such as aluminum ions) of different energies and doses through the ion implantation area is needed to form the P-base region 30 and the P++ region 20 in the substrate 10, i.e., to form the first P++ region 21, the second P++ region 22, the first P-base region 31, and the second P-base region 32.

[0054] It should be noted that the embodiment is only a preferred implementation of the embodiment of the present application, and is not the only limitation on the specific process of step 302; based on the embodiment of the present application, those skilled in the art can flexibly set it according to the actual application scenario.

[0055] As an embodiment, please further refer to Figure 7 , Figure 7 A flowchart of step 303 in the embodiment of the present application is provided. Figure 3 Step 303 can specifically include the following steps 3031 to 3037.

[0056] Step 3031, depositing a first silicon dioxide on the surface of the substrate and the polycrystalline silicon film segment.

[0057] In the embodiment, when the P+ region 40 and the N+ region 50 are formed by implantation on the surface of the substrate 10, a first silicon dioxide needs to be deposited on the surface of the substrate 10 and the polycrystalline silicon film segment, i.e., a first silicon dioxide is deposited on the surface of the N-epitaxial layer 13 and the polycrystalline silicon film segment.

[0058] Step 3032, forming a side wall and an N+ implantation area by etching the first silicon dioxide.

[0059] In the embodiment, referring to Figure 8 , Figure 8 The third structure schematic diagram of the MOS device provided by the embodiment of the application in the manufacturing process. After the first silicon dioxide is deposited on the surface of the substrate 10 and the polysilicon film segment, the side wall and the N+ to-be-implanted region are formed by etching the first silicon dioxide.

[0060] Specifically, the side wall includes a first side wall and a second side wall; the first side wall is connected to the edge of the polysilicon film segment close to the first side U of the substrate 10, and the second side wall is connected to the edge of the polysilicon film segment close to the second side V of the substrate 10; the width of the first side wall along the preset direction F is equal to the distance between the side of the first N+ region 51 away from the first P+ region 41 and the circumferential edge of the first P-base region 31; the width of the second side wall along the preset direction F is equal to the distance between the side of the second N+ region 52 away from the second P+ region 42 and the circumferential edge of the second P-base region 32; the first side wall and the second side wall are the remaining portions of the first silicon dioxide after etching (the portions of the first silicon dioxide other than the side wall are removed due to etching); the surface of the substrate 10 without the side wall and the polysilicon film segment is the N+ to-be-implanted region.

[0061] Step 3033, implanting N-type ions through the N+ to-be-implanted region to form an initial N+ region on the surface of the substrate.

[0062] In the embodiment, still referring to Figure 8 , after the side wall and the N+ to-be-implanted region are formed, N-type ions are implanted through the N+ to-be-implanted region to form an initial N+ region on the surface of the substrate 10, i.e., to form an initial N+ region on the surface of the N- epitaxial layer 13.

[0063] Specifically, the initial N+ region includes a first initial N+ region and a second initial N+ region; the first initial N+ region is located on the first side U of the surface of the substrate 10, and the second initial N+ region is located on the second side V of the surface of the substrate 10; the width of the first initial N+ region along the preset direction F is equal to the sum of the width of the first N+ region 51 along the preset direction F and the width of the first P+ region 41 along the preset direction F; the width of the second initial N+ region along the preset direction F is equal to the sum of the width of the second N+ region 52 along the preset direction F and the width of the second P+ region 42 along the preset direction F.

[0064] Step 3034, removing the side wall and the polysilicon film segment by etching and depositing second silicon dioxide on the surface of the substrate.

[0065] In the embodiment, after the initial N+ region is formed on the surface of the substrate 10, the side wall and the polysilicon film segment are removed by etching, and the second silicon dioxide is deposited on the surface of the substrate 10, i.e., the second silicon dioxide is deposited on the surface of the N- epitaxial layer 13.

[0066] Step 3035, forming P+ to-be-injected regions by photoetching and etching the second silicon dioxide.

[0067] In the embodiment, referring to Figure 9 , Figure 9 The fourth structure schematic diagram of the MOS device provided by the embodiment in the application in the manufacturing process. After depositing the second silicon dioxide on the surface of the substrate 10, the P+ to-be-injected regions are formed by photoetching and etching the second silicon dioxide.

[0068] Specifically, the second silicon dioxide after photoetching and etching is converted into a second silicon dioxide segment (the part of the second silicon dioxide other than the second silicon dioxide segment is removed due to etching), the edge of the second silicon dioxide segment close to the first side U of the substrate 10 is aligned with the edge of the first P+ region 41 close to the first N+ region 51, the edge of the second silicon dioxide segment close to the second side V of the substrate 10 is aligned with the edge of the second P+ region 42 close to the second N+ region 52, and the position of the surface of the substrate 10 without the second silicon dioxide segment serves as the above-mentioned P+ to-be-injected region.

[0069] Step 3036, etching and removing the part of the first initial N+ region corresponding to the first P+ region and the part of the second initial N+ region corresponding to the second P+ region through the P+ to-be-injected region.

[0070] In the embodiment, still referring to Figure 9 , after forming the P+ to-be-injected region, the part of the first initial N+ region corresponding to the first P+ region 41 and the part of the second initial N+ region corresponding to the second P+ region 42 are etched and removed through the P+ to-be-injected region. It can be understood that the remaining part of the first initial N+ region after etching can serve as the first N+ region 51, and the remaining part of the second initial N+ region after etching can serve as the second N+ region 52.

[0071] Step 3037, injecting P-type ions through the P+ to-be-injected region to form the first P+ region connected with the first N+ region and the second P+ region connected with the second N+ region.

[0072] In the embodiment, still referring to Figure 9 , after the part of the first initial N+ region corresponding to the first P+ region 41 and the part of the second initial N+ region corresponding to the second P+ region 42 are etched and removed, P-type ions are injected through the P+ to-be-injected region to form the first P+ region 41 connected with the first N+ region 51 and the second P+ region 42 connected with the second N+ region 52 on the surface of the substrate 10, that is, the first P+ region 41 connected with the first N+ region 51 and the second P+ region 42 connected with the second N+ region 52 on the surface of the N- epitaxial layer 13.

[0073] It should be noted that this embodiment is only a preferred implementation of the present application, and it is not the only limitation on the specific process of step 303; those skilled in the art can make flexible settings based on the present application and the actual application scenario.

[0074] The preceding text describes an implementation method for implanting P+ region 40, N+ region 50, P-base region 30, and P++ region 20 within substrate 10. However, the MOS device provided in this application embodiment includes not only P+ region 40, N+ region 50, P-base region 30, and P++ region 20, but also a back metal electrode 60, a gate oxide layer 70, a polysilicon gate 80, an ILD insulating layer 90, and a front metal electrode JS. Therefore, the fabrication method of the MOS device provided in this application embodiment does not only include the steps described above, but may also include steps such as forming a back metal electrode 60, a gate oxide layer 70, a polysilicon gate 80, an ILD insulating layer 90, and a front metal electrode JS. In order to clearly understand the fabrication method of the MOS device provided in this application embodiment, a more specific example (including steps a to m) will be used below to elaborate on the fabrication method of the MOS device.

[0075] Step a, such as Figure 5 As shown, a polycrystalline silicon thin film with a thickness of 1–1.2 μm is grown on the surface of substrate 10 (using SiC).

[0076] Step b, as follows Figure 6 As shown, using a polycrystalline silicon thin film as a mask, ion implantation regions P-base region 30 and P++ region 20 are formed by photolithography and etching of the polycrystalline silicon thin film. At the same time, aluminum ions of different energies and doses are implanted multiple times through these ion implantation regions to form box-shaped P-base region 30 and P++ region 20 in the substrate 10. The polycrystalline silicon thin film after photolithography and etching will be transformed into a polycrystalline silicon thin film segment (the part of the polycrystalline silicon thin film other than the polycrystalline silicon thin film segment is removed by photolithography and etching). The polycrystalline silicon thin film segment is located on the surface of the substrate 10 at the position corresponding to the gap JX, and the position on the surface of the substrate 10 without the polycrystalline silicon thin film segment is used as the above-mentioned ion implantation region.

[0077] Step c, as Figure 8As shown, a first silicon dioxide is deposited on the surface of the substrate 10 and the polysilicon film segment, with a thickness of 2-2.2 μm, and a side wall and an N+ to-be-implanted region are formed by etching the first silicon dioxide, and N-type ions are implanted through the N+ to-be-implanted region to form a self-aligned channel length (the channel is a self-aligned channel between the P-base region 30 and the N+ region 50, with a length not fixed, usually 0.5-0.7 μm), so as to form an initial N+ region on the surface of the substrate 10; wherein the side wall comprises a first side wall and a second side wall, the first side wall is connected to the edge of the polysilicon film segment close to the first side U of the substrate 10, and the second side wall is connected to the edge of the polysilicon film segment close to the second side V of the substrate 10, the width of the first side wall along the preset direction F is equal to the distance between the side of the first N+ region 51 away from the first P+ region 41 and the circumferential edge of the first P-base region 31, the width of the second side wall along the preset direction F is equal to the distance between the side of the second N+ region 52 away from the second P+ region 42 and the circumferential edge of the second P-base region 32, the first side wall and the second side wall are both the remaining part of the first silicon dioxide after etching (the part of the first silicon dioxide other than the side wall is removed due to etching), and the surface of the substrate 10 without the side wall and the position of the polysilicon film segment serves as the above-mentioned N+ to-be-implanted region; the initial N+ region comprises a first initial N+ region and a second initial N+ region, the first initial N+ region is located on the first side U of the surface of the substrate 10, and the second initial N+ region is located on the second side V of the surface of the substrate 10, the width of the first initial N+ region along the preset direction F is equal to the sum of the width of the first N+ region 51 along the preset direction F and the width of the first P+ region 41 along the preset direction F, and the width of the second initial N+ region along the preset direction F is equal to the sum of the width of the second N+ region 52 along the preset direction F and the width of the second P+ region 42 along the preset direction F;

[0078] Step d, the side wall and the polysilicon film segment are removed by dry etching, and a second silicon dioxide is deposited on the surface of the substrate 10, with a thickness of 2 μm;

[0079] Step e, as Figure 9As shown, the P+ to-be-injected region is formed by photoetching and etching the second silicon dioxide, while the corresponding part of the first initial N+ region to the first P+ region 41 and the corresponding part of the second initial N+ region to the second P+ region 42 are etched away through the P+ to-be-injected region, and the aluminum ion injection is performed multiple times through the P+ to-be-injected region, so as to form the first P+ region 41 connected with the first N+ region 51 and the second P+ region 42 connected with the second N+ region 52 in the substrate 10; wherein the second silicon dioxide after photoetching and etching is converted into a second silicon dioxide segment (the part of the second silicon dioxide other than the second silicon dioxide segment is etched away), the edge of the second silicon dioxide segment close to the first side U of the substrate 10 is aligned with the edge of the first N+ region 51 close to the first P+ region 41, the edge of the second silicon dioxide segment close to the second side V of the substrate 10 is aligned with the edge of the second N+ region 52 close to the second P+ region 42, and the position of the surface of the substrate 10 without the second silicon dioxide segment is the above-mentioned P+ to-be-injected region; the remaining part of the first initial N+ region after etching can be the first N+ region 51, and the remaining part of the second initial N+ region after etching can be the second N+ region 52;

[0080] Step f, wet etching the second silicon dioxide segment to remove the second silicon dioxide segment, while coating photoresist (thickness of 1.8-2.2 μm) on the surface of the substrate 10 and performing carbonization annealing to form a carbon film protective layer;

[0081] Step g, activation of high-temperature injected ions through the carbon film protective layer (i.e. high-temperature activation of the ions injected in steps b, c and e), temperature of 1700-1850 °C, time of 30 min, argon gas is introduced;

[0082] Step h, removing the carbon film protective layer and growing a gate oxide layer on the surface of the substrate 10, thickness of At the same time, depositing a polysilicon layer on the gate oxide layer, thickness of

[0083] Step i, photoetching and etching the gate oxide layer and the polysilicon layer to form the gate oxide layer 70 (including the first gate oxide layer 71, the second gate oxide layer 72 and the third gate oxide layer 73) and the polysilicon gate 80 as shown in Figure 2

[0084] Step j, depositing an ILD dielectric layer (thickness of ) on the surface of the substrate 10, the gate oxide layer 70 and the polysilicon gate 80, and photoetching and etching the ILD dielectric layer to form the ILD dielectric layer 90 as shown in Figure 2 ​The ILD insulating layers 90 (including the first ILD insulating layer 91, the second ILD insulating layer 92 and the third ILD insulating layer 93) and the contact holes of the MOS device (i.e. the gap between the first ILD insulating layer 91 and the second ILD insulating layer 92, and the gap between the first ILD insulating layer 91 and the third ILD insulating layer 93, one of which is a lead hole of the gate of the MOS device, and the other of which is a lead hole of the source of the MOS device) are shown in FIG. 1;

[0085] Step k, thinning the back surface of the substrate 10 (i.e. the side of the N+ base 11 away from the N-type buffer layer 12), and preparing a nickel layer (thickness of 1000A) on the back surface of the substrate 10, while performing RTP annealing;

[0086] Step l, depositing a preset metal on the surface of the substrate 10 and the ILD insulating layer 90, and performing photolithography and etching on the deposited preset metal to form the front metal electrode JS as shown in FIG. 1; Figure 2

[0087] Step m, covering the nickel layer prepared in step k on the back surface of the substrate 10 to form the back metal electrode 60 (as the drain of the MOS device) as shown in FIG. 1, thereby forming the electrode connection of the MOS device. Figure 2

[0088] In summary, the embodiment of the present application introduces the high-ion-concentration-doped P++ region 20 below the low-ion-concentration-doped P-base region 30, which not only does not require an additional photolithography process, but also effectively avoids the latch-up effect of the MOS device, thereby improving the avalanche tolerance of the MOS device, enabling the MOS device to have better reliability and use effect, and further expanding the application of the MOS device in the field of motor driving; moreover, the formation of the P++ region 20 in the embodiment of the present application can also control the expansion direction of the PN junction depletion layer in the MOS device, thereby effectively improving the punch-through voltage of the MOS device. In addition, in the manufacturing method, the channel length of the MOS device is determined by the self-alignment process, which on the one hand makes the channel resistance of the MOS device smaller, and on the other hand avoids the instability of the MOS device caused by the photolithography process error, ensures the consistency of the MOS device in the manufacturing process, maximally limits the on-resistance of the MOS device, reduces the power loss of the MOS device, and further improves the reliability of the MOS device.

[0089] It should be noted that each embodiment in the content of the present application is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts of each embodiment can be referred to each other. For product class embodiments, since they are similar to method class embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method class embodiment.​​​

[0090] It is also important to note that the use of relational terms, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between or among such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0091] The above description of disclosed embodiments is intended to be illustrative and not restrictive. Many modifications of the embodiments as well as many embodiments incorporating the general principles thereof can be made by persons of ordinary skill in the art, without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is not to be restricted except in light of the legal limitations provided in the claims and any other permitted scope of the disclosure.

Claims

1. A MOS device, characterized by, The substrate, the P+ region, the N+ region, the P-base region with low ion concentration doping, and the P++ region with high ion concentration doping; wherein the P++ region comprises a first P++ region and a second P++ region, the P-base region comprises a first P-base region and a second P-base region, the N+ region comprises a first N+ region and a second N+ region, the P+ region comprises a first P+ region and a second P+ region, the surface of the substrate has a first side and a second side opposite to the first side, and a preset direction from the first side to the second side; The first P+ region and the first N+ region in mutual connection are arranged on the surface of the substrate at the first side in the preset direction, the second N+ region and the second P+ region in mutual connection are arranged on the surface of the substrate at the second side in the preset direction, the first P-base region is arranged in the substrate and covers the first P+ region and the first N+ region, the side of the first N+ region away from the first P+ region is spaced from the periphery of the first P-base region, the second P-base region is arranged in the substrate and covers the second P+ region and the second N+ region, the side of the second N+ region away from the second P+ region is spaced from the periphery of the second P-base region, the first P++ region is arranged in the substrate and connected to the side of the first P-base region away from the first N+ region, the second P++ region is arranged in the substrate and connected to the side of the second P-base region away from the second N+ region, the first P-base region, the first P++ region, the second P-base region, and the second P++ region form a gap therebetween, the side of the first P-base region and the first P++ region close to the gap is aligned with each other, and the side of the second P-base region and the second P++ region close to the gap is aligned with each other; the P++ region with high ion concentration doping is located below the P-base region with low ion concentration doping.

2. The MOS device of claim 1, wherein, The substrate comprises an N+ substrate, an N-type buffer layer, and an N- epitaxial layer; wherein the N-type buffer layer is coated on the surface of the N+ substrate, and the N- epitaxial layer is coated on the surface of the N-type buffer layer.

3. The MOS device of claim 2, wherein, Further comprising a back metal electrode arranged on the side of the N+ substrate away from the N-type buffer layer.

4. The MOS device of claim 1, wherein, Further comprising a gate oxide layer coated on the surface of the substrate; wherein the gate oxide layer comprises a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer, the first gate oxide layer corresponds to the gap, the second gate oxide layer is located at the first side of the substrate, and the third gate oxide layer is located at the second side of the substrate. The MOS device further comprises a polysilicon gate arranged on the surface of the first gate oxide layer.

5. The MOS device of claim 4, wherein, Further comprising an ILD insulating layer, the ILD insulating layer is coated on the surface of the gate oxide layer; wherein the ILD insulating layer comprises a first ILD insulating layer, a second ILD insulating layer and a third ILD insulating layer, the first ILD insulating layer coats the first gate oxide layer and the polysilicon gate, the second ILD insulating layer is coated on the surface of the second gate oxide layer, and the third ILD insulating layer is coated on the surface of the third gate oxide layer.

6. The MOS device of claim 5, wherein, Further comprising a front metal electrode, the front metal electrode is arranged on the ILD insulating layer, between the first ILD insulating layer and the second ILD insulating layer, and between the first ILD insulating layer and the third ILD insulating layer; wherein the front metal electrode between the first ILD insulating layer and the second ILD insulating layer forms an ohmic contact with the first P+ region and the first N+ region, and the front metal electrode between the first ILD insulating layer and the third ILD insulating layer forms an ohmic contact with the second P+ region and the second N+ region.

7. A method of fabricating a MOS device, comprising: Comprising: acquiring a substrate; implanting to form a P-base region and a P++ region in the substrate; implanting to form a P+ region and an N+ region on the surface of the substrate; The surface of the substrate has opposite first and second sides and a preset direction from the first side to the second side; the P-base region is low ion concentration doping, the P++ region is high ion concentration doping, the P++ region includes a first P++ region and a second P++ region, the P-base region includes a first P-base region and a second P-base region, the N+ region includes a first N+ region and a second N+ region, and the P+ region includes a first P+ region and a second P+ region; the first P+ region and the first N+ region that are in connection with each other are arranged on the surface of the substrate at the first side along the preset direction, the second N+ region and the second P+ region that are in connection with each other are arranged on the surface of the substrate at the second side along the preset direction, the first P-base region is arranged in the substrate and covers the first P+ region and the first N+ region, one side of the first N+ region away from the first P+ region is spaced from the periphery of the first P-base region, the second P-base region is arranged in the substrate and covers the second P+ region and the second N+ region, one side of the second N+ region away from the second P+ region is spaced from the periphery of the second P-base region, the first P++ region is arranged in the substrate and connected to one side of the first P-base region away from the first N+ region, the second P++ region is arranged in the substrate and connected to one side of the second P-base region away from the second N+ region, a gap is formed between the first P-base region, the first P++ region and the second P-base region, the second P++ region that are in connection with each other, and one side of the first P-base region, the first P++ region close to the gap is aligned with each other, and one side of the second P-base region, the second P++ region close to the gap is aligned with each other; the high ion concentration doping P++ region is below the low ion concentration doping P-base region.

8. The method of fabricating a MOS device of claim 7, wherein, The implanting the P-base region and the P++ region in the substrate includes: Growth of a polysilicon film on the surface of the substrate; Using the polysilicon film as a mask, the ion implantation region of the P-base region and the P++ region is formed by photoetching and etching the polysilicon film; wherein the polysilicon film after photoetching and etching is changed into a polysilicon film segment, the polysilicon film segment is located at a position corresponding to the gap on the surface of the substrate, and the position of the surface of the substrate without the polysilicon film segment is used as the ion implantation region; The P-type ion implantation is performed through the ion implantation region for multiple times with different energies and doses to form the P-base region and the P++ region in the substrate.

9. The method of fabricating a MOS device of claim 8, wherein, The implanting the P+ region and the N+ region on the surface of the substrate includes: Depositing a first silicon dioxide on the surface of the substrate and the polysilicon film segment; forming side walls and N+ regions to be implanted by etching the first silicon dioxide; wherein the side walls include a first side wall and a second side wall, the first side wall is connected to the edge of the polysilicon film segment close to the first side of the substrate, the second side wall is connected to the edge of the polysilicon film segment close to the second side of the substrate, the width of the first side wall along the preset direction is equal to the distance between the side of the first N+ region away from the first P+ region and the circumference of the first P-base region, the width of the second side wall along the preset direction is equal to the distance between the side of the second N+ region away from the second P+ region and the circumference of the second P-base region, the first side wall and the second side wall are the remaining part of the first silicon dioxide after etching, and the surface of the substrate has no position of the side wall and the polysilicon film segment as the N+ region to be implanted; forming initial N+ regions on the surface of the substrate by implanting N-type ions through the N+ region to be implanted; wherein the initial N+ regions include a first initial N+ region and a second initial N+ region, the first initial N+ region is located on the first side of the surface of the substrate, and the second initial N+ region is located on the second side of the surface of the substrate, the width of the first initial N+ region along the preset direction is equal to the sum of the width of the first N+ region and the width of the first P+ region along the preset direction, and the width of the second initial N+ region along the preset direction is equal to the sum of the width of the second N+ region and the width of the second P+ region along the preset direction; removing the side walls and the polysilicon film segment by etching; depositing second silicon dioxide on the surface of the substrate; forming P+ regions to be implanted by photolithography and etching the second silicon dioxide; wherein the second silicon dioxide after photolithography and etching is changed into a second silicon dioxide segment, the edge of the second silicon dioxide segment close to the first side of the substrate is aligned with the edge of the first N+ region close to the first P+ region, the edge of the second silicon dioxide segment close to the second side of the substrate is aligned with the edge of the second N+ region close to the second P+ region, and the surface of the substrate has no position of the second silicon dioxide segment as the P+ region to be implanted; removing the part of the first initial N+ region corresponding to the first P+ region and the part of the second initial N+ region corresponding to the second P+ region by etching through the P+ region to be implanted; wherein the remaining part of the first initial N+ region after etching is the first N+ region, and the remaining part of the second initial N+ region after etching is the second N+ region; forming the first P+ region connected to the first N+ region and the second P+ region connected to the second N+ region by implanting P-type ions through the P+ region to be implanted.

10. Use of the MOS device according to any one of claims 1-6 in power electronic equipment.

11. Use of the MOS device manufactured by the manufacturing method of the MOS device according to any one of claims 7-9 in power electronic equipment.

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