Reference voltage buffer

Abstract

The application discloses a reference voltage buffer, comprising: an output stage, the output stage comprising first to fifth transistors, the gate of the first transistor being connected with a second bias voltage, the source of the first transistor being connected with a ground terminal, the drain of the first transistor being connected with the source of a second transistor and the drain of a third transistor, the gate of the second transistor being connected with a first bias voltage, the drain of the second transistor, the drain and the gate of a fourth transistor, and the gate of a fifth transistor being connected with each other, and the sources of the fourth and fifth transistors being connected with a power supply terminal; an operational amplifier, the inverting input terminal of the operational amplifier being connected with the drain of the fifth transistor and the source of the third transistor, the non-inverting input terminal of the operational amplifier being connected with a reference voltage, and the output terminal of the operational amplifier being connected with the gate of the third transistor; and a current injection module, the current injection module being connected with the operational amplifier and injecting currents into the operational amplifier respectively. The voltage regulating range of the application is large, the precision is high, and meanwhile, the current driving capability of the reference circuit is not affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit, and in particular, to a reference voltage buffer. BACKGROUND

[0002] The reference voltage buffer is a circuit for providing a reference voltage with driving capability in an analog-to-digital converter, which requires stable voltage output while providing current output and input. In particular, in the application of high-speed medium-precision successive approximation analog-to-digital converter, the multi-channel interleaving technology is widely used, and there is a random error between the reference voltages of different channels, which will seriously affect the performance of the analog-to-digital converter after interleaving, so the reference voltage of each channel can be finely adjusted by digital control within a certain range of uniform step. At the same time, due to the large number of channels, the power consumption of each channel is required to be high. Therefore, the reference buffer needs to realize the function of fast recovery of output voltage under low power consumption, and the output voltage can be configured by digital control. SUMMARY

[0003] The present application aims to provide a reference voltage buffer with large voltage adjustment range and high precision, without affecting the current driving capability of the reference circuit.

[0004] The present application discloses a reference voltage buffer, comprising:

[0005] an output stage, the output stage comprising first to fifth transistors, the gate of the first transistor being connected to a second bias voltage, the source of the first transistor being connected to a ground terminal, the drain of the first transistor being connected to the source of the second transistor and the drain of the third transistor, the gate of the second transistor being connected to a first bias voltage, the drain of the second transistor, the drain and the gate of the fourth transistor, and the gate of the fifth transistor being connected, the sources of the fourth and fifth transistors being connected to a power supply terminal;

[0006] an operational amplifier, the inverting input terminal of the operational amplifier being connected to the drain of the fifth transistor and the source of the third transistor, the non-inverting input terminal of the operational amplifier being connected to a reference voltage, and the output terminal of the operational amplifier being connected to the gate of the third transistor; and

[0007] a current injection module, the current injection module being connected to the operational amplifier and injecting current into the operational amplifier respectively.

[0008] In one preferred embodiment, the operational amplifier comprises: a load module, sixth to eighth transistors, wherein the drains of the sixth and seventh transistors are connected to the load module, the sources of the sixth and seventh transistors are connected to the drain of the eighth transistor, the gate of the eighth transistor is connected to a third bias voltage, the source of the eighth transistor is connected to the ground terminal, the gate of the sixth transistor is connected to the gate of the third transistor, and the gate of the seventh transistor is connected to the reference voltage.

[0009] In one preferred embodiment, the current injection unit comprises a first branch and a second branch, each of which comprises: ninth to thirteenth transistors, the sources of the ninth to eleventh transistors are connected to the power supply terminal, the drain of the ninth transistor and the gates of the ninth to eleventh transistors are connected to the current steering digital-to-analog converter, the drain of the tenth transistor is connected to the drain of the twelfth transistor, the source of the twelfth transistor and the gates of the twelfth and thirteenth transistors are connected to the ground terminal, and the source of the thirteenth transistor is connected to the ground terminal, wherein the drains of the sixth transistor are connected to the drains of the eleventh transistor in the first branch and the thirteenth transistor in the second branch, respectively, and the drains of the seventh transistor are connected to the drains of the thirteenth transistor in the first branch and the eleventh transistor in the second branch, respectively.

[0010] In one preferred embodiment, the load unit comprises fourteenth to nineteenth transistors, the sources of the fourteenth to sixteenth transistors are connected to the power supply terminal, the gates and drains of the fourteenth transistor and the gate of the sixteenth transistor are connected to the drains of the eleventh transistor in the first branch and the thirteenth transistor in the second branch, the gates and drains of the fifteenth transistor and the gate of the seventeenth transistor are connected to the drains of the thirteenth transistor in the first branch and the eleventh transistor in the first branch, the drain of the fourteenth transistor is connected to the gates and drains of the eighteenth transistor and the gate of the nineteenth transistor, and the drain of the seventeenth transistor is connected to the gate of the third transistor and the drain of the nineteenth transistor.

[0011] In one preferred embodiment, the current steering digital-to-analog converter receives an 8-bit digital signal.

[0012] In one preferred embodiment, a capacitor is further connected between the drain of the fifth transistor and the source of the third transistor and the ground terminal.

[0013] Compared with the prior art, the reference voltage buffer of the present application has at least the following beneficial effects:

[0014] The application is mainly used for reference driving circuit of high-speed multi-path interleaving successive approximation analog-digital converter, and has two-stage amplifier structure formed by output stage with push-pull function and gain stage with high gain, which can ensure the accuracy of output reference voltage and has strong current driving capability. The performance characteristics have two obvious advantages, one is to reduce the requirement of output end decoupling capacitor, thereby saving circuit area, and the other is to reduce the requirement of circuit static current, thereby reducing the power consumption of the circuit. In order to perform multi-path interleaving reference matching, the output voltage of the reference driving circuit is adjustable, so the circuit adds current steering digital-to-analog converter to inject current into the output of the first stage operational amplifier to achieve the purpose of adjusting the output of the reference circuit. The advantages of this scheme are large voltage adjustment range, high precision, and do not affect the current driving capability of the reference circuit.

[0015] A large number of technical features are described in the specification of the present application, which are distributed in various technical solutions. If all possible combinations of technical features (i.e. technical solutions) of the present application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above invention content of the present application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be regarded as having been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role, and can only be used at the same time in technology, and feature E can be combined with feature C in technology. Therefore, the scheme of A+B+C+D should not be regarded as having been described because it is technically infeasible, and the scheme of A+B+C+E should be regarded as having been described. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of a reference voltage buffer in an embodiment of the present application.

[0017] Figure 2 is a schematic diagram of a gain stage circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In the following description, many technical details are presented in order to make the reader better understand the present application. However, those skilled in the art can understand that the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail with reference to the drawings.

[0020] The application discloses a reference voltage buffer, Figure 1 A schematic diagram of a reference voltage buffer in an embodiment is shown. The reference voltage buffer includes an output stage and a gain stage. Figure 2 A schematic diagram of a gain stage circuit in an embodiment is shown. The gain stage includes an operational amplifier 101 and a current injection module.

[0021] The output stage includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The gate of the first transistor M1 is connected to a second bias voltage VB2, the source of the first transistor M1 is connected to a ground terminal, the drain of the first transistor M1 is connected to the source of the second transistor M2 and the drain of the third transistor M3, the gate of the second transistor M2 is connected to a first bias voltage VB1, the drain of the second transistor M2, the drain and gate of the fourth transistor M4, and the gate of the fifth transistor M5 are connected, and the sources of the fourth transistor M4 and the fifth transistor M5 are connected to a power supply terminal.

[0022] The inverting input terminal of the operational amplifier 101 is connected to the drain of the fifth transistor M5 and the source of the third transistor M3, the non-inverting input terminal of the operational amplifier 101 is connected to a reference voltage VIN, and the output terminal of the operational amplifier 101 is connected to the gate (S1) of the third transistor M3. In an embodiment, the operational amplifier 101 includes a load module, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The drains of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the load module, the sources of the sixth transistor M6 and the seventh transistor M7 are both connected to the drain of the eighth transistor M8, the gate of the eighth transistor M8 is connected to a third bias voltage VB3, the source of the eighth transistor M8 is connected to the ground terminal, the gate of the sixth transistor M6 is connected to the gate (S1) of the third transistor M3, and the gate of the seventh transistor M7 is connected to the reference voltage VIN. The current injection module is connected to the operational amplifier 101 and injects currents into the operational amplifier 101.

[0023] In one embodiment, the current injection unit comprises a first branch 102 and a second branch 103, the first branch 102 and the second branch 103 respectively comprise: a ninth transistor M9, M9', a tenth transistor M10, M10', an eleventh transistor M11, M11', a twelfth transistor M12, M12', and a thirteenth transistor M13, M13', the source of the ninth transistor M9, M9', the tenth transistor M10, M10', and the eleventh transistor M11, M11' are connected to the power supply end, the drain of the ninth transistor M9, M9', the gate of the ninth transistor M9, M9', the tenth transistor M10, M10', and the eleventh transistor M11, M11' are connected to the current digital-to-analog converter 104, the drain of the tenth transistor M10, M10' is connected to the drain of the twelfth transistor M12, M12', the source of the twelfth transistor M12, M12', the gate of the twelfth transistor M12, M12', and the gate of the thirteenth transistor M13, M13' are connected to the ground, and the source of the thirteenth transistor M13, M13' is connected to the ground, wherein the drain of the sixth transistor M6 is connected to the drain of the eleventh transistor M11 in the first branch 102 and the drain of the thirteenth transistor M13' in the second branch 103, respectively, and the drain of the seventh transistor M7 is connected to the drain of the thirteenth transistor M13' in the first branch 102 and the drain of the eleventh transistor M11' in the second branch 103, respectively.

[0024] In one embodiment, the load unit comprises a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19, the source of the fourteenth transistor M14, the fifteenth transistor M15, and the sixteenth transistor M16 is connected to the power supply end, the gate of the fourteenth transistor M14 and the gate of the sixteenth transistor M16 are connected to the drain of the eleventh transistor M11 in the first branch 102 and the drain of the thirteenth transistor M13' in the second branch 103, the gate of the fifteenth transistor M15 and the gate of the seventeenth transistor M17 are connected to the drain of the thirteenth transistor M13 in the first branch 102 and the drain of the eleventh transistor M11 in the first branch 102, the drain of the sixteenth transistor M16 is connected to the gate and the drain of the eighteenth transistor M18 and the gate of the nineteenth transistor M19, the drain of the seventeenth transistor M17 is connected to the gate of the third transistor M3 (S1) and the drain of the nineteenth transistor M19.

[0025] In one embodiment, the current steering digital-to-analog converter 104 receives an 8-bit digital signal. In the default mode, the 8-bit digital signal received by the current steering digital-to-analog converter 104 is at the middle value (128), at which the differential output current of the current steering digital-to-analog converter is zero, no differential current is injected into transistors M9 and M9', and the reference voltage output will follow the reference input (VIN). If the 8-bit digital signal received by the digital-to-analog converter 104 is greater than the middle value (between 128 and 255), the differential output current of the current steering digital-to-analog converter will be positive, IP > IN, transistor M11' injects current into transistor M7, and transistor M13' extracts current from transistor M6, which ultimately results in a decrease in the output SI voltage generated by the reference, the decrease being proportional to the change in the 8-bit digital signal. Conversely, when the 8-bit digital signal received by the digital-to-analog converter 104 decreases (0-128), the opposite process occurs, resulting in an increase in the output SI voltage generated by the reference.

[0026] In one embodiment, a capacitor (not shown) is connected between the drain of the fifth transistor M5 and the source of the third transistor M3. When the load of the circuit draws current from the output, the output voltage of the reference circuit will decrease. At this time, the output stage loop begins to operate, and because the source voltage of the transistor M3 decreases, the current of the transistor M3 decreases, the current of the constant current source formed by the transistor Ml will flow through the transistor M2 instead, and the gate voltage of the transistor M4 decreases. The voltage difference between the gate and source of the transistor M5 is thus increased, the current of the transistor M5 increases, and the output voltage increases, and the loop continues to operate until the voltage increases to the loop stable point.

[0027] It should be noted that the relational terms herein such as first and second and the like merely identify one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The application file contains at least one expression of a "means or step for" performing an identified function or step. It will be understood that the application is not limited to the means or step recited, but is intended to cover each and every adaptation of the means or step which performs the same function or step of which the means or step belongs, and replaces the same. The use of the terms "first", "second", and the like does not imply any physical or logical relationship between elements. The use of the terms "first", "second", and the like does not imply any physical or logical relationship between elements. The use of the terms "first", "second", and the like does not imply any physical or logical relationship between elements. The plural forms "a", "an", and the like can include singular forms, unless expressly surmised otherwise by context.

[0028] All documents mentioned in this specification are hereby incorporated by reference in their entirety to provide additional description of the application. In addition, it should be appreciated that modifications can be made to the preferred embodiments and yet, be within the scope of the application. Therefore, the above description should not be construed as limiting, but merely as illustrative of the present application.

Claims

1. A reference voltage buffer, characterized in that, include: An output stage, comprising a first to a fifth transistor, wherein the gate of the first transistor is connected to a second bias voltage, the source of the first transistor is connected to ground, the drain of the first transistor is connected to the source of the second transistor and the drain of the third transistor, the gate of the second transistor is connected to a first bias voltage, and the drain of the second transistor, the drain and gate of the fourth transistor are connected to the gate of the fifth transistor, and the sources of the fourth and fifth transistors are connected to a power supply. An operational amplifier, wherein the inverting input terminal of the operational amplifier is connected to the drain of the fifth transistor and the source of the third transistor, the non-inverting input terminal of the operational amplifier is connected to a reference voltage, and the output terminal of the operational amplifier is connected to the gate of the third transistor; and A current injection module is connected to the operational amplifier and injects current into the operational amplifier.

2. The reference voltage buffer as described in claim 1, characterized in that, The operational amplifier includes: a load module and a sixth to an eighth transistor, wherein the drains of the sixth and seventh transistors are respectively connected to the load module, the sources of the sixth and seventh transistors are both connected to the drain of the eighth transistor, the gate of the eighth transistor is connected to a third bias voltage, the source of the eighth transistor is connected to ground, the gate of the sixth transistor is connected to the gate of the third transistor, and the gate of the seventh transistor is connected to the reference voltage.

3. The reference voltage buffer as described in claim 2, characterized in that, The current injection module includes a first branch and a second branch, each including a ninth to a thirteenth transistor. The sources of the ninth to eleventh transistors are all connected to the power supply terminal. The drain of the ninth transistor and the gates of the ninth to eleventh transistors are all connected and connected to a current-controlled digital-to-analog converter. The drain of the tenth transistor is connected to the drain of the twelfth transistor. The source of the twelfth transistor and the gates of the twelfth and thirteenth transistors are connected and connected to the ground terminal. The source of the thirteenth transistor is connected to the ground terminal. The drain of the sixth transistor is connected to the drain of the eleventh transistor in the first branch and the drain of the thirteenth transistor in the second branch. The drain of the seventh transistor is connected to the drain of the thirteenth transistor in the first branch and the drain of the eleventh transistor in the second branch.

4. The reference voltage buffer as described in claim 3, characterized in that, The load module includes fourteenth to nineteenth transistors. The sources of the fourteenth to sixteenth transistors are connected to the power supply terminal. The gate and drain of the fourteenth transistor and the gate of the sixteenth transistor are connected to the drain of the eleventh transistor in the first branch and the drain of the thirteenth transistor in the second branch. The gate and drain of the fifteenth transistor and the gate of the seventeenth transistor are connected to the drain of the thirteenth transistor in the first branch and the drain of the eleventh transistor in the first branch. The drain of the fourteenth transistor is connected to the gate and drain of the eighteenth transistor and the gate of the nineteenth transistor. The drain of the seventeenth transistor is connected to the gate of the third transistor and the drain of the nineteenth transistor.

5. The reference voltage buffer as described in claim 3, characterized in that, The current-controlled digital-to-analog converter receives 8-bit digital signals.

6. The reference voltage buffer as claimed in claim 1, characterized in that, A capacitor is also connected between the drain of the fifth transistor and the source of the third transistor and ground.

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