A general lightweight hash processing method, system and storage medium

Abstract

The application discloses a general lightweight hash processing method and system and a storage medium. A linear feedback shift register (LFSR) is selected, and a register state conversion function is used to perform state conversion on the linear feedback shift register (LFSR). The output of the linear feedback shift register (LFSR) is used to initialize the internal state of a hash algorithm in combination with an initialization algorithm. Data for which a hash value needs to be calculated is input, and an update algorithm is used to update the initialized internal state. The data for which the hash value needs to be calculated is filled data. A determination algorithm is used to post-process the updated internal state to generate a final hash value. The application solves the speed and security problems of existing hash processing, is simple to implement, can flexibly adjust the length and starting point, is beneficial to parallel and rapid calculation, has small required storage space, and can dynamically append a hash word to eliminate collision when a hash collision occurs, thereby improving security.

Description

Technical Field

[0001] This invention relates to the technical field of information technology, and in particular to a general lightweight hash processing method, system, and storage medium. Background Technology

[0002] A hash function compresses data from an arbitrary domain to a fixed range. The output of the function is called the hash value of the input data, or simply a hash. The phenomenon that multiple different input data produce the same hash value is called a collision. For a given hash function, if it is computationally infeasible to find two different input data from the domain to produce a collision, then we say that the hash function is collision-resistant. It is worth noting that collision-resistant does not mean collision-free, because for a compression function, collisions are theoretically unavoidable.

[0003] Currently, most hash algorithms are based on The hash function based on the MD structure (hereinafter referred to as MD structure) is used in hash algorithms, including the most popular MD5, SHA-1, and SHA-2. Because the internal state and the final hash value of the hash function based on the MD structure are the same, there is a relatively simple and direct relationship between the two, making it relatively vulnerable to attacks. The security of the MD structure poses a significant problem. Current methods to address hash security include modifying the MD structure to create more secure MD variants and developing new algorithms based on non-MD structures, such as wide-pipe structures and new algorithms based on sponge functions. However, wide-pipe structures generally degrade performance. Currently, algorithms based on sponge functions are considered relatively advanced and secure, including the latest SHA-3 standard, which is designed based on sponge functions. However, some research indicates that algorithms based on sponge functions are susceptible to sliding attacks. Furthermore, although SHA-3 is more efficient than SHA-2, it is still not lightweight enough, and its speed is slower than MD5 and SHA-1. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the existing problems in the field of information technology, the present invention is proposed.

[0006] Therefore, the technical problem solved by this invention is that existing hash processing algorithms are complex in structure, have low performance, are vulnerable to attacks, and have low security.

[0007] To address the aforementioned technical problems, in a first aspect, the present invention provides a general lightweight hash processing method applied to a general lightweight hash processing system. The method includes: selecting a linear feedback shift register (LFSR) and performing state transitions on the LFSR using a register state transition function; initializing the internal state of the hash algorithm using the output of the LFSR in conjunction with an initialization algorithm; inputting data for which a hash value needs to be calculated, and updating the initialized internal state using an update algorithm, wherein the data for which a hash value needs to be calculated is the padded data; and post-processing the updated internal state using a determination algorithm to generate the final hash value.

[0008] As a preferred embodiment of the general lightweight hash processing method described in this invention, the initialization algorithm is expressed as follows:

[0009] Constant: Switching mask m

[0010] Input: An uninitialized internal matrix M = [S0; S1; ...; S n Returns the initialized M, s, t, x, and three 64-bit words s, t, x.

[0011] The i-th row S of the inner matrix M i =[a i b i c i d i The state values ​​of the four registers starting from the i×68th state are directly set, while the switching mask m is used as the first state value of the registers. Additionally, s, t, and x are initialized, with s and t set to (a0+b0+c0+d0) and x set to 0. The specific steps are as follows:

[0012]

[0013] As a preferred embodiment of the general lightweight hash processing method described in this invention, the update algorithm is expressed as:

[0014] Input: The data whose hash value needs to be calculated.

[0015] Result: The updated internal matrix M = [S0; S1; ...; S...] n ] and three 64-bit words s, t, x

[0016] The update algorithm updates the internal state using each 64-bit word of the input data, which has been padded to a length containing one or more complete 64-bit words. The input to the update algorithm is a 64-bit state word in the register, a 64-bit word of the padded data, and the current internal state. The output of the update algorithm is the new internal state returned by each call to the update algorithm. The specific steps are as follows:

[0017]

[0018] in, The XOR operation is used for bitwise operations, <<< is used for left rotation bitwise operations, and ■+ is used for dot addition operations. This is a point XOR bitwise operation.

[0019] As a preferred embodiment of the general lightweight hash processing method described in this invention, the data padding method used for the padded data includes free suffix padding and free prefix padding.

[0020] As a preferred embodiment of the general lightweight hash processing method described in this invention, the free prefix padding is characterized by:

[0021] Data population includes the following steps:

[0022] Step 1: Append enough zeros. If the original data contains exactly one or more complete 64-bit words, then no zeros need to be appended.

[0023] Step 2: Append a 64-bit word, denoted as w1, which is calculated from the data length (number of bytes in the data) z and the word s, i.e.:

[0024] s←lfsr(s)

[0025]

[0026] As a preferred embodiment of the general lightweight hash processing method described in this invention, the determining algorithm compares S0 = [a0, b0, c0, d0] with each of the remaining sets S i =[a i b i c i d i The mixture is then combined, and the result is compressed to generate the hash word h. i Where i = 1, 2, ..., n, the determination algorithm is expressed as:

[0027] Input: Inner matrix M = [S0; S1; ...; S n ]

[0028] Result: Hash value H = h1h2…h n

[0029]

[0030]

[0031] Here, >>> represents the right rotation bitwise operation.

[0032] As a preferred embodiment of the general lightweight hash processing method described in this invention, the update algorithm and the determination algorithm are designed in a two-layer structure, wherein the upper layer is the update algorithm and the lower layer is the determination algorithm.

[0033] Secondly, a general-purpose lightweight hash processing system is provided, the system comprising: a processor, a network module, and a memory; wherein the processor and the memory communicate through the network module, and the processor reads and runs a computer program from the memory;

[0034] The state transition module is used to: use a register state transition function as a transition tool to perform state transition on the register, wherein the register is a linear feedback shift register; the initialization module is used to: initialize the internal state of the hash algorithm according to the output of the register in the state transition module and use an initialization algorithm as an initialization tool; the update module is used to: use the output of the state transition module and the initialization module, and in combination with the filling data, use an update algorithm to update the internal state of the initialized hash algorithm; the determination module is used to: post-process the updated internal state to generate the final hash value.

[0035] Thirdly, a computer-readable storage medium is provided, wherein at least one instruction, at least one program, code set, or instruction set is stored in the storage medium, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the above-described general lightweight hash processing method.

[0036] The beneficial effects of the present invention are as follows: The general lightweight hash processing method, system and storage medium provided in the embodiments of this application solve the speed and security problems of hash processing by using a balanced maximum length linear feedback shift register (lfsr) to independently calculate each hash word using a single algorithm. Furthermore, the general lightweight hash processing method of this application is simple to implement, can flexibly adjust the length and starting point, facilitates parallel and fast calculation, and requires little storage space. When a hash collision occurs, hash words can be dynamically appended to eliminate the collision, thereby improving the security of the hash processing method. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0038] Figure 1 This is a block diagram of a general lightweight hash processing system described in an embodiment of this application;

[0039] Figure 2 This is a flowchart illustrating a general lightweight hash processing method as described in an embodiment of this application.

[0040] Figure 3 This is a schematic diagram of the overall structure of a general lightweight hash processing method described in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the Galois linear feedback shift register lfsr described in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram illustrating the construction of a general lightweight hash processing method for calculating the hash value of structured block data, as described in an embodiment of this application.

[0043] Figure 6 This is a block flowchart of a general-purpose lightweight hash processing system processor according to an embodiment of this application. Detailed Implementation

[0044] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0046] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0047] This invention is described in detail with reference to the accompanying drawings. When describing the embodiments of this invention, the drawings are merely examples and should not be construed as limiting the scope of protection of this invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0048] In the description of this invention, similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first, second or third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0050] Figure 1 A block diagram of a general-purpose lightweight hash processing system provided in an embodiment of this application is shown. The general-purpose lightweight hash processing system in this embodiment can be a server with data storage, transmission, and processing functions, such as... Figure 1 As shown, the general-purpose lightweight hash processing system 100 includes a processor 110, a network module 120, and a memory 130.

[0051] The memory 110, processor 120, and network module 130 are electrically connected directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The memory 110 stores data generated during processing by the processor 120, which executes various functional applications and general lightweight hash processing by running software programs and modules stored in the memory 110.

[0052] The memory 110 may be, but is not limited to, Random Access Memory (RAMD), Read Only Memory (ROMD), Programmable Read-Only Memory (PROMD), Erasable Programmable Read-Only Memory (EPROMND), Electrically Erasable Programmable Read-Only Memory (EEPROMD), etc. The memory 110 stores programs and processing data for the processor 120. Upon receiving an execution instruction, the processor 120 executes the program.

[0053] The network module 130 is used to establish a communication connection between the processor 120 and other communication terminal devices via a network, enabling the transmission and reception of network signals and data. The network signals may include wireless signals or wired signals.

[0054] Understandable. Figure 1 The structure shown is for illustrative purposes only; the general-purpose lightweight hash processing system 100 may also include components that are more robust than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0055] This application also provides a computer-storable medium storing a computer program that implements the above-described method when the computer program is run.

[0056] Reference Figures 2-4 This is a schematic diagram illustrating a general lightweight hash processing method provided in this embodiment. The method steps defined in the relevant process are applied to the general lightweight hash processing system 100 and can be implemented by the processor 120. Figures 2-3 It can be seen that the method includes the following steps S1 to S4:

[0057] S1: Select the linear feedback shift register lfsr and use the register state transition function to perform state transition on the linear feedback shift register lfsr;

[0058] Please refer to Figure 4 The 64 bits of the register are numbered sequentially from high to low as 64, 63, ..., 1, and each bit can take the binary value 0 or 1. Figure 4In the diagram, the current state of the register is 01101110…11001001. The bits that affect the next state are called taps. The tap sequence in the diagram is [64,61,59,57,…,8,6,5,3], which can be equivalently represented by the characteristic polynomial x. 64 +x 61 +x 59 +x 57 +…+x 8 +x 6 +x 5 +x 3 +1 is used to represent this. In a polynomial, the constant "1" does not represent a specific tap; it refers to a single bit of input. The rightmost bit is the output bit, and the resulting sequence is called the output stream. In mathematical operations, the tap sequence is represented by the value of the switching mask. For example, the tap sequence [64,61,59,57,…,8,6,5,3] corresponds to the binary value 10010101…10110101 or the hexadecimal value 0x95…b5 (where the prefix 0x indicates that the following value is hexadecimal). That is, the switching mask is 0x95…b5. With the switching mask, the next state can be calculated from the current state of the register. For example, assuming the current state is y and the switching mask is m, the state update can be performed using the following simple calculation:

[0059]

[0060] Here, & represents the AND bitwise operation, and >> represents the logical right shift operation. This is an XOR bitwise operation.

[0061] Optionally, in the specific implementation, the linear feedback shift register lfsr can be a 64-bit balanced maximum length linear feedback shift register lfsr, whose corresponding switching mask is m = 0x95ac9329ac4bc9b5. This mask is used as a constant, and the current register state y is input into the function to obtain the new register state y. The function is as follows:

[0062] Constant: Switching mask m = 0x95ac9329ac4bc9b5

[0063] Input: Current register state y

[0064] Returns: New register status y

[0065] 1. Function lfsr(y):

[0066] 2.i←y&1

[0067] 3.y←y>>1

[0068] 4. If i ≠ 0

[0069] 5.

[0070] 6. Return y

[0071] After calculation, the final y value is the new state. During the calculation, the initial state of the register cannot be zero, otherwise its state will not change and will remain zero forever.

[0072] Obtaining a hash value requires three steps: calculation, initialization, updating, and determination. The resulting hash value is of variable length, and each hash value contains one or more 64-bit unsigned integers. For convenience, we will refer to these 64-bit unsigned integers as 64-bit words or simply words in the following description. Except during the initialization phase, each word of the hash value is independent and calculated independently, making S... i =[a i b i c i d i (i = 0, 1, 2, ..., n) indicates a string containing four characters a i b i c i and d i The set of hash algorithms, the internal state of which can be represented as an (n+1)×4 internal matrix M, where M:

[0073]

[0074] The first set S0 is used to calculate each hash word, and the other sets S1, S2, ..., S... n Used only for calculating the corresponding hash words h1, h2, ..., h n .

[0075] S2: Use the output of the linear feedback shift register lfsr, combined with the initialization algorithm, to initialize the internal state of the hash algorithm.

[0076] Optionally, in this embodiment, the initialization algorithm is expressed as the formula:

[0077] Constant: Switching mask m = 0x95ac9329ac4bc9b5

[0078] Input: An uninitialized internal matrix M = [S0; S1; ...; S n ] and three 64-bit words s, t, x

[0079] Returns: Initialized M, s, t, x

[0080] The i-th row S of the inner matrix M i =[a i bi c i d i The state values ​​of the four registers starting from the i×68th state are directly set, while the switching mask m is used as the first state value of the register. Additionally, words s, t, and x are initialized; words s and t are set to (a0+b0+c0+d0), and x is set to 0. The specific steps are as follows:

[0081]

[0082] The initialization process ensures that all words a0, b0, c0, d0, a1, b1, c1, d1, ... are non-zero and distinct, and that any two sets S... i and S j (i≠j) does not overlap, meaning that any word in one set is more than 64 register states away from any word in another set. For example, the first word a1 in set S1 is 65 register states away from the last word d0 in set S0.

[0083] S3: Input the data whose hash value needs to be calculated, update the initialized internal state using the update algorithm, and the data whose hash value needs to be calculated is the filled data.

[0084] Optionally, in this embodiment, the update algorithm is expressed as:

[0085] Input: The data whose hash value needs to be calculated.

[0086] Result: The updated internal matrix M = [S0; S1; ...; S...] n ] and three 64-bit words s, t, x

[0087] The update algorithm updates the internal state using each 64-bit word of the input data, which has been padded to a length containing one or more complete 64-bit words. The input to the update algorithm is a 64-bit state word in a register, a 64-bit word of the padded data, and the current internal state. The output of the update algorithm is the new internal state returned by each update algorithm call. The specific steps are as follows:

[0088]

[0089]

[0090] Where <<< represents left rotation bitwise operations, and ■+ represents dot addition operations. For point XOR bitwise operations, the two point operators "■+" and "■" operate on each element of two compound operands (or a compound operand and a regular operand) one by one. For example, if S1 = [a1,b1,c1,d1] and S0 = [a0,b0,c0,d0], then... If x is a regular operand, then S1■+x=[a1+x,b1+x,c1+x,d1+x]. In this application, composite variables are represented by uppercase letters, and regular variables are represented by lowercase letters.

[0091] Furthermore, the data filling methods used include free suffix filling and free prefix filling. Taking free prefix filling as an example, the above data filling process includes two steps.

[0092] Step 1: Simply append enough zeros (if the original data contains exactly one or more complete 64-bit words, then no zeros need to be appended);

[0093] Step 2: Append a 64-bit word, denoted as w1, which is calculated from the data length (number of bytes in the data) z and the word s, i.e.:

[0094] s←lfsr(s)

[0095]

[0096] The second step above calls a state transition function once, thus consuming the internal state of an additional linear register. From Figure 3 As can be seen, the last character of the filled data is set to Where z is the number of bytes in the unpadded data, this will consume an extra word from the register, effectively resulting in S being input to the last two registers. k-1 and S k+1 A gap is created between them, and this gap is the key to achieving free prefix filling.

[0097] In the first set S0, the values ​​of the four words a0, b0, c0, and d0 remain distinct throughout the update process, and in any other set S... i (i>0) contains the four characters a i b i c i and d i The values ​​of are not guaranteed to be different during the update step, but for any two words, such as 'a', they are not guaranteed to be different. i and b i They cannot be equal twice in a row, because once they are equal, they will be XORed with two words a0 and b0 with different values ​​during the next update, and the resulting operations will definitely not be equal.

[0098] In the data input within the update algorithm, the internal state word s can be viewed as a special counter. Unlike a regular counter that increments by 1 each time, it simply ensures that it takes a different value each time. This word actually serves as the second (automatically generated) input in addition to the normal data input, and it has the function of uniquely identifying each normal data word. It enhances the security of the hash algorithm and is the key to enabling the algorithm to have the free prefix padding property.

[0099] S4: The general-purpose lightweight hash processing system uses a deterministic algorithm to post-process the updated internal state and generate the final hash value.

[0100] Optionally, the determination algorithm used in this embodiment will compare S0 = [a0, b0, c0, d0] with each of the remaining sets S i =[a i b i c i d i The mixture is then combined, and the result is compressed to generate the hash word h. i Where i = 1, 2, ..., n, the algorithm for determining i is expressed as:

[0101] Input: Inner matrix M = [S0; S1; ...; S n ]

[0102] Result: Hash value H = h1h2…h n

[0103]

[0104]

[0105] Here, >>> represents the right rotation bitwise operation.

[0106] The final hash value H is the hash value of each hash word h. i The concatenation, that is, for a hash value containing n words: H = h1h2…h i , is a hash value of variable length.

[0107] Furthermore, the update algorithm and the determination algorithm are designed with a two-layer structure, with the update algorithm at the top and the determination algorithm at the bottom. The top layer uses the update algorithm to absorb data and update the internal state in the process; this layer uses a simple, efficient, and parallel-operation-capable algorithm to achieve high-speed operation. The bottom layer uses the determination algorithm to fully mix the internal state after absorbing the data, and then compresses it with a high compression ratio to generate the final hash value, thereby enhancing the function's collision resistance and one-wayness. The use of different compression functions in the top and bottom layers not only prevents sliding attacks but also allows for optimization of each layer according to different requirements.

[0108] In this embodiment, the initialized word s is loaded into the linear feedback shift register lfsr. Word s is then continuously updated. Word t is used to store the accumulated values ​​of word s during the update steps, requiring repeated calls to the update algorithm. Word s is updated only through the state transition function and is unaffected by any input data; it is not considered part of the internal state. Word t is the accumulation of word s values ​​and is also not considered part of the internal state. Word x is affected by both input data and word s; it is part of the internal state.

[0109] It adopts a dual-layer design to balance speed and safety.

[0110] The hash value calculated in this application can start at any byte of any hash word and end at any byte, allowing B to... ij Represents the i-th hash word h i If the j-th byte is h1h2...h n =B 11 B 12 ...B 18 B 21 B 22 ...B 28 ...B n1 B n2 ...B n8 For example, an application can choose to discard 11 bytes at the beginning of the hash value and 5 bytes at the end, thus obtaining a new hash value H=B. 24 B 25 B 26 B 27 B 28 ...B n1 B n2 B n3 When a hash value is represented as a hexadecimal string, the number of bytes discarded at the beginning (e.g., 11, or hexadecimal b) is displayed as a prefix of the hash value.

[0111] This application embodiment utilizes the maximum length linear feedback shift register lfsr to generate a long-period non-repeating pseudo-random number series. The long-period non-repeating pseudo-random number series can achieve the following functions: initializing constants, automatically generating additional inputs other than data, identifying data blocks, and generating gaps to achieve free prefix filling.

[0112] Furthermore, the final output of this application is a variable-length hash value, which can resolve the hash collision problem. In a typical application scenario, the application predetermines a hash value length and then begins calculating hash values. Initially, all hash values ​​start from the first hash word, meaning no bytes are discarded at the beginning of any hash value. Subsequently, if a hash collision occurs, all hash values ​​involved in the collision are adjusted to eliminate the collision. This adjustment can be done by adding an extra hash word to the relevant hash value. A minor issue with this approach is that different hash values ​​will have different lengths. The solution provided in this embodiment is to maintain the overall hash value length by discarding a hash word at the beginning of the hash value simultaneously. In rare cases, this adjustment process may need to be repeated multiple times to resolve collisions. That is, if the first adjustment fails to resolve a collision or introduces a new collision, the adjustment continues until all collisions are eliminated. It should also be noted that while adjusting hash values ​​by adding and deleting an integer number of hash words is simple and efficient, it is not necessary. Adjustments can also be performed at the byte level as needed. For example, if a collision occurs and two different files both have the hash value h1h2h3h4, a hash word will be appended, making the two hash values ​​h1h2h3h4 h5 and h1h2h3h4 h5'. To keep the hash value length unchanged, the initial h1 is discarded, resulting in h2h3h4 h5 and h2h3h4 h5'. If the appended h5 and h5' are different, the recalculated hash values ​​will also be different, and their collision will be eliminated (but they may still collide with other hash values—if this happens, hash words need to be appended to all related hash values); if h5 and h5' are the same, hash words continue to be appended (while discarding the initial hash word to keep the hash value length unchanged) until there are no more collisions.

[0113] Furthermore, the hash algorithm designed in this application embodiment is optimized for Single Instruction Multiple Data (SIMD) intrinsic instructions, which are supported on most CPUs and all GPUs today, and can significantly improve computing speed.

[0114] Reference Figure 5 This application also provides a schematic diagram of a general lightweight hash processing method for calculating the hash value of structured grouped data.

[0115] Depend on Figure 5As can be seen, for structured grouped data, each group of the data is filled in, then all the filled groups are concatenated, and finally the hash value of the entire concatenated data is calculated. This method of filling in first and then concatenating is different from the traditional method of concatenating first and then filling in. The traditional method of concatenating first and then filling in cannot retain the structural information of the data because there is no group boundary information reflected in the final filled data. However, the method of filling in first and then concatenating can achieve the goal of calculating a single hash value for the entire data. When using free suffix filling or free prefix filling, the structural information of the data can be retained. The method of filling in first and then concatenating is more suitable for calculating structured grouped data, such as a pair of key and value, a list of files in a folder, a list of transactions in a ledger, etc.

[0116] Furthermore, by using structured grouped data, the hash algorithm in this embodiment can be used as a keyed hash function, that is, the key and data are treated as two groups of structured data to calculate the hash value.

[0117] In the basic algorithms of the two embodiments described above, each set S i =[a i ,b i ,c i ,d i It consists of four 64-bit words; in a more general design, each set S... i The number of 64-bit words included can be increased as needed. Increasing the number of words improves security but reduces running speed. Although the number of words can be any value not less than 4, it is recommended to use an even number or a power of 2 to take advantage of the inherent advantages of SIMD instructions: the basic algorithm can be easily modified to implement it in each set S. i Using more words, the iteration count of the second loop of the update algorithm is set to per set S. i The number of characters and the number of digits in each character, i.e., 4 + 64 = 68, therefore, the number of iterations should be changed to a general value of q + 64 in the general algorithm, where q is the number of iterations for each set S. i In addition to the number of Chinese characters, each set S needs to be... i The added characters are added to the code in the same way as the original four characters, when each set S i When the number of Chinese characters is not 4, the hexadecimal expression of each hash value must begin with this number followed by a colon. For example, if the hash value b-40b9442506...3d627a given earlier is in each S... i The calculation is based on the number of Chinese characters set to 6. Therefore, its complete form should be 6:b-40b9442506...3d627a.

[0118] Therefore, the hash algorithm of this application can achieve the same result without changing the basic algorithm, simply by adjusting each set S. i =[a i ,b i ,c i ,d i The security of the LHA algorithm is dynamically adjusted by the number of words contained in [, ...]. By dynamically adjusting the security of the hash algorithm, various new and unknown attacks can be effectively dealt with at the lowest cost.

[0119] Furthermore, although the hash algorithm described in this application only applies to 64-bit operations, the basic algorithm can be applied almost unchanged to other bit sizes. For example, on some small, resource-constrained devices that do not support 64-bit operations, 32-bit, 16-bit, or 8-bit operations can be used instead of 64-bit operations.

[0120] Reference Figure 6 Based on the same inventive concept described above, the processor 120 includes: a state transition module 121, an initialization module 122, an update module 123, and a determination module 124;

[0121] State transition module 121 is used to: utilize register state transition functions as transition tools

[0122] The register performs state transitions on the register, which is a linear feedback shift register.

[0123] The initialization module 122 is used to: initialize the internal state of the hash algorithm based on the output of the register in the state transition module and using the initialization algorithm as the initialization tool;

[0124] The update module 123 is used to: use the output of the state transition module and the initialization module, and in combination with the filling data, to update the internal state of the initialized hash algorithm using the update algorithm;

[0125] The determining module 124 is used to: post-process the updated internal state to generate the final hash value. It is understood that a description of the above module can be found in the [reference needed]. Figures 2-5 The method shown will not be elaborated further here.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus and method embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0127] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0128] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a general-purpose lightweight hash processing system 100, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of further restrictions, an element defined by the phrase "including one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0129] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for universal lightweight hashing, comprising: The method is applied to a general lightweight hash processing system, and comprises the following steps, a linear feedback shift register (LFSR) is selected, and a state transition function is used to perform state transition on the linear feedback shift register (LFSR); an output of the linear feedback shift register (LFSR) is used to initialize an internal state of a hash algorithm by using an initialization algorithm; data for which a hash value is to be calculated is input, and the initialized internal state is updated by using an update algorithm, and the data for which the hash value is to be calculated is padded data; a final hash value is generated by using a determination algorithm to post-process the updated internal state; a formula of the initialization algorithm is as follows: a constant: a switching mask m Input: uninitialised internal matrix M = [S0; S1;... ; S n ] and three 64-bit words s, t, x return: M, s, t, and x after initialization The i-th row S i = [a i , b i , c i , d i ] of the internal matrix M is set directly to the four register state values starting from the i x 68-th state, while the switch mask m is used as the first state value of the registers, and the s, t and x are also initialized, the s and t being set to (a0+b0+c0+d0) and x to 0, in the following steps: wherein the hash values are computed by three steps, initialization, update and finalization, the obtained hash values are variable length hash values, and each hash value contains one or more 64-bit unsigned integers, the 64-bit unsigned integers are referred to as 64-bit words or simply words, each word of the hash value is computed independently and irrelevantly except for the initialization phase, S i = [a i , b i , c i , d i ](i = 0, 1, 2,..., n) represents a set containing four words a i , b i , c i and d i ; the update algorithm is as follows: input: data for which a hash value is to be calculated Result: The updated internal matrix M = [S0; S1;... ; S n ] and three 64-bit words s, t, x each 64-bit word of the input data is used to update the internal state by using the update algorithm, and the input data has been padded to a length containing one or more complete 64-bit words, and the specific steps are as follows: wherein is an exclusive OR operation, «« is a left shift operation, and ■+ is a dot addition operation, is a dot exclusive OR operation; a data padding method used by the padded data comprises, a free suffix padding and a free prefix padding; the free prefix padding is as follows, the data padding comprises the following steps: first step: append enough 0s, if the original data contains one or more complete 64-bit words, no 0s need to be appended, second step: append a 64-bit word, the 64-bit word is represented as w1, and w1 is calculated from a data length z and a word s, that is: s←lfsr(s) the data length is a number of bytes z contained by the data. The determination algorithm mixes S0 = [a0, b0, c0, d0] with each of the remaining sets S i = [a i , b i , c i , d i ] and then compresses the result of the mixing to generate a hash word h i , where i = 1, 2,..., n, and is represented as: Input: Internal matrix M = [S0; S1;... ; S n ] Result: Hash value H = hi h2... h n wherein, >>> is a right rotation bit operation.

2. The method of claim 1, wherein: the update algorithm and the determination algorithm are designed in a double-layer structure, wherein an upper layer is the update algorithm, and a lower layer is the determination algorithm.

3. A universal lightweight hashing processing system, further characterized by: comprise, a processor, a network module, and a memory; wherein the processor and the memory communicate through the network module, the processor reads a computer program from the memory and runs to execute the method in any one of claims 1-2.

4. The universal lightweight hashing processing system of claim 3, further characterized by: the processor comprises, a state transition module configured to perform state transition on a register by using a register state transition function as a transition tool, the register being a linear feedback shift register (LFSR); an initialization module configured to initialize an internal state of a hash algorithm by using an initialization algorithm as an initialization tool according to an output of the register in the state transition module; an update module configured to update the initialized internal state of the hash algorithm by using an update algorithm in combination with padded data, the output of the state transition module and the initialization module; a determination module configured to post-process the updated internal state to generate a final hash value.

5. A computer readable storage medium, characterized in that, the storage medium stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the general lightweight hash processing method in any one of claims 1-2.

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