Semiconductor structure preparation method and semiconductor structure

Abstract

The present invention provides a method for preparing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductor preparation. A silicon oxide groove with a target size can be easily realized by designing a silicon substrate and fine process control. Compared with the prior art, the present application does not directly process the silicon oxide structure; instead, the size of the silicon trench is inferred from the size of the silicon oxide trench to achieve precise control of the size of the silicon trench, and then the silicon trench is oxidized to obtain a silicon oxide groove. Under the above-mentioned preparation conditions, a silicon oxide groove with a high aspect ratio, a small groove gap and a well-steep sidewall can be obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a preparation method of a semiconductor structure and a semiconductor structure. Background Art

[0002] Transparent groove or columnar structures with high aspect ratio are widely used in the preparation of MEMS devices, especially micro-optical devices and microfluidic devices.

[0003] The commonly used preparation method at present is to thermally grow or deposit silicon dioxide on a silicon substrate and directly etch the silicon dioxide to form grooves.

[0004] The disadvantage of this method is that it is difficult to prepare a trench structure with a high aspect ratio, a small trench gap, and a well-steep sidewall, which greatly reduces the performance of the device. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing a semiconductor structure and a semiconductor structure to alleviate the technical problem in the prior art that it is difficult to prepare a trench structure with a high aspect ratio, a small trench gap and a sidewall with good steepness.

[0006] An embodiment of the present invention provides a method for preparing a semiconductor structure, comprising the steps of:

[0007] S10. Providing a silicon substrate and a substrate, connecting the bottom surface of the silicon substrate to the substrate;

[0008] S20. According to formulas (1), (2), (3) and (4), the initial size of the silicon trench to be etched is obtained according to the target size of the silicon oxide trench to be prepared and the oxidation deformation rate α;

[0009] The target dimensions include the distance D between the bottom surface of the silicon oxide trench and the upper surface of the substrate, the width S and depth H of the silicon oxide trench, and the width L of the silicon oxide column used to separate two adjacent silicon oxide trenches; the S is less than 2 microns, and the width-to-depth ratio L / H of the silicon oxide column is greater than 5;

[0010] The initial dimensions include the distance d between the bottom surface of the silicon trench and the lower surface of the silicon substrate, the width s of the silicon trench, and the width l and height h of the silicon column;

[0011] l= L / α (1)

[0012] s = (1-1 / α) * L + S (2)

[0013] d = D / α (3)

[0014] h = H - (1-1 / α) * L / 2 + D (4)

[0015] S30. Etching the upper surface of the silicon substrate to form a plurality of silicon trenches having an initial size on the upper surface of the silicon substrate;

[0016] S40. Under the condition of an environment temperature of 900° C. to 1100° C., the silicon trench is oxidized for 1 to 15 hours to obtain a silicon oxide trench with a target size.

[0017] Furthermore, the method includes, before step S30, grinding and thinning the upper surface of the silicon substrate according to the thickness H0 of the silicon substrate and the depth H of the silicon oxide groove, so that the distance D between the bottom surface of the silicon oxide groove and the upper surface of the substrate is in the range of 0-1 micron.

[0018] Furthermore, the grinding and thinning process specifically includes:

[0019] Mechanical grinding.

[0020] Furthermore, the grinding and thinning process specifically includes:

[0021] Chemical Mechanical Polishing.

[0022] Furthermore, the substrate is a quartz substrate.

[0023] Furthermore, in step S10, the bottom surface of the silicon base is connected to the quartz substrate by bonding.

[0024] Furthermore, the method comprises the following steps before the step of connecting the bottom surface of the silicon base to the substrate:

[0025] Step S111: Process the bottom surface of the silicon substrate and the quartz substrate respectively by plasma activation and / or surface chemical mechanical planarization process.

[0026] Furthermore, after step S111, the distance between the bottom surface of the silicon substrate and the quartz substrate after they are combined is in the range of 1 angstrom to 9 angstroms.

[0027] In a second aspect, an embodiment of the present invention provides a semiconductor structure, which is prepared by the above-mentioned method for preparing a semiconductor structure.

[0028] The method for preparing a semiconductor structure provided by an embodiment of the present invention comprises the following steps: S10. providing a silicon substrate and a substrate, and connecting the bottom surface of the silicon substrate to the substrate; S20. obtaining the initial size of the silicon trench to be etched according to the target size of the silicon oxide trench to be prepared and the oxidation deformation rate α according to formulas (1), (2), (3) and (4); wherein the target size includes the distance D between the bottom surface of the silicon oxide trench and the upper surface of the substrate, the width S and depth H of the silicon oxide trench, and the width L of the silicon oxide column used to separate two adjacent silicon oxide trenches; wherein S is less than 2 microns, and the width-to-depth ratio L / H of the silicon oxide column is greater than 5; wherein the initial size includes the distance d between the bottom surface of the silicon trench and the lower surface of the silicon substrate, the width s of the silicon trench, the width l and the height h of the silicon pillar; l = L / α(1); s = (1-1 / α)*L+S(2); d = D / α(3); h = H-(1-1 / α)*L / 2+D(4); S30. Etching the upper surface of the silicon substrate, thereby forming a plurality of silicon trenches with initial sizes on the upper surface of the silicon substrate; S40. Under the condition of an environment with a temperature of 900°C-1100°C, oxidizing the silicon trench for 1-15 hours, thereby obtaining a silicon oxide trench with a target size. The silicon oxide trench with a target size can be easily achieved by designing the silicon substrate and fine process control. Compared with the prior art, the silicon oxide structure is not directly processed in the present application; instead, the size of the silicon trench is inferred from the size of the silicon oxide trench to achieve precise control of the size of the silicon trench, and then the silicon trench is oxidized to obtain a silicon oxide trench. Under the above-mentioned preparation conditions, a silicon oxide trench with a high aspect ratio, a small trench gap and a sidewall with good steepness can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of step S10 in the method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a grinding and thinning process in a method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of step S30 in the method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of step S40 in the method for preparing a semiconductor structure provided in an embodiment of the present invention.

[0034] Icons: 100 - silicon substrate; 110 - silicon oxide trench; 120 - silicon oxide pillar; 130 - silicon trench; 140 - silicon pillar; 200 - quartz substrate. DETAILED DESCRIPTION

[0035] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] like Figure 1 - Figure 4 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present invention comprises the steps of:

[0037] S10. Provide a silicon substrate 100 and a base, and connect the bottom surface of the silicon substrate 100 to the base.

[0038] The key difference between the preparation method adopted in the present application and the prior art is that the object processed in the present application is a silicon substrate 100, not a silicon oxide substrate. In the prior art, some schemes adopt the method of directly etching the silicon oxide substrate 100 to form a groove. The gap of the groove obtained by such means has an obvious inverted trapezoidal structure with a wide top and a narrow bottom, and the sidewall is obviously not vertical. If the groove depth is further increased, the sidewall steepness will inevitably deteriorate further, thereby limiting the acquisition of a groove with a higher aspect ratio.

[0039] However, if the silicon substrate 100 is processed first, the above-mentioned problem will not occur, and a silicon trench 130 with a precise size can be obtained.

[0040] S20. According to formulas (1), (2), (3) and (4), the initial size of the silicon trench 130 to be etched is obtained according to the target size of the silicon oxide trench 110 to be prepared and the oxidation deformation rate α; wherein the target size includes the distance D between the bottom surface of the silicon oxide trench 110 and the upper surface of the substrate, the width S and the depth H of the silicon oxide trench 110, and the width L of the silicon oxide column 120 used to separate two adjacent silicon oxide trenches 110; the S is less than 2 microns, and the width-to-depth ratio L / H of the silicon oxide column 120 is greater than 5; wherein the initial size includes the distance d between the bottom surface of the silicon trench 130 and the lower surface of the silicon substrate 100, the width s of the silicon trench 130, and the width l and height h of the silicon column 140;

[0041] l= L / α (1)

[0042] s = (1-1 / α) * L + S (2)

[0043] d = D / α (3)

[0044] h = H - (1-1 / α) * L / 2 + D (4)

[0045] In the present application, the size (initial size) of the silicon trench 130 is inferred from the size (target size) of the silicon oxide trench 110 to achieve precise control of the size of the silicon trench 130. The main reason for adopting the above scheme instead of directly processing the silicon oxide substrate 100 to obtain the silicon oxide trench 110 is that in the silicon oxide trench 110 of the target size, the S is less than 2 microns, the width-to-depth ratio L / H of the silicon oxide column 120 is greater than 5, the width of the silicon oxide trench 110 to be obtained is narrow, and the width-to-depth ratio is large. The traditional scheme cannot achieve the preparation of this type of silicon oxide trench 110. The target size is a known quantity, and under the condition that the environment is 900℃-1100℃ and the oxidation treatment time is 1-15 hours, the oxidation deformation rate α ranges from 2.0 to 2.6, which is an empirical coefficient obtained by experiment and is a known quantity. Then, the initial size can be obtained by formulas (1), (2), (3) and (4), and the initial size is easy to obtain.

[0046] S30 . Etching the upper surface of the silicon substrate 100 , thereby forming a plurality of silicon trenches 130 having an initial size on the upper surface of the silicon substrate 100 .

[0047] After the initial size is obtained, the silicon substrate 100 can be etched according to the initial size to obtain the silicon trench 130 that meets the initial size requirement. The patterning process of the silicon substrate 100 is a prior art. Specifically, a mask pattern can be formed on the upper surface of the silicon substrate 100 by a photolithography process, and then, the silicon substrate 100 is subjected to plasma dry etching through the mask pattern to form the silicon trench 130.

[0048] S40. Under the condition of an environment temperature of 900° C. to 1100° C., the silicon trench 130 is oxidized for 1 to 15 hours, so as to obtain a silicon oxide trench 110 with a target size.

[0049] After the silicon trench 130 meeting the initial size is prepared, the silicon trench 130 is completely oxidized to form an oxidized silicon trench 110 by means of high temperature oxidation, including completely oxidizing the bottom surface and sidewalls of the silicon trench 130 .

[0050] In summary, the silicon oxide trench 110 with the target size can be easily realized by designing the silicon substrate 100 and fine process control. Compared with the prior art, the silicon oxide structure is not directly processed in the present application; instead, the size of the silicon trench 130 is inferred from the size of the silicon oxide trench 110 to achieve precise control of the size of the silicon trench 130, and then the silicon trench 130 is oxidized to obtain the silicon oxide trench 110. Under the above preparation conditions, the silicon oxide trench 110 with a high aspect ratio, a width-to-depth ratio L / H greater than 5, a small trench gap (S less than 2 microns) and a sidewall with good steepness (steepness less than 0.5°) can be obtained.

[0051] It should be noted that, in practice, the sidewalls of the silicon oxide trench 110 are more or less inclined, and the steepness is a measure of the degree of perpendicularity between the sidewalls of the trench and its bottom surface. The steepness is defined as the angle θ between the sidewalls of the trench and a vertical line. The smaller the angle, the more perpendicular the sidewalls are to the bottom surface of the trench, and vice versa, the sidewalls and the bottom surface form a slope surface.

[0052] The method includes the following steps before step S30: grinding and thinning the upper surface of the silicon substrate 100 according to the initial thickness H0 of the silicon substrate 100 (i.e., the thickness before grinding) and the depth H of the silicon oxide groove 110, so that the distance D between the bottom surface of the silicon oxide groove 110 and the upper surface of the substrate is in the range of 0-1 micron.

[0053] The thickness of the silicon substrate 100 is reduced from H0 to the required thickness h. The key point of this thickness h is that after subsequent etching and high-temperature oxidation, the structure as a whole is transparent, especially the portion between the bottom surface of the silicon oxide groove 110 and the upper surface of the substrate. Since the size of the groove structure is relatively small, ranging from submicron to tens of microns, and is closely adjacent to the quartz substrate 200 below, it is necessary to thin the silicon substrate 100, which is usually several hundred microns thick, to tens of microns thick, and process the groove on the remaining thickness of the silicon substrate 100 (which has been bonded to the quartz substrate 200). Through the above-mentioned size limitation, the transparent property of the silicon oxide groove 110 prepared subsequently can be maintained, thereby improving the performance of the device prepared based on this structure.

[0054] The grinding and thinning process specifically includes mechanical grinding and may also include chemical mechanical polishing. Specifically, the first step of the thinning process may be to grind the upper surface of the silicon substrate 100 by mechanical grinding to reduce the thickness of the silicon substrate 100 to a thickness close to the target thickness h, and then perform chemical mechanical polishing to make the surface smooth and flat, so as to facilitate the implementation of subsequent processes.

[0055] The substrate is a quartz substrate 200 , and in step S10 , the bottom surface of the silicon base 100 is connected to the quartz substrate 200 .

[0056] The quartz substrate 200 plays a supporting role, and at the same time, the quartz substrate 200 maintains the transparency of the overall structure. The bottom surface of the silicon substrate 100 is connected to the quartz substrate 200 by bonding, and the interface of the two substrates first forms a hydrogen bond / van der Waals force, and after high-temperature annealing, a Si-O-Si covalent bond is formed, thereby bonding the two substrates together.

[0057] Before bonding, the silicon substrate 100 and the quartz substrate 200 may be surface treated, including: step S111. The bottom surface of the silicon substrate 100 and the quartz substrate 200 are treated respectively by plasma activation and / or surface chemical mechanical flattening process. The mechanism of plasma activation comes from the multiple effects it produces and significantly changes the surface structure of the material. Charged particles can ionize atoms, destroy the chemical bonds that form the lattice and form dangling bonds; plasma injects ions into the material and produces surface charged particles, forming an electric field, thereby increasing the chemical activity of the material surface and affecting the mobility of ions, so that a strong bond can be formed at the interface of the two materials. Chemical mechanical flattening (CMP) is to flatten the surface of the substrate through the chemical reaction between the material surface and the polishing liquid and the mechanical polishing. After the CMP-treated surfaces of the two substrates, the distance between the bottom surface of the silicon substrate 100 and the quartz substrate 200 is in the range of 1 angstrom to 9 angstroms, close to a distance of several angstroms (0.1 nanometers), making it easier to generate hydrogen bonds / van der Waals forces between the two surfaces.

[0058] The semiconductor structure provided by the embodiment of the present invention is prepared by the above-mentioned method for preparing the semiconductor structure. The semiconductor structure prepared by the above-mentioned method has a semiconductor structure of silicon oxide trench 110 with a high aspect ratio, a width-to-depth ratio L / H greater than 5, a small trench gap (S less than 2 microns) and a sidewall with good steepness (steepness less than 0.5°). This semiconductor structure with a micro-groove with a large aspect ratio and good transparency has a wide range of application prospects in the field of MEMS, especially in the application of micro-optical devices, micro-fluidic devices, etc.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: Includes steps: S10. Providing a silicon substrate (100) and a substrate, and connecting the bottom surface of the silicon substrate (100) to the substrate; S20. According to formulas (1), (2), (3) and (4), the initial size of the silicon trench (130) to be etched is obtained according to the target size of the silicon oxide trench (110) to be prepared and the oxidation deformation rate α; The target dimensions include a distance D between the bottom surface of the silicon oxide trench (110) and the upper surface of the substrate, a width S and a depth H of the silicon oxide trench (110), and a width L of a silicon oxide column (120) for separating two adjacent silicon oxide trenches (110); the S is less than 2 microns, and a width-to-depth ratio L / H of the silicon oxide column (120) is greater than 5; The initial dimensions include the distance d between the bottom surface of the silicon trench (130) and the lower surface of the silicon substrate (100), the width s of the silicon trench (130), and the width l and height h of the silicon column (140); l＝ L / α (1) s = (1-1 / α) * L + S (2) d = D / α (3) h = H - (1-1 / α) * L / 2 + D (4) S30. Etching the upper surface of the silicon substrate (100) to form a plurality of silicon trenches (130) having an initial size on the upper surface of the silicon substrate (100); S40. Under the condition of an ambient temperature of 900° C. to 1100° C., the silicon trench (130) is subjected to an oxidation treatment for 1 to 15 hours to convert the entire silicon substrate (100) into a silicon oxide substrate, thereby obtaining a silicon oxide trench (110) having a target size; The method comprises the following steps, before step S30, of grinding and thinning the upper surface of the silicon substrate (100) according to the thickness H0 of the silicon substrate (100) and the depth H of the silicon oxide groove (110), so that the distance D between the bottom surface of the silicon oxide groove (110) and the upper surface of the substrate is in the range of 0-1 micrometer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The grinding and thinning process specifically includes: Mechanical grinding.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The grinding and thinning process specifically includes: Chemical Mechanical Polishing.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate is a quartz substrate (200).

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: In the step S10, the bottom surface of the silicon base (100) is connected to the quartz substrate (200) by bonding.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The method comprises the following steps before the step of connecting the bottom surface of the silicon base (100) to the substrate: Step S111: using plasma activation and / or surface chemical mechanical flattening processes to process the bottom surface of the silicon base (100) and the quartz substrate (200) respectively.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: After step S111, the distance between the bottom surface of the silicon substrate (100) and the quartz substrate (200) after they are combined is in the range of 1 angstrom to 9 angstroms.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step S30 specifically includes: Step S31. Forming a mask pattern on the upper surface of the silicon substrate (100) by photolithography; Step S32: Plasma dry etching is performed on the silicon substrate (100) through the mask pattern to form a silicon trench (130).

9. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 8.

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