Signal correction circuit, method and computer storage medium

Abstract

The present application relates to the field of signal processing, and discloses a kind of signal correction circuit, method and computer storage medium, the circuit includes sine signal input module, first analog correction module, first analog-digital converter, cosine signal input module, second analog correction module, second analog-digital converter, digital correction module and output interface, sine signal input module, first analog correction module, first analog-digital converter, digital correction module and output interface are sequentially connected, cosine signal input module, second analog correction module, second analog-digital converter, digital correction module and output interface are sequentially connected;First analog correction module and first analog correction module carry out analog correction to signal, and digital correction module carries out digital correction to the signal after analog correction to obtain corrected target sine signal and target cosine signal.The present application improves the signal processing accuracy of off-axis split type encoder.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing, in particular to a signal correction circuit, method and computer storage medium. BACKGROUND

[0002] With the rapid development of off-axis split encoder, the user's requirements for the signal processing of off-axis split encoder are also getting higher and higher. In order to meet the requirements of off-axis split encoder signal processing and improve the accuracy of signal processing, higher requirements are put forward for the signal processing mode of off-axis split encoder.

[0003] The traditional signal processing mode of off-axis split encoder is to directly process the original analog signal collected by the sensing chip through the comparator, and finally output a square wave signal. This signal processing mode of off-axis split encoder has a big defect, that is, there is no signal correction when processing the original analog signal. That is, this signal processing mode of off-axis split encoder will cause low accuracy of signal processing due to no correction of the original analog signal. SUMMARY

[0004] The main purpose of the present application is to provide a signal correction circuit, method and computer storage medium, which aims to solve the technical problem that the existing signal processing mode of off-axis split encoder will cause low accuracy of signal processing due to no correction of the original analog signal.

[0005] To achieve the above purpose, the present application provides a signal correction circuit applied to off-axis split encoder, which comprises a sine signal input module, a first analog correction module, a first analog-to-digital converter, a cosine signal input module, a second analog correction module, a second analog-to-digital converter, a digital correction module and an output interface, wherein,

[0006] The sine signal input module is connected with the first analog correction module, the first analog correction module is connected with the first analog-to-digital converter, the cosine signal input module is connected with the second analog correction module, the second analog correction module is connected with the second analog-to-digital converter, and the digital correction module is connected with the first analog-to-digital converter, the second analog-to-digital converter and the output interface respectively;

[0007] The first analog correction module receives the initial sine signal input by the sine signal input module, the initial sine signal is an analog signal, and the first analog correction module is used to correct the initial sine signal based on correction parameters until the error is less than a preset threshold, to obtain a first sine signal;

[0008] The first analog-to-digital converter module is used to convert the first sine signal into a digital signal to obtain a second sine signal;

[0009] The second analog correction module receives the initial cosine signal input from the cosine signal input module. The initial cosine signal is an analog signal. The second analog correction module is used to correct the initial cosine signal based on correction parameters until the error is less than a preset threshold to obtain the first cosine signal.

[0010] The second analog-to-digital converter module is used to convert the first cosine signal into a digital signal to obtain the second cosine signal;

[0011] The digital correction module is used to digitally correct the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal.

[0012] Optionally, the signal correction circuit includes a calculation module, which is connected to the digital correction module and the output interface respectively, and is used to calculate the angle signal based on the target sine signal and the target cosine signal.

[0013] Optionally, the signal correction circuit further includes a first digital-to-analog converter, which includes a first digital-to-analog input terminal and a first digital-to-analog output terminal. The first digital-to-analog input terminal is connected to the digital correction module, and the first digital-to-analog output terminal is connected to the calculation module, for converting the digital signals in the target sine signal and the target cosine signal into analog signals respectively.

[0014] Optionally, the signal correction circuit further includes a correction parameter determination module, which is connected to the digital correction module, the first analog correction module, and the second analog correction module, respectively.

[0015] The correction parameter determination module initially stores an initial analog correction parameter set and a digital correction parameter set. The initial analog correction parameter set is used to perform analog correction on the initial sine signal and the initial cosine signal, and the digital correction parameter set is used to perform digital correction on the second sine signal and the second cosine signal.

[0016] The correction parameter determination module is further configured to adjust the initial analog correction parameter set based on the initial sine signal and the initial cosine signal after analog correction, and update the initial analog correction parameter set to the adjusted analog correction parameters.

[0017] Optionally, the first analog correction module includes a first programmable operational amplifier (PGA), a first analog adder, and a first filter. The first programmable operational amplifier (PGA) is connected to the sine wave input module and the correction parameter determination module, respectively. The first analog adder is connected to the first programmable operational amplifier (PGA), the first filter, and the correction parameter determination module, respectively. The first filter is connected to the first analog-to-digital converter.

[0018] The first programmable operational amplifier (PGA) includes a first positive input terminal, a first negative input terminal, a first programming control terminal, and a first operational amplifier output terminal. The sine wave signal input module includes a positive sine wave signal interface and a negative sine wave signal interface. The first positive input terminal is connected to the positive sine wave signal interface, the first negative input terminal is connected to the negative sine wave signal interface, the first programming control terminal is connected to the correction parameter determination module, and the first operational amplifier output terminal is connected to the first analog adder.

[0019] The second analog correction module includes a second programmable operational amplifier (PGA), a second analog adder, and a second filter. The second programmable operational amplifier (PGA) is connected to the cosine signal input module and the correction parameter determination module, respectively. The second analog adder is connected to the second programmable operational amplifier (PGA), the second filter, and the correction parameter determination module, respectively. The second filter is connected to the second analog-to-digital converter.

[0020] The second programmable operational amplifier (PGA) includes a second positive input terminal, a second negative input terminal, a second programming control terminal, and a second operational amplifier output terminal. The cosine signal input module includes a sine / cosine signal interface and a negative / cosine signal interface. The second positive input terminal is connected to the sine / cosine signal interface, the second negative input terminal is connected to the negative / cosine signal interface, the second programming control terminal is connected to the correction parameter determination module, and the second operational amplifier output terminal is connected to the second analog adder.

[0021] Optionally, the first analog adder includes a first adder input, a first adder output, and a first bias level control terminal. The first adder input is connected to the output of the first operational amplifier, the first adder output is connected to the first filter, and the first bias level control terminal is connected to the correction parameter determination module.

[0022] The second analog adder includes a second adder input, a second adder output, and a second bias level control terminal. The second adder input is connected to the output of the second operational amplifier, the second adder output is connected to the second filter, and the second bias level control terminal is connected to the correction parameter determination module.

[0023] Furthermore, to achieve the above objectives, the present invention also provides a signal correction method, which is applied to the signal correction circuit, and the steps of the signal correction method include:

[0024] Obtain the initial sine signal;

[0025] The initial sinusoidal signal is subjected to analog correction to obtain the first sinusoidal signal;

[0026] The first sine signal is converted into a digital signal to obtain the second sine signal;

[0027] Obtain the initial cosine signal;

[0028] The initial cosine signal is subjected to analog correction to obtain the first cosine signal;

[0029] The first cosine signal is converted into a digital signal to obtain the second cosine signal;

[0030] The second sine signal and the second cosine signal are digitally corrected to obtain the corrected target sine signal and target cosine signal.

[0031] Optionally, the initial sinusoidal signal is subjected to analog correction to obtain a first sinusoidal signal, including:

[0032] Obtain an initial simulation correction parameter set; wherein, the initial simulation correction parameter set contains multiple initial simulation correction parameters, including initial sine amplification factor, initial sine bias voltage, initial cosine amplification factor, initial cosine bias voltage, and initial phase difference parameter;

[0033] The initial sinusoidal signal is simulated and corrected using the initial sinusoidal amplification factor and the initial sinusoidal bias voltage to obtain the corrected initial sinusoidal signal.

[0034] When the sinusoidal error between the corrected initial sinusoidal signal and the ideal sinusoidal signal is greater than or equal to a preset sinusoidal threshold, the initial sinusoidal amplification factor and the initial sinusoidal bias voltage are adjusted to obtain a first set of analog correction parameters.

[0035] The first set of simulated correction parameters is used to simulate and correct the initial sinusoidal signal after correction until the sinusoidal error is less than the preset sinusoidal threshold, thereby obtaining the sinusoidal signal to be corrected in phase, and determining the first sinusoidal signal corresponding to the sinusoidal signal to be corrected in phase.

[0036] Correspondingly, the initial sine signal is subjected to analog correction to obtain the first cosine signal, including:

[0037] The initial cosine signal is simulated and corrected using the initial cosine amplification factor and the initial cosine bias voltage to obtain the corrected initial cosine signal.

[0038] If the cosine error between the corrected initial cosine signal and the ideal cosine signal is greater than or equal to a preset cosine threshold, the initial cosine amplification factor and the initial cosine bias voltage are adjusted to obtain a second set of analog correction parameters.

[0039] The initial cosine signal after correction is simulated and corrected using the second set of simulated correction parameters until the cosine error is less than the preset cosine threshold, thereby obtaining the phase-to-correct cosine signal and determining the first cosine signal corresponding to the phase-to-correct cosine signal.

[0040] Optionally, the step of determining the first sinusoidal signal corresponding to the sinusoidal signal whose phase needs to be corrected includes:

[0041] The initial sinusoidal phase difference parameter is determined based on the initial phase difference parameter, the sinusoidal signal to be corrected for phase, and the cosine signal to be corrected for phase.

[0042] The initial sinusoidal phase difference parameter is used to simulate and correct the sinusoidal signal whose phase needs to be corrected, to obtain a third sinusoidal signal;

[0043] When the phase difference between the third sinusoidal signal and the cosine signal to be corrected is not equal to the preset phase difference value, the initial sinusoidal phase difference parameter is adjusted to obtain the third analog correction parameter set.

[0044] The third sinusoidal signal is simulated and corrected using the third set of analog correction parameters until the phase difference equals the preset phase difference value, thus obtaining the first sinusoidal signal.

[0045] Optionally, after the step of adjusting the initial simulation correction parameter set to obtain the first simulation correction parameter set, the method includes:

[0046] Update the initial simulation correction parameter set to the first simulation correction parameter set;

[0047] The first set of simulated correction parameters is stored in the correction parameter determination module.

[0048] Optionally, after the step of digitally correcting the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal, the method further includes:

[0049] The sinusoidal angle information is calculated based on the target sinusoidal signal;

[0050] Cosine angle information calculated based on the target cosine signal;

[0051] Output the sine angle information and the cosine angle information.

[0052] In addition, to achieve the above objectives, the present invention also provides a computer storage medium storing a signal correction program, which, when executed by a processor, implements the steps of the signal correction method described above.

[0053] The signal correction circuit of this invention includes a sine signal input module, a first analog correction module, a first analog-to-digital converter (ADC), a cosine signal input module, a second analog correction module, a second ADC, a digital correction module, and an output interface. The sine signal input module is connected to the first analog correction module, the first analog correction module is connected to the first ADC, the cosine signal input module is connected to the second analog correction module, the second analog correction module is connected to the second ADC, and the digital correction module is connected to the first ADC, the second ADC, and the output interface. The first analog correction module receives an initial sine signal input from the sine signal input module, where the initial sine signal is an analog signal. The first analog-to-digital converter (ADC) is used to correct the initial sine signal based on correction parameters until the error is less than a preset threshold, thus obtaining a first sine signal. The second analog-to-digital converter (ADC) is used to convert the first sine signal into a digital signal, thus obtaining a second sine signal. The second analog correction module receives the initial cosine signal input from the cosine signal input module. The initial cosine signal is an analog signal. The second analog correction module is used to correct the initial cosine signal based on correction parameters until the error is less than a preset threshold, thus obtaining a first cosine signal. The second ADC is used to convert the first cosine signal into a digital signal, thus obtaining a second cosine signal. The digital correction module is used to perform digital correction on the second sine signal and the second cosine signal, thus obtaining a corrected target sine signal and a target cosine signal. The first sine / cosine signal is obtained by sequentially correcting the initial input sine / cosine signal through the first / second analog correction module and judging by the preset threshold. The target sine / cosine signal is obtained by digitally correcting the first sine / cosine signal through the first / second digital correction module. This avoids the phenomenon that the signal is not corrected when processing the original analog signal in the existing solution. This signal correction circuit improves the signal processing accuracy of the off-axis split encoder by correcting the input signal through the first / second analog correction module and the first / second digital correction module. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of one embodiment of the signal correction circuit of the present invention;

[0056] Figure 2 This is a schematic diagram of the actual structure of the signal correction circuit of the present invention;

[0057] Figure 3 This is a schematic diagram of the internal structure of the first programmable operational amplifier (PGA) and the second programmable operational amplifier (PGA) in the signal correction circuit of the present invention;

[0058] Figure 4 This is a schematic diagram of the internal structure of the sine signal input module and the cosine signal input module in the signal correction circuit of the present invention;

[0059] Figure 5 This is a schematic diagram of the internal structure of the first analog adder and the second analog adder in the signal correction circuit of the present invention;

[0060] Figure 6 This is a schematic diagram of the internal structure of the first digital-to-analog converter in the signal correction circuit of the present invention;

[0061] Figure 7 This is a physical diagram of the gears and read head of the off-axis split encoder of the present invention;

[0062] Figure 8 This is a block diagram illustrating the implementation of the signal correction circuit of the present invention;

[0063] Figure 9 This is a schematic diagram of the signal correction device structure in the hardware operating environment involved in the embodiments of the present invention;

[0064] Figure 10 This is a flowchart illustrating an embodiment of the signal correction method of the present invention;

[0065] Figure 11 This is a schematic diagram of the technical solution of the signal correction method of the present invention.

[0066] Explanation of icon numbers:

[0067] Reference numerals Names Reference numerals Names 10 Sine signal input module 20 First analog correction module 21 First programmable operational amplifier PGA 22 First analog adder 23 First filter 30 First analog-to-digital converter 40 Cosine signal input module 50 Second analog correction module 51 Second programmable operational amplifier PGA 52 Second analog adder 53 Second filter 60 Second analog-to-digital converter 70 Digital correction module 80 Output interface 90 Solving module 100 First digital-to-analog converter 00 Correction parameter determination module 211 First positive input end 212 First negative input end 213 First operational amplifier output end 214 First programming control end 511 Second positive input end 512 Second negative input end 513 Second operational amplifier output end 514 Second programming control end 221 First addition input end 222 First addition output end 223 First bias level control end 521 Second addition input end 522 Second addition output end 523 Second bias level control end 10A First digital-to-analog input end 10B First digital-to-analog output end 11 Positive sine signal interface 12 Negative sine signal interface 41 Positive cosine signal interface 42 Negative cosine signal interface

[0068] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0070] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0071] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0072] This invention proposes a signal correction circuit.

[0073] In one embodiment of the present invention, such as Figure 1 As shown, Figure 1 This is a schematic diagram of one embodiment of a signal correction circuit. The signal correction circuit includes a sine signal input module 10, a first analog correction module 20, a first analog-to-digital converter 30, a cosine signal input module 40, a second analog correction module 50, a second analog-to-digital converter 60, a digital correction module 70, and an output interface 80.

[0074] The sine signal input module 10 is connected to the first analog correction module 20, the first analog correction module 20 is connected to the first analog-to-digital converter 30, the cosine signal input module 40 is connected to the second analog correction module 50, the second analog correction module 50 is connected to the second analog-to-digital converter 60, and the digital correction module 70 is connected to the first analog-to-digital converter 30, the second analog-to-digital converter 60, and the output interface 80 respectively.

[0075] The first analog correction module 20 receives an initial sine signal input from the sine signal input module 10. The initial sine signal is an analog signal. The first analog correction module 20 is used to correct the initial sine signal based on correction parameters until the error is less than a preset threshold to obtain a first sine signal.

[0076] The first analog-to-digital converter 30 is used to convert the first sine signal into a digital signal to obtain a second sine signal;

[0077] The second analog correction module 50 receives the initial cosine signal input from the cosine signal input module 40. The initial cosine signal is an analog signal. The second analog correction module 50 is used to correct the initial cosine signal based on the correction parameters until the error is less than a preset threshold to obtain the first cosine signal.

[0078] The second analog-to-digital converter module 60 is used to convert the first cosine signal into a digital signal to obtain a second cosine signal;

[0079] The digital correction module 70 is used to digitally correct the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal.

[0080] In this embodiment, an off-axis split encoder refers to an encoder in which the readhead assembly and the grating assembly are separate. (Refer to...) Figure 7 , Figure 7 The images show the gear and reader head of an off-axis split encoder, with top and front views respectively. The gear is on the left and the reader head is on the right. The rotation center of the gear is coaxial with the rotation center of the motor (the center of the great circle). The encoder is mounted on the side of the gear, not on the same rotation center. Furthermore, the assembly of the gear and encoder is a two-stage process (installing the gear and motor first, then the reader head). This inevitably leads to a certain deviation in the relative positions of the encoder and gear. The key to the encoder implementation is how to correct the differences in the original signal caused by the installation deviation, ultimately outputting a stable and highly accurate signal. This solution can adaptively adjust various correction parameters (amplification factor, bias level, etc.) based on the installation conditions between the reader head and the gear. These installation conditions can be determined by comparing the measured signal with the ideal signal. This adaptive adjustment method allows for greater freedom in the installation gap between the reader head and the gear. In existing technologies with fixed correction parameters, the installation gap between the reader head and the gear is generally limited to 0.1mm-0.3mm. This solution allows for a wider range of settings from 0.1mm to 1mm, providing greater flexibility in the installation position.

[0081] In this embodiment, the original signal (here referring to the input signals of the sine signal input module 10 and the cosine signal input module 40, specifically the sine signal and the cosine signal) can be corrected through analog and digital correction to achieve the signal correction process, which can be referred to... Figure 2 First, the signal passes through two programmable operational amplifiers (PGAs) to remove common-mode interference (only present in differential quadrature signals) and correct for unequal signal amplitudes. Then, after passing through an analog adder, the analog bias of the corrected signal is adjusted. Next, after passing through a filter, the higher harmonics of the corrected signal are filtered, and finally, the phase difference between the two signals is corrected. The corrected analog signal is then converted into a digital signal by an analog-to-digital converter (ADC) for processing. After digital correction, the digital signal is output as an angle value. In other words, the sensor chip sends a set of theoretically quadrature sensing signals (sinθ, cosθ) with a 90° phase difference to the cosine signal input module 40 and the sine signal input module 10 for signal input. The sensor chip refers to the acquisition device inside the off-axis split encoder. However, in reality, due to installation, interference, and other reasons, the obtained sensing signal contains various imperfect components. The actual sinθ signal can be used... The representation and actual cosθ are available It means that u a0 and u b0 This indicates that the DC bias of the signal is unequal, u a1 and u b1 This indicates that the signal amplitudes are unequal. This indicates that the signals are not orthogonal (the phase difference between the signals is not 90°). and This indicates the presence of higher harmonics in the signal, such as the second and third harmonics. The correction signal amplitude refers to the correction value. a1 and u b1 The unequal bias of the correction signal refers to the correction of u a0 and u b0 Phase difference correction refers to making the phase difference between two signals 90°. The filter mainly refers to filtering out unwanted high-order harmonics. The filter coefficients here are mainly based on the maximum gear speed. This avoids the problems of low encoder accuracy and difficulty in eliminating errors caused by installation differences, as well as the difficulty in ensuring consistent output accuracy. This solution corrects the amplitude, bias, and harmonics of the output signal and can use negative feedback for processing, thereby improving the signal processing accuracy of off-axis split encoders.

[0082] In one embodiment, reference is made to... Figure 2 and Figure 6 As shown, Figure 2 This is a schematic diagram of the actual structure of a signal correction circuit. Figure 6This is an internal schematic diagram of the first digital-to-analog converter in the signal correction circuit. The signal correction circuit includes a calculation module 90, which is connected to the digital correction module 70 and the output interface 80, respectively, and is used to calculate the angle signal based on the target sine signal and the target cosine signal.

[0083] Specifically, the signal correction circuit further includes a first digital-to-analog converter 100, which includes a first digital-to-analog input terminal 10A and a first digital-to-analog output terminal 10B. The first digital-to-analog input terminal 10A is connected to the digital correction module 70, and the first digital-to-analog output terminal 10B is connected to the calculation module 90, for converting the digital signals in the target sine signal and the target cosine signal into analog signals respectively.

[0084] Specifically, the signal correction circuit further includes a correction parameter determination module 00, which is connected to the digital correction module 70, the first analog correction module 20, and the second analog correction module 50, respectively.

[0085] The correction parameter determination module 00 initially stores an initial analog correction parameter set and a digital correction parameter set. The initial analog correction parameter set performs analog correction on the initial sine signal and the initial cosine signal, and the digital correction parameter set is used to perform digital correction on the second sine signal and the second cosine signal.

[0086] The correction parameter determination module is further configured to adjust the initial analog correction parameter set based on the initial sine signal and the initial cosine signal after analog correction, and update the initial analog correction parameter set to the adjusted analog correction parameters.

[0087] In this embodiment, after the analog correction signal is obtained through processing, the processor of the entire circuit evaluates the amplitude and bias of the signal. If the amplitude and bias of the signal do not meet the threshold that the processor can process, the processor will re-control the programmable operational amplifier (PGA) and adder to correct the amplitude and bias of the analog signal respectively until the error is less than the preset threshold. The correction parameters refer to the sine parameters (amplification factor and bias level), cosine parameters (amplification factor and bias level), and phase correction parameters. The processor here refers to a microprocessor (i.e., the correction parameter determination module 00 mentioned later) that can be installed or wired after the second analog-to-digital converter 60 and the first analog-to-digital converter 30. It can evaluate the signal amplitude and bias against preset thresholds and feed back new instructions to the programmable operational amplifier (PGA) and adder based on the evaluation results. This enables the automation of the entire signal processing process, thus avoiding the phenomenon of no correction in the implementation process when only a comparator is used. After the sine and cosine signals meet the amplitude and bias requirements after analog correction, the two signals that meet the requirements will be phase corrected. The specific phase correction method is described in the method content of this scheme. Finally, due to the low accuracy of the programmable operational amplifier and adder, even if the amplitude and bias of the signal meet the requirement of being less than the threshold after analog correction, there will still be a certain deviation. The main reason for this is the achievable resolution limit of analog signals. This resolution limit refers to the numerical values; that is, the amplification factor and bias voltage cannot be taken to precise values. For example, the smallest unit of amplification factor and bias voltage is 1, but a value of 0.5 will result in either an upward or downward adjustment. Therefore, digital signal processing methods are used to fine-tune the signal's gain, bias, phase, and higher harmonics. This fine-tuning refers to the fine-tuning method in digital signal processing (the correction parameter determination module receives the signal and performs analog correction, and sends the signal to perform digital correction, i.e., the double arrows in the diagram). This will not be explained further here. Digital correction also involves a feedback process similar to analog correction. The digital correction parameter set in the correction parameter determination module 00 is continuously iterated and updated to ensure that the digital correction meets the user-defined or signal-specific requirements. The way the digital correction parameter set is updated is similar to the way the initial analog correction parameter set is updated. After correction and interference removal, the signal is a pair of approximately ideal orthogonal signals (sinθ, cosθ). Using the trigonometric function method of the solution module 90, this signal can be solved into an angle signal. The main reason for this is that the ultimate goal of the entire circuit is to measure the position and speed of the motor, thus requiring the calculation of angle signals. The calculation method for these angle signals is similar to existing methods. Furthermore, based on the specific application requirements, the processor can calculate and convert the angle signals into usable signals. Finally, this signal is output through the interface circuit.The output signal is a square wave digital signal, but it can also be an analog voltage signal, an analog current signal, a serial protocol digital signal, or other signals. Here, the square wave digital signal refers to the signal directly output by the calculation module 90 after processing by other devices. The serial protocol digital signal refers to the signal input to the calculation module 90 using the corresponding communication protocol (which can be set in the calculation module 90 or elsewhere). The analog voltage signal and analog current signal refer to the output after processing by the first digital-to-analog converter 100 in the calculation module 90. This avoids the limitations of existing technologies that process the original signal using proprietary foreign chips and directly output a square wave signal, which cannot meet the needs of other signal outputs. The internal settings of the calculation module 90 can improve the diversity of output signals for the off-axis split encoder, thereby enhancing its functionality.

[0088] In one embodiment, reference is made to... Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram of the internal structure of the first programmable operational amplifier (PGA) and the second programmable operational amplifier (PGA) in the signal correction circuit. Figure 4 This is a schematic diagram of the internal structure of the sine signal input module and the cosine signal input module in the signal correction circuit. The first analog correction module 20 includes a first programmable operational amplifier (PGA) 21, a first analog adder 22, and a first filter 23. The first programmable operational amplifier (PGA) 21 is connected to the sine signal input module 10 and the correction parameter determination module 00, respectively. The first analog adder 22 is connected to the first programmable operational amplifier (PGA) 21, the first filter 23, and the correction parameter determination module 00, respectively. The first filter 23 is connected to the first analog-to-digital converter 30.

[0089] The first programmable operational amplifier (PGA) 21 includes a first positive input terminal 211, a first negative input terminal 212, a first programming control terminal 214, and a first operational amplifier output terminal 213. The sine wave signal input module 10 includes a sine wave signal interface 11 and a negative sine wave signal interface 12. The first positive input terminal 211 is connected to the sine wave signal interface 11, the first negative input terminal 212 is connected to the negative sine wave signal interface 12, the first programming control terminal 214 is connected to the correction parameter determination module 00, and the first operational amplifier output terminal 213 is connected to the first analog adder 22.

[0090] The second analog correction module 50 includes a second programmable operational amplifier (PGA) 51, a second analog adder 52, and a second filter 53. The second programmable operational amplifier (PGA) 51 is connected to the cosine signal input module 40 and the correction parameter determination module 00, respectively. The second analog adder 52 is connected to the second programmable operational amplifier (PGA) 51, the second filter 53, and the correction parameter determination module 00, respectively. The second filter 53 is connected to the second analog-to-digital converter 60.

[0091] The second programmable operational amplifier (PGA) 51 includes a second positive input terminal 511, a second negative input terminal 512, a second programming control terminal 514, and a second operational amplifier output terminal 513. The cosine signal input module 40 includes a sine / cosine signal interface 41 and a negative / cosine signal interface 42. The second positive input terminal 511 is connected to the sine / cosine signal interface 41, the second negative input terminal 512 is connected to the negative / cosine signal interface 42, the second programming control terminal 514 is connected to the correction parameter determination module 00, and the second operational amplifier output terminal 513 is connected to the second analog adder 52.

[0092] In this embodiment, the input orthogonal sensing signal can be a differential orthogonal signal or a single-ended orthogonal signal. The differential orthogonal signals sinθ and cosθ contain both positive and negative signals. Here, we will use the positive and negative sinθ signals for explanation (the processing flow of the positive and negative cosθ signals corresponds to this). The positive sinθ signal is the output of the sine wave signal interface 11, and the negative sinθ signal (represented as -sinθ) is the output of the negative sine wave signal interface 12. After passing through the first programmable operational amplifier PGA 21, we get sinθ - (-sinθ) = 2sinθ. Similarly, the positive and negative cosθ signals, after passing through the first programmable operational amplifier PGA 51, get 2cosθ. At the same time, the differential orthogonal signal removes common-mode interference from the signal and changes... Make the signals orthogonal. A single-ended orthogonal signal refers to the case where only positive sinθ and positive cosθ signals exist. The processing methods for both are the same, and this embodiment will use single-ended orthogonal signals for explanation. The orthogonal signals acquired and processed can be one set or multiple sets. When multiple sets of signals are acquired and processed, the accuracy of the final output signal can be guaranteed. This involves a probability issue: if one set is incorrect, the entire result will be incorrect; if one set is incorrect, the impact on the overall result is minimal. This can improve the accuracy of the signal processing of the entire off-axis split encoder. The main function of the programmable operational amplifier (PGA) here is to convert the amplitude u in the sinusoidal signal... a1 Processed to the amplitude u in the cosine signal b1To achieve this, the amplification factor of the programmable op-amp (PGA) is changed by altering the input amplification factor at the programming control terminal. By adjusting the amplification factor to make them nearly equal, amplitude correction of the signal in the off-axis split encoder can be achieved, ensuring the accuracy of the final output signal. It's worth noting that if there are no specific requirements, the PGA can be replaced with a differential proportional amplifier to save costs.

[0093] In one embodiment, reference is made to... Figure 5 As shown, Figure 5 This is a schematic diagram of the internal structure of the first analog adder and the second analog adder in the signal correction circuit. The first analog adder 22 includes a first adder input terminal 221, a first adder output terminal 222, and a first bias level control terminal 223. The first adder input terminal 221 is connected to the first operational amplifier output terminal 213, the first adder output terminal 222 is connected to the first filter 23, and the first bias level control terminal 223 is connected to the correction parameter determination module 00.

[0094] The second analog adder 52 includes a second adder input terminal 521, a second adder output terminal 522, and a second bias level control terminal 523. The second adder input terminal 521 is connected to the output terminal 513 of the second operational amplifier, the second adder output terminal 522 is connected to the second filter 53, and the second bias level control terminal 523 is connected to the correction parameter determination module 00.

[0095] In this embodiment, the function of the two analog adders is to control the two signals after amplitude correction to remove the DC bias contained in the signals, that is, to remove the u from the two signals. a0 and u b0 In addition, the bias level of the analog adder can be changed by altering the bias level of the bias level control terminal. By changing the bias level to make the two approximately equal to 0, the bias correction of the signal in the off-axis split encoder can be achieved, thus ensuring the accuracy of the final output signal.

[0096] Furthermore, refer to Figure 9 , Figure 9 This is a schematic diagram of the signal correction device structure in the hardware operating environment involved in the embodiments of the present invention.

[0097] like Figure 9As shown, the signal correction device may include: a processor 0003, such as a central processing unit (CPU), a communication bus 0001, an acquisition interface 0002, a processing interface 0004, and a memory 0005. The communication bus 0001 is used to establish communication between these components. The acquisition interface 0002 may include an information acquisition device or acquisition unit, such as a computer; optionally, the acquisition interface 0002 may also include a standard wired interface or a wireless interface. The processing interface 0004 may optionally include a standard wired interface or a wireless interface. The memory 0005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk storage device. Optionally, the memory 0005 may also be a storage device independent of the aforementioned processor 0003.

[0098] Those skilled in the art will understand that Figure 9 The structure shown does not constitute a limitation on the signal correction device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0099] like Figure 9 As shown, the memory 0005, which serves as a computer storage medium, may include an operating system, an acquisition interface module, a processing interface module, and a signal correction program.

[0100] exist Figure 9 In the signal correction device shown, the communication bus 0001 is mainly used to realize the connection and communication between components; the acquisition interface 0002 is mainly used to connect to the backend server and communicate data with the backend server; the processing interface 0004 is mainly used to connect to the deployment end (user end) and communicate data with the deployment end; the processor 0003 and the memory 0005 in the signal correction device of the present invention can be set in the signal correction device. The signal correction device calls the signal correction program stored in the memory 0005 through the processor 0003 and executes the signal correction method provided in the embodiment of the present invention.

[0101] Furthermore, refer to, for example Figure 10 As shown, a flowchart illustrating a first embodiment of the signal correction method of the present invention is presented based on an embodiment of the above-described signal correction circuit. The steps of the signal correction method include:

[0102] Step S10: Obtain the initial sine wave signal;

[0103] Step S20: Perform analog correction on the initial sinusoidal signal to obtain a first sinusoidal signal;

[0104] Step S30: Convert the first sine signal into a digital signal to obtain a second sine signal;

[0105] Step S40: Obtain the initial cosine signal;

[0106] Step S50: Perform analog correction on the initial cosine signal to obtain the first cosine signal;

[0107] Step S60: Convert the first cosine signal into a digital signal to obtain the second cosine signal;

[0108] Step S70: Perform digital correction on the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal.

[0109] In this embodiment, when a raw signal is input, an internal judgment is performed, primarily detecting the signal type of the raw signal. Specifically, it checks whether the signal type matches a sine / cosine signal, a negative cosine signal, a sine / sine signal, or a negative cosine signal. Once the signal type is determined, the signal is sent to the sine / sine and negative cosine signal interfaces in the sine signal input module, or the sine / cosine and negative cosine signal interfaces in the cosine signal input module, according to the signal type. Steps S10 and S40, S20 and S50, and S30 and S60 are performed synchronously and correspondingly. (Refer to...) Figure 2The process involves correction via a first / second analog correction module. Specifically, the first / second programmable operational amplifier (PGA) performs amplitude correction on the original sine / cosine signal to obtain an amplitude sine / cosine signal. A first / second analog adder then performs bias correction on the amplitude sine / cosine signal to obtain a bias sine / cosine signal. A first / second filter then filters the bias sine / cosine signal to obtain a filtered sine / cosine signal. Finally, a correction parameter determination module performs analog correction on the filtered sine / cosine signal to obtain a first sine / cosine signal. This refers to phase correction of the two signals after the filtered sine / cosine signal meets the requirements. The first sine / cosine signal, which meets the requirements (sine / cosine error is less than the preset sine / cosine threshold), refers to the first quasi-sine / cosine signal mentioned later. The first sine / cosine signal is converted by the first / second analog-to-digital converter to obtain the second sine / cosine signal. The main process is that the initial sine / cosine signal is processed by the first / second programmable operational amplifier (PGA), the first / second analog adder, the first / second filter, and the first / second analog-to-digital converter to obtain the second sine / cosine signal. Finally, the second sine / cosine signal is digitally corrected to obtain the target sine signal and the target cosine signal. Here, the initial sine / cosine signal refers to the first sine / cosine signal acquired; the amplitude sine / cosine signal refers to the initial sine / cosine signal after amplitude correction; the bias sine / cosine signal refers to the amplitude sine / cosine signal after bias correction; the filtered sine / cosine signal refers to the bias sine / cosine signal after filtering; the first sine / cosine signal refers to the bias sine / cosine signal that meets the requirements after processing by the correction parameter determination module; and the second sine / cosine signal refers to the first sine / cosine signal after analog-to-digital conversion. Correcting the signal through amplitude, bias, phase, and filtering ensures the accuracy of the signal output. After digitally correcting the second sine and second cosine signals to obtain the corrected target sine and target cosine signals, the process also includes:

[0110] Step S71: Based on the sinusoidal angle information calculated from the target sinusoidal signal;

[0111] Step S72: Based on the cosine angle information obtained by solving the target cosine signal;

[0112] Step S73: Output the sine angle information and the cosine angle information.

[0113] In this embodiment, after obtaining the target sine and cosine signals, the calculation module in the signal correction circuit calculates the two signals to obtain their corresponding angle signals, thereby achieving the effect of the encoder measuring angle and speed. Here, the sine angle information refers to the signal obtained by the calculation module in the correction circuit from the target sine signal, and the cosine angle information refers to the signal obtained by the calculation module in the correction circuit from the target cosine signal.

[0114] Furthermore, based on the first embodiment of the signal correction method of the present invention, a second embodiment of the signal correction method of the present invention is proposed, the signal correction method comprising:

[0115] Furthermore, the initial sinusoidal signal is subjected to analog correction to obtain a first sinusoidal signal, including:

[0116] Step a, obtain the initial simulation correction parameter set; wherein, the initial simulation correction parameter set contains multiple initial simulation correction parameters, including initial sine amplification factor, initial sine bias voltage, initial cosine amplification factor, initial cosine bias voltage, and initial phase difference parameter;

[0117] Step b: The initial sinusoidal signal is simulated and corrected using the initial sinusoidal amplification factor and the initial sinusoidal bias voltage to obtain the corrected initial sinusoidal signal;

[0118] Step c: If the sinusoidal error between the corrected initial sinusoidal signal and the ideal sinusoidal signal is greater than or equal to a preset sinusoidal threshold, the initial sinusoidal amplification factor and the initial sinusoidal bias voltage are adjusted to obtain a first set of analog correction parameters.

[0119] Step d: Use the first set of simulated correction parameters to simulate and correct the initial sinusoidal signal after correction until the sinusoidal error is less than the preset sinusoidal threshold to obtain the phase-to-correct sinusoidal signal and determine the first sinusoidal signal corresponding to the phase-to-correct sinusoidal signal.

[0120] Step e: The initial cosine signal is simulated and corrected using the initial cosine amplification factor and the initial cosine bias voltage to obtain the corrected initial cosine signal;

[0121] Step f: If the cosine error between the corrected initial cosine signal and the ideal cosine signal is greater than or equal to a preset cosine threshold, the initial cosine amplification factor and the initial cosine bias voltage are adjusted to obtain a second set of analog correction parameters.

[0122] Step g: Use the second set of simulated correction parameters to simulate and correct the initial cosine signal after correction until the cosine error is less than the preset cosine threshold to obtain the phase cosine signal to be corrected, and determine the first cosine signal corresponding to the phase cosine signal to be corrected.

[0123] In this embodiment, the initial sine and initial cosine signals are processed by obtaining an initial analog correction parameter set. The initial analog correction parameter set includes at least the initial sine / cosine amplification factor, the initial sine / cosine bias voltage, and the initial sine / cosine phase difference parameter. "Initial" refers to the most original parameters. The first and second adjusted bias levels / amplification factors mentioned later are parameters adjusted based on the initial or most recent parameters. This mainly refers to the correction parameter determination module sending the initial sine wave amplification factor from the initial analog correction parameter set to the first programmable operational amplifier (PGA), and the initial sine wave bias level from the initial analog correction parameter set to the first analog adder. The first PGA and the first analog adder correct the amplitude and bias of the input initial sine wave signal, and a first filter removes high-order harmonics from the initial sine wave signal after two corrections, resulting in a corrected initial sine wave signal. Finally, it checks whether the sine wave error between the corrected initial sine wave signal and the ideal sine wave signal is less than a preset sine wave threshold. The main steps are: determining the sine wave amplitude and sine wave bias corresponding to the corrected sine wave signal acquired by the correction parameter determination module in the signal correction circuit (the correction parameter determination module is connected to the digital correction module; if they do not match, further processing continues; if they match, the channel is opened to allow the signal to flow to the phase processing module); and simultaneously detecting whether the sine wave amplitude is less than a preset sine wave amplitude and whether the sine wave bias is less than a preset sine wave bias. Here, the sine wave amplitude refers to the value of u in the signal after all corrections. a1 The value of the sinusoidal signal bias refers to the value of u in the signal after full correction. a0The preset sine wave amplitude and preset sine wave bias are user-defined values ​​that can be set according to the user or actual conditions. Here, they refer to the amplitude error and bias error between the corrected initial sine wave signal and the ideal sine wave signal. When both sine wave errors are less than the preset sine wave threshold, the corrected initial sine wave signal meets the requirements. The preset sine wave threshold can be a value corresponding to both the amplitude error and the bias error, or it can be a single value corresponding to both. When the requirements are met (both sine wave errors are less than the preset sine wave threshold), the corrected initial sine wave signal with the sine wave error less than the preset sine wave threshold is used as the phase-to-correction sine wave signal. In other words, the signal that has undergone analog correction and meets the requirement that all sine wave errors are less than the preset sine wave threshold is used as the phase-to-correction sine wave signal. Conversely, if the requirements are not met (sine errors are all not less than the preset sine threshold or there is a sine error not less than the preset sine threshold), adjustments will be made (adjusting the sine amplification factor and the initial sine bias voltage) to obtain the first analog correction parameter set. After performing the previous correction steps based on the first analog correction parameter set, the judgment will be repeated until the corrected initial sine signal meets the requirements (sine errors are all less than the preset sine threshold). The corrected signal will then be used as the phase sine signal to be corrected. Alternatively, adjustments can be made to obtain the first / second initial analog correction parameter set, and the initial sine / cosine signal will be corrected based on the first / second initial analog correction parameter set, and the judgment will be repeated until the corrected initial sine signal meets the requirements (sine errors are all less than the preset sine threshold). The corrected signal will then be used as the phase sine / cosine signal to be corrected. Here, the first / second analog correction parameter set is updated based on the corrected initial sine / cosine signal. For example, a new concept is introduced here: when the sinusoidal error is 5, the ideal sinusoidal signal requires 0. The maximum preset sinusoidal threshold here is 5. The preset sinusoidal signal amplitude refers to the maximum value of the preset sinusoidal threshold. When the sinusoidal signal amplitude is less than the preset sinusoidal signal amplitude and the sinusoidal signal bias is less than the preset sinusoidal signal bias, the first sinusoidal signal will be determined based on the phase-to-correct sinusoidal signal and the first cosine signal will be determined based on the phase-to-correct cosine signal (the first sine / cosine signal is obtained after phase correction of the two signals). Then, the corrected sinusoidal signal is digitally fine-tuned by the digital correction module to obtain the target sinusoidal signal. Finally, the sinusoidal angle information obtained by the solution module in the signal correction circuit after fine-tuning the target sinusoidal signal is used as the output signal. This means that the signal correction circuit corrects the analog signal to roughly meet the user's requirements and then fine-tunes the corresponding digital signal. The fine-tuning here mainly refers to the correction of the bias, gain, phase, and harmonics of the digital signal.

[0124] In this embodiment, the fine-tuning of the digital signal includes digital correction using correction parameters for bias, gain, phase, and harmonics. The digital signal obtained from each fine-tuning is compared with the ideal digital signal to determine the error. Based on the determined error, the digital correction parameters are continuously optimized until the digital correction result meets the user-defined requirements. After obtaining the target sine and cosine signals, the angle of the fine-tuned signal can be calculated. Through correction and fine-tuning, the signal processing accuracy of the off-axis split encoder can be guaranteed.

[0125] When the amplitude of the sinusoidal signal is greater than or equal to the preset sinusoidal signal amplitude, the preset sinusoidal signal amplitude and the preset sinusoidal signal bias are two preset values ​​in the preset sinusoidal threshold. The first adjustment amplification factor corresponding to the initial sinusoidal amplification factor in the sinusoidal signal amplitude can be determined as a correction parameter in the first analog correction parameter set. When the sinusoidal signal bias is greater than or equal to the preset sinusoidal signal bias, the first adjustment bias level corresponding to the initial sinusoidal bias level in the sinusoidal signal bias is determined as a correction parameter in the first analog correction parameter set. The first adjustment amplification factor refers to the adjustment amplification factor corresponding to the initial sinusoidal amplification factor adjusted according to the sinusoidal signal amplitude. The first adjustment bias level and the first adjustment amplification factor are continuously replaced until the requirements are met. For example, in a sinusoidal digital signal, the amplitude of the sinusoidal signal is *a*, the bias is *b*, the preset amplitude is *c*, and the preset bias is *d*, where *a* > *c* and *b* > *d*. This determines the first adjustment amplification factor *e* and the first adjustment bias level *f*, respectively. Here, there is a correspondence between the sinusoidal signal amplitude and the adjustment amplification factor, and a correspondence between the sinusoidal signal bias and the adjustment bias level. For example, the correspondence can be defined as a sinusoidal signal amplitude of 5 corresponding to an adjustment amplification factor of 5, or it can be defined as: when the adjustment amplification factor is 5, if the sinusoidal signal amplitude is greater than or equal to the preset sinusoidal signal amplitude, then the adjustment amplification factor is appropriately reduced. This continues until the requirements are met. The output signal that meets the requirements is then output as the first pseudo-sinusoidal signal. The initial cosine signal is processed in the same way as the initial sine signal, and both are processed synchronously.

[0126] The processing method of the initial cosine signal is the same as that of the initial sine signal. When the amplitude of the cosine signal is greater than or equal to the preset cosine signal amplitude or the cosine signal offset is greater than or equal to the preset cosine signal offset, where the preset cosine signal amplitude and the preset cosine signal offset are two preset values in the preset cosine threshold, the second adjustment magnification corresponding to the adjustment of the initial cosine magnification in the cosine signal amplitude will be determined as a correction parameter in the second analog correction parameter set. When the cosine signal offset is greater than or equal to the preset cosine signal offset, the second adjustment bias level corresponding to the adjustment of the initial cosine bias level in the cosine signal offset will be determined as a correction parameter in the second analog correction parameter set. The second adjustment magnification refers to the adjusted magnification corresponding to the adjustment of the initial cosine magnification according to the cosine signal amplitude, and the second adjustment bias level refers to the adjusted bias level corresponding to the adjustment of the initial cosine bias level according to the cosine signal amplitude. The second adjustment bias level and the second adjustment magnification are continuously replaced until the requirements are met. For example, if the amplitude of the cosine signal in the cosine digital signal is g, the cosine signal offset is h, the preset cosine signal amplitude is c, and the preset cosine signal offset is d, where g > c and h < d, the first adjustment magnification i corresponding to g will be determined, and there is no need to determine the second adjustment bias level corresponding to the cosine signal offset h. Here, there is a corresponding relationship between the cosine signal amplitude and the adjustment magnification, and a corresponding relationship between the cosine signal offset and the adjustment bias level. The second adjustment magnification, the first adjustment magnification, the second adjustment bias level, and the first adjustment bias level are all iteratively updated. When new ones are generated, the old data will be replaced. By updating the magnification and the bias level, the update of the initial analog correction parameter set is realized. Therefore, the initial analog correction parameter set will only be used for the first time after installation, and then it will be continuously and accurately updated. Here, a situation different from the above is exemplified. Also, the preset sine / cosine signal amplitude / offset can also refer to the difference between the amplitudes / offsets of the two signals. Subsequently, operations will be performed on whether the difference between the two meets the requirements. When it is greater, the magnification / bias level will be changed to narrow the gap between the two.

[0127] Further, the step of determining the first sine signal corresponding to the sine signal with the phase to be corrected may include:

[0128] Step h, determining an initial sine phase difference parameter according to the initial phase difference parameter, the sine signal with the phase to be corrected, and the cosine signal with the phase to be corrected;

[0129] Step i, performing analog correction on the sine signal with the phase to be corrected by using the initial sine phase difference parameter to obtain a third sine signal;

[0130] Step j: If the phase difference between the third sine signal and the cosine signal to be corrected is not equal to the preset phase difference value, the initial sine phase difference parameter is adjusted to obtain the third analog correction parameter set.

[0131] Step k: Use the third analog correction parameter set to perform analog correction on the third sine signal until the phase difference is equal to the preset phase difference value to obtain the first sine signal.

[0132] In this embodiment, when the initial sine / cosine signal after correction meets the requirement (less than the preset sine / cosine threshold), a phase-corrected sine / cosine signal is obtained. Then, the phase-corrected sine / cosine signal is phase-corrected to obtain a first sine / cosine signal. Based on the initial phase difference parameter, the phase-corrected sine signal, and the phase-corrected cosine signal, an initial sine phase difference parameter is determined. By using the initial sine phase difference parameter to simulate and correct the phase-corrected sine signal, a third sine signal is obtained. Here, the third sine signal refers to the phase-corrected sine signal that has undergone phase correction using the initial sine phase difference parameter in the initial simulated correction parameter set. The phase difference between the third sine signal and the phase-corrected cosine signal is judged. When the phase difference is not equal to the preset phase difference value, the initial sine phase difference parameter is adjusted to obtain a third simulated correction parameter set. The third sine signal is then simulated and corrected again using the third simulated correction parameter set until the phase difference equals the preset phase difference value, thus obtaining the first sine signal.

[0133] In this embodiment, the preset phase difference value refers to correcting the phase difference between the two signals to 90°. The purpose of phase difference correction is to make the phase difference between the first sine signal and the second sine signal equal to 90°. Therefore, the third initial analog correction parameter set can be adjusted and determined, and the third sine signal can be simulated and corrected again using the third initial analog correction parameter set until the phase difference equals the preset phase difference value. The third analog correction parameter set is updated based on the third sine signal.

[0134] In this embodiment, the phase of the first quasi-sine signal can be corrected while keeping the phase of the cosine signal to be corrected unchanged; alternatively, the phase of the cosine signal to be corrected can be corrected while keeping the first quasi-sine signal unchanged; or both the first quasi-sine signal and the cosine signal to be corrected can be corrected simultaneously. The first two cases only require updating one set of phase difference parameters, while the third requires updating two sets of phase difference parameters. The specific choice can be made based on actual circumstances, and this embodiment does not limit this approach.

[0135] In this embodiment, the update method of the phase difference parameter is similar to that of the amplification factor and bias voltage. Phase correction can improve the accuracy of the target signal.

[0136] Furthermore, after adjusting the initial simulation correction parameter set to obtain the first simulation correction parameter set, the following steps may be included:

[0137] Step m: Update the initial simulation correction parameter set to the first simulation correction parameter set;

[0138] Step n: Store the first set of simulated correction parameters in the correction parameter determination module.

[0139] In this embodiment, by updating the initial analog correction parameter set to a first analog correction parameter set and storing the first analog correction parameter set in the correction parameter determination module, the new sinusoidal amplification factor and the new sinusoidal bias voltage in the first analog correction parameter set are determined. These two parameters are then sent to the corresponding modules, and the initial sinusoidal signal is reprocessed using the changed parameters. Specifically, the sinusoidal amplification factor is sent to the first programmable operational amplifier (PGA), and the sinusoidal bias voltage is sent to the first analog adder to achieve the reprocessing of the sinusoidal signal. For example, the sinusoidal amplification factor and sinusoidal bias voltage can be exemplified by the first adjustable amplification factor and the first adjustable bias level, respectively. After determining the first adjustable amplification factor and the first adjustable bias level, the two parameters can be input to the corresponding devices (the first adjustable amplification factor is input to the first programmable operational amplifier (PGA) via the first programming control terminal, and the first adjustable bias level is input to the first analog adder via the first bias level control terminal).

[0140] In this embodiment, there exists a situation where, if either of the two values ​​is greater than or equal to a preset value, only the adjustment value corresponding to the value greater than the preset value will be sent to the corresponding device (the first programmable operational amplifier PGA or the first analog adder). Alternatively, the other value can be sent as before. Whenever the requirement is not met, a first analog correction parameter set is generated and stored in the correction parameter determination module, so that the correction parameter determination module can directly call it (here, if the requirement is not met, the latest first analog correction parameter set is called; if it is met, the initial analog correction parameter set is called for the next correction). Furthermore, the processing steps for the initial cosine signal are consistent with the processing flow for the initial sine signal, with the only possibility being that the condition meeting the requirement (preset cosine threshold) is different. This continues until the requirement is met, thus ensuring the intelligence of the entire off-axis split encoder, allowing parameters (amplification factor and bias voltage) to be adjusted according to actual conditions.

[0141] Furthermore, this embodiment also provides a schematic flowchart of a signal correction method, referring to... Figure 11In this embodiment, the entire circuit requires the acquisition of differential sinusoidal signals (referring to differential quadrature signals) or single-ended quadrature signals to start operating. Since both acquired signals are analog signals, the following explanation will use analog signals. Reference can also be made to... Figure 8 , Figure 8 This is a block diagram of a signal correction circuit. The numbers in the diagram are respectively related to... Figure 1 and Figure 2 The numbers in the code are mapped to each other, only with different symbols. The positive and negative signs at the PGA represent the positive and negative input terminals, respectively. Based on the signal flow from left to right, the symbols correspond to PGA-adder-filter-analog-digital converter (ADC). The first ADC can be skipped. First, the analog signal gain is corrected by the PGA; then, the analog signal bias is corrected by the adder; and finally, the analog signal is filtered by the filter, completing the analog signal correction process. Afterward, the analog signal is converted to a digital signal by the ADC. The digital signal is then acquired, and its amplitude is checked against a sampling threshold. If it is not less than the threshold, the PGA amplification factor is adjusted, and the analog signal gain correction via the PGA is resumed. If the signal amplitude is less than the sampling threshold, the signal bias is checked against the threshold. If it is not less than the threshold, the adder bias voltage is adjusted, and the analog signal bias correction via the adder is resumed. The sampling threshold can be user-defined or determined by actual needs. When the signal bias is less than the sampling threshold, the digital signal is processed, mainly including gain fine-tuning, bias fine-tuning, phase correction, and digital filtering. This digital signal processing method follows the traditional digital signal processing flow. Finally, the output signal is obtained by calculating the angle of the digital signal, thus ending the entire processing flow. Gain correction, bias correction, and filtering ensure the signal processing accuracy of the off-axis split encoder. Furthermore, adjusting the coefficients in the correction process based on the sampling threshold improves the intelligence of the off-axis split encoder.

[0142] The present invention also provides a signal correction device.

[0143] The device of the present invention includes: a memory, a processor, and a signal correction program stored in the memory and executable on the processor, wherein the signal correction program, when executed by the processor, implements the steps of the signal correction method as described above.

[0144] The present invention also provides a computer storage medium.

[0145] The present invention provides a signal correction program stored on a computer storage medium, which, when executed by a processor, implements the steps of the signal correction method described above.

[0146] The method implemented when the signal correction program running on the processor is executed can be referred to in various embodiments of the signal correction method of the present invention, and will not be repeated here.

[0147] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A signal correction circuit, applied to an off-axis split encoder, characterized in that, The signal correction circuit includes a sine signal input module, a first analog correction module, a first analog-to-digital converter, a cosine signal input module, a second analog correction module, a second analog-to-digital converter, a digital correction module, and an output interface. The sine signal input module is connected to the first analog correction module, the first analog correction module is connected to the first analog-to-digital converter, the cosine signal input module is connected to the second analog correction module, the second analog correction module is connected to the second analog-to-digital converter, and the digital correction module is connected to the first analog-to-digital converter, the second analog-to-digital converter, and the output interface, respectively. The first analog correction module receives an initial sine signal input from the sine signal input module. The initial sine signal is an analog signal. The first analog correction module is used to correct the initial sine signal based on correction parameters until the error is less than a preset threshold to obtain a first sine signal. The first analog-to-digital converter is used to convert the first sine signal into a digital signal to obtain a second sine signal; The second analog correction module receives the initial cosine signal input from the cosine signal input module. The initial cosine signal is an analog signal. The second analog correction module is used to correct the initial cosine signal based on correction parameters until the error is less than the preset threshold to obtain a first cosine signal. The correction parameters include the amplification factor for correcting the initial sine signal, the bias level for correcting the initial sine signal, the amplification factor for correcting the initial cosine signal, and the bias level for correcting the initial cosine signal. The second analog-to-digital converter is used to convert the first cosine signal into a digital signal to obtain a second cosine signal; The digital correction module is used to digitally correct the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal.

2. The signal correction circuit as described in claim 1, characterized in that, The signal correction circuit includes a calculation module, which is connected to the digital correction module and the output interface respectively, and is used to calculate the angle signal based on the target sine signal and the target cosine signal.

3. The signal correction circuit as described in claim 2, characterized in that, The signal correction circuit further includes a first digital-to-analog converter, which includes a first digital-to-analog input terminal and a first digital-to-analog output terminal. The first digital-to-analog input terminal is connected to the digital correction module, and the first digital-to-analog output terminal is connected to the calculation module. It is used to convert the digital signals in the target sine signal and the target cosine signal into analog signals.

4. The signal correction circuit as described in claim 1, characterized in that, The signal correction circuit further includes a correction parameter determination module, which is connected to the digital correction module, the first analog correction module, and the second analog correction module respectively. The correction parameter determination module initially stores an initial analog correction parameter set and a digital correction parameter set. The initial analog correction parameter set is used to perform analog correction on the initial sine signal and the initial cosine signal, and the digital correction parameter set is used to perform digital correction on the second sine signal and the second cosine signal. The correction parameter determination module is further configured to adjust the initial analog correction parameter set based on the initial sine signal and initial cosine signal after analog correction, and update the initial analog correction parameter set to the adjusted analog correction parameters.

5. The signal correction circuit as described in claim 4, characterized in that, The first analog correction module includes a first programmable operational amplifier (PGA), a first analog adder, and a first filter. The first programmable operational amplifier (PGA) is connected to the sine wave input module and the correction parameter determination module, respectively. The first analog adder is connected to the first programmable operational amplifier (PGA), the first filter, and the correction parameter determination module, respectively. The first filter is connected to the first analog-to-digital converter. The first programmable operational amplifier (PGA) includes a first positive input terminal, a first negative input terminal, a first programming control terminal, and a first operational amplifier output terminal. The sine wave signal input module includes a positive sine wave signal interface and a negative sine wave signal interface. The first positive input terminal is connected to the positive sine wave signal interface, the first negative input terminal is connected to the negative sine wave signal interface, the first programming control terminal is connected to the correction parameter determination module, and the first operational amplifier output terminal is connected to the first analog adder. The second analog correction module includes a second programmable operational amplifier (PGA), a second analog adder, and a second filter. The second programmable operational amplifier (PGA) is connected to the cosine signal input module and the correction parameter determination module, respectively. The second analog adder is connected to the second programmable operational amplifier (PGA), the second filter, and the correction parameter determination module, respectively. The second filter is connected to the second analog-to-digital converter. The second programmable operational amplifier (PGA) includes a second positive input terminal, a second negative input terminal, a second programming control terminal, and a second operational amplifier output terminal. The cosine signal input module includes a sine / cosine signal interface and a negative / cosine signal interface. The second positive input terminal is connected to the sine / cosine signal interface, the second negative input terminal is connected to the negative / cosine signal interface, the second programming control terminal is connected to the correction parameter determination module, and the second operational amplifier output terminal is connected to the second analog adder.

6. The signal correction circuit as described in claim 5, characterized in that, The first analog adder includes a first adder input, a first adder output, and a first bias level control terminal. The first adder input is connected to the output of the first operational amplifier, the first adder output is connected to the first filter, and the first bias level control terminal is connected to the correction parameter determination module. The second analog adder includes a second adder input, a second adder output, and a second bias level control terminal. The second adder input is connected to the output of the second operational amplifier, the second adder output is connected to the second filter, and the second bias level control terminal is connected to the correction parameter determination module.

7. A signal correction method, characterized in that, The signal correction method is applied to the signal correction circuit according to any one of claims 1 to 6, and the steps of the signal correction method include: Obtain the initial sine signal; The initial sinusoidal signal is subjected to analog correction to obtain the first sinusoidal signal; The first sine signal is converted into a digital signal to obtain the second sine signal; Obtain the initial cosine signal; The initial cosine signal is subjected to analog correction to obtain the first cosine signal; The first cosine signal is converted into a digital signal to obtain the second cosine signal; The second sine signal and the second cosine signal are digitally corrected to obtain the corrected target sine signal and target cosine signal.

8. The signal correction method as described in claim 7, characterized in that, The first sinusoidal signal is obtained by analog correction of the initial sinusoidal signal, including: Obtain an initial simulation correction parameter set; wherein, the initial simulation correction parameter set contains multiple initial simulation correction parameters, including initial sine amplification factor, initial sine bias voltage, initial cosine amplification factor, initial cosine bias voltage, and initial phase difference parameter; The initial sinusoidal signal is simulated and corrected using the initial sinusoidal amplification factor and the initial sinusoidal bias voltage to obtain the corrected initial sinusoidal signal. If the sinusoidal error between the corrected initial sinusoidal signal and the ideal sinusoidal signal is greater than or equal to a preset sinusoidal threshold, the initial sinusoidal amplification factor and the initial sinusoidal bias voltage are adjusted to obtain a first set of analog correction parameters. The first set of simulated correction parameters is used to simulate and correct the initial sinusoidal signal after correction until the sinusoidal error is less than the preset sinusoidal threshold, thereby obtaining the phase-to-correct sinusoidal signal and determining the first sinusoidal signal corresponding to the phase-to-correct sinusoidal signal. Correspondingly, the initial sine signal is subjected to analog correction to obtain the first cosine signal, including: The initial cosine signal is simulated and corrected using the initial cosine amplification factor and the initial cosine bias voltage to obtain the corrected initial cosine signal. If the cosine error between the corrected initial cosine signal and the ideal cosine signal is greater than or equal to a preset cosine threshold, the initial cosine amplification factor and the initial cosine bias voltage are adjusted to obtain a second set of analog correction parameters. The initial cosine signal after correction is simulated and corrected using the second set of simulated correction parameters until the cosine error is less than the preset cosine threshold, thereby obtaining the phase-to-correct cosine signal and determining the first cosine signal corresponding to the phase-to-correct cosine signal.

9. The signal correction method as described in claim 8, characterized in that, The step of determining the first sinusoidal signal corresponding to the sinusoidal signal whose phase needs to be corrected includes: The initial sinusoidal phase difference parameter is determined based on the initial phase difference parameter, the sinusoidal signal to be corrected for phase, and the cosine signal to be corrected for phase. The initial sinusoidal phase difference parameter is used to simulate and correct the sinusoidal signal whose phase needs to be corrected, to obtain a third sinusoidal signal; When the phase difference between the third sinusoidal signal and the cosine signal to be corrected is not equal to the preset phase difference value, the initial sinusoidal phase difference parameter is adjusted to obtain the third analog correction parameter set. The third sinusoidal signal is simulated and corrected using the third set of analog correction parameters until the phase difference equals the preset phase difference value, thus obtaining the first sinusoidal signal.

10. The signal correction method as described in claim 8, characterized in that, After adjusting the initial simulation correction parameter set to obtain the first simulation correction parameter set, the process includes: Update the initial simulation correction parameter set to the first simulation correction parameter set; The first set of simulated correction parameters is stored in the correction parameter determination module.

11. The signal correction method as described in claim 7, characterized in that, After digitally correcting the second sine signal and the second cosine signal to obtain the corrected target sine signal and target cosine signal, the process further includes: The sinusoidal angle information is calculated based on the target sinusoidal signal; Cosine angle information calculated based on the target cosine signal; Output the sine angle information and the cosine angle information.

12. A computer storage medium, characterized in that, The computer storage medium stores a signal correction program, which, when executed by a processor, implements the steps of the signal correction method as described in any one of claims 7 to 11.

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