Spur power consumption analysis and power consumption reduction method, device, terminal and medium before integrated circuit chip tape-out

Abstract

The application provides a method, device, terminal and medium for glitch power consumption analysis and consumption reduction of an integrated circuit chip before tape-out, one or more key modules in a digital circuit are selected according to a preset digital circuit selection rule, and a netlist of the selected key modules is simulated to obtain glitch power consumption of the modules; one or more non-selected non-key modules are selected as typical modules, and the typical modules are simulated using different glitch propagation thresholds to obtain corresponding glitch power consumption; the netlist of the same typical module is simulated again to adjust the glitch propagation threshold and then apply the glitch power consumption to the calculation of other non-key modules according to the simulation result; the application can accurately evaluate glitch power consumption and effectively reduce consumption, and power consumption evaluation is realized at an early stage of chip design, and consumption reduction reaches about 28%.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chip power consumption analysis technology, and in particular to glitch power consumption analysis and power reduction methods, devices, terminals and media before integrated circuit chip tape-out. Background Technology

[0002] The power consumption of integrated circuit chips includes static power consumption and dynamic power consumption; dynamic power consumption accounts for the majority in most cases, mainly including the internal power consumption of the cell (digital circuit standard library unit), the switching power consumption of the interconnects, and glitch power. When a glitch is generated within the cell, it will propagate downstream. During the propagation process, the pulse width of the glitch gradually decreases, and eventually the glitch disappears. The glitch also consumes glitch power consumption along its propagation path.

[0003] Integrated circuit chip manufacturing processes have developed rapidly in recent years, with 5nm technology already in mass production. However, as integrated circuit chip processes have moved below 28nm, the proportion of glitch power consumption in dynamic power consumption has increased significantly. In some process nodes and some circuits, glitch power consumption accounts for more than 25% of dynamic power consumption.

[0004] Currently, the power consumption calculation method for digital circuits involves simulation on an RTL (Register Transfer Level) or gate-level netlist to generate simulation waveforms. Power analysis tools such as PTPX then read in the simulation waveforms and the gate-level netlist to calculate the power consumption. The accuracy of power consumption simulation and calculation on a netlist with delay after placement and routing is higher than that of power consumption simulation and calculation on a synthesized netlist (or RTL) without delay.

[0005] However, the accuracy of current glitch power consumption calculations is very low. In digital simulations, when the pulse width is less than x% of the cell delay, the glitch cannot propagate downstream; when it is greater than x%, the glitch propagates downstream. This x value needs to be set by the user. In reality, this model is too simplistic; the x value varies greatly across different modules, chips, and manufacturing processes. Setting different x values ​​can result in significantly different power consumption results. An example of obtaining glitch power consumption using a module digital simulation method: selecting the first x value, the glitch power consumption is 2.9 milliwatts; selecting the second x value, the glitch power consumption is 125 milliwatts, and the total module power consumption is 525 milliwatts. It is evident that glitch power consumption has a significant impact and is highly sensitive to x.

[0006] In addition to this, there is another method in the industry for predicting glitch power consumption: After the first chip manufactured using a new process is completed, power consumption is measured, and then analyzed using digital simulation methods to obtain a value of x. This value is then applied to subsequent chips manufactured using the same process. This method can be used for chips fabricated using older processes or chips other than the first chip fabricated using a new process, provided that the chip's function is similar to that of previous chips. However, this method has significant limitations.

[0007] As the impact of glitch power consumption becomes increasingly significant, current methodologies for calculating glitch power consumption are inaccurate. Accurate glitch power consumption can only be obtained through actual chip testing. The industry urgently needs to obtain accurate glitch power consumption before tape-out and hopes to obtain relatively accurate glitch power consumption in the early stages of chip design. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, apparatus, terminal and medium for glitch power consumption analysis and power reduction before integrated circuit chip tape-out, so as to solve the technical problem of inaccurate glitch power consumption analysis of integrated circuit chips.

[0009] To achieve the above and other related objectives, the first aspect of this application provides a method for glitch power consumption analysis and reduction before integrated circuit chip tape-out, comprising: selecting one or more key modules in a digital circuit according to a preset digital circuit selection rule, and simulating the netlist of the selected key modules to obtain the glitch power consumption of these modules; selecting one or more non-key modules that were not selected as typical modules, and performing digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; and simulating the netlist of the same typical module again, so as to adjust the glitch propagation threshold according to the simulation results and apply it to the glitch power consumption calculation of other non-key modules.

[0010] In some embodiments of the first aspect of this application, the preset digital circuit selection rules include any one or more combinations of the following: selecting key modules that have been instantiated multiple times and have high dynamic power consumption rankings for simulation; selecting key modules that are highly sensitive to glitch power consumption to glitch propagation threshold for simulation, wherein the glitch propagation threshold is used to determine whether glitch propagates downstream.

[0011] In some embodiments of the first aspect of this application, the preset digital circuit selection rule further includes: if the selected key module is large in scale and the simulation speed is slow, then an important sub-module in the key module is selected for simulation.

[0012] In some embodiments of the first aspect of this application, power consumption is also reduced by means of, for example, using digital circuit standard library cells instead of synthesis tools to build critical circuits.

[0013] In some embodiments of the first aspect of this application, power consumption is reduced by means of the following: selecting digital circuit standard library units with similar delays so that the delays of signals input to different input terminals of the digital logic circuit are similar at the output terminal.

[0014] In some embodiments of the first aspect of this application, power consumption is reduced by means of the following: for input signals that have experienced fewer logic layers, a number of dummy units are added to their input paths to increase the number of logic layers they have experienced, so that the number of logic layers experienced by multiple input signals after each digital circuit standard library unit is instantiated is the same.

[0015] In some embodiments of the first aspect of this application, the input signals of the integrated circuit chip with optimized glitch power consumption are optimized by using multiple delay matchers to transmit the input signals to match the delays between the input signals.

[0016] In some embodiments of the first aspect of this application, when the same integrated circuit chip is instantiated multiple times, a delay matching array with the same number of columns as the number of input signals is provided, and each column includes a delay matching unit with the same number of instantiations; the output signal of each row of delay matching units in the delay matching array is transmitted to each input port of the corresponding instantiated integrated circuit chip.

[0017] To achieve the above and other related objectives, a second aspect of this application provides an early glitch power consumption analysis and power reduction method at the module level before integrated circuit chip tape-out, comprising: simulating the synthesized module netlist of a module in a digital circuit to obtain the synthesized glitch power consumption of the synthesized module netlist, for use in analyzing the magnitude of the glitch power consumption of the module.

[0018] Furthermore, before the integrated circuit chip is fabricated, different module architectures and design methods are compared, and an architecture and design method with low glitches and power consumption are selected; the effectiveness of different power reduction methods is evaluated, and each power reduction method is selected based on the evaluation results.

[0019] To achieve the above and other related objectives, a third aspect of this application provides a glitch power consumption analysis and reduction device before integrated circuit chip tape-out, comprising: a critical module glitch power consumption analysis module, configured to select one or more critical modules in a digital circuit according to a preset digital circuit selection rule, and simulate the netlist of the selected critical modules to obtain the glitch power consumption of these modules; a non-critical module glitch power consumption analysis module, configured to select one or more non-critical modules as typical modules from the unselected non-critical modules, and perform digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; and to simulate the netlist of the same typical module again, so as to adjust the glitch propagation threshold according to the simulation results and apply it to the glitch power consumption calculation of other non-critical modules.

[0020] To achieve the above and other related objectives, a fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements a method for analyzing glitch power consumption and reducing power consumption before the integrated circuit chip is fabricated.

[0021] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, comprising: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the glitch power consumption analysis and power reduction method before the integrated circuit chip is fabricated.

[0022] As described above, the glitch power consumption analysis and power reduction method, apparatus, terminal and medium of this application before integrated circuit chip tape-out have the following beneficial effects:

[0023] (1) This invention provides a method for obtaining accurate glitch power consumption at the module level and a method for obtaining relatively accurate glitch power consumption at the chip level. This method is not limited; it can be used even when there is no reference chip under a new process, or when there is no chip of the same type for reference.

[0024] (2) The power consumption analysis method of the present invention has high accuracy because the power consumption of key modules is obtained through Spice simulation, while that of non-key modules is obtained through correlation analysis of Spice simulation and digital simulation. This method provides more granular power consumption analysis and stronger guidance.

[0025] (3) The power consumption analysis method of the present invention can be combined with traditional methods to improve the accuracy of traditional methods or increase the speed at which the present method obtains power consumption data.

[0026] (4) This invention provides a method for evaluating glitches and power consumption in the early stages of chip design, thereby allowing for the selection of different architectures.

[0027] (5) A module-level method for reducing glitch power consumption is provided. Combined with the front-end method for evaluating glitch power consumption, the power consumption of key modules can be reduced by about 28%. Attached Figure Description

[0028] Figure 1 The diagram shown is a flowchart illustrating a method for analyzing and reducing power consumption of integrated circuit chips before tape-out, according to an embodiment of this application.

[0029] Figure 2A The diagram shown is a schematic representation of a two-input AND gate in one embodiment of this application.

[0030] Figure 2B The diagram shows a jump in the input signal of a two-input AND gate in one embodiment of this application.

[0031] Figure 2C The diagram shows a pulse generated at the output of a two-input AND gate in one embodiment of this application.

[0032] Figure 3 The diagram shown is a schematic representation of a 6-input addition tree in one embodiment of this application.

[0033] Figure 4 The diagram shows the same submodule being instantiated four times in one embodiment of this application.

[0034] Figure 5 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application.

[0035] Figure 6 The diagram shown is a structural schematic of a device for analyzing and reducing power consumption of integrated circuit chips before tape-out, according to an embodiment of this application. Detailed Implementation

[0036] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0037] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0038] To address the problems mentioned above in the background art, this invention provides a method, apparatus, terminal, and storage medium for analyzing and reducing glitch power consumption before integrated circuit chip tape-out, aiming to obtain relatively accurate glitch power consumption in the early stages of integrated circuit chip design, and also provides a technical solution for reducing glitch power consumption.

[0039] Meanwhile, to make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.

[0040] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0041] <1> Glitches: These are intermediate states caused primarily by imbalances in circuit delays.

[0042] <2> Spice (Simulation Program With Integrated Circuit Emphasis): A general-purpose analog circuit simulator used in circuit analysis programs for integrated circuit chips.

[0043] <3> Cell: A standard library unit for digital circuits, also known as a Standard Cell. This invention provides a method for glitch power consumption analysis and reduction before integrated circuit chip tape-out, a system for the method, and a storage medium storing an executable program for implementing the method. Regarding the implementation of the method, this invention will describe exemplary implementation scenarios.

[0044] like Figure 1 The diagram illustrates a flowchart of a method for analyzing and reducing power consumption glitch before integrated circuit chip fabrication according to an embodiment of the present invention. The method for analyzing and reducing power consumption glitch before integrated circuit chip fabrication in this embodiment mainly includes the following steps:

[0045] Step S11: Select one or more key modules in the digital circuit according to the preset digital circuit selection rules, and simulate the netlist of the selected key modules to obtain the glitch power consumption of these modules and reduce the power consumption.

[0046] In this embodiment, the Spice simulator is used to simulate the selected key modules. Since Spice simulation is time-consuming, and digital circuits are typically large in scale, it is necessary to select a portion of the digital circuit as the simulation object. This selected portion of the digital circuit should possess key modules with typical characteristics to represent the entire digital circuit.

[0047] It should be understood that Spice (circuit simulator) simulation is a circuit-level simulation program, commonly used in analog circuit simulation, but it is generally not applied to digital circuits due to its slow speed. Spice simulation results are very accurate; the difference between the power consumption obtained from Spice simulation of a module netlist with delay after placement and routing and the actual measured power consumption of the chip is generally within 3%. However, in this embodiment of the invention, performing Spice simulation on digital circuits can accurately obtain the pulse width change when glitches pass through standard library cells of digital circuits, thereby avoiding the error introduced by manually setting x in digital circuit simulation tools and greatly improving the accuracy of glitch power consumption analysis.

[0048] It should be noted that glitches are mainly intermediate states caused by imbalances in circuit delays. Figures 2A-2C To explain the principle of burr formation: Figure 2A In a 2-input AND gate, there are three ports: input A, input B, and output OUT. Figure 2B In the two-input AND gate, the timing of the transition of the input signal at input terminal A is inconsistent with the timing of the transition of the input signal at input terminal B; Figure 2C In a two-input AND gate, the output terminal OUT generates a pulse, which is called a glitch. The power consumed by the glitch is called glitch power consumption.

[0049] In this embodiment, the preset digital circuit selection rules include any one or more combinations of the following: selecting key modules with more data path operations and higher dynamic power consumption for simulation; selecting key modules that have been instantiated multiple times and have higher dynamic power consumption for simulation; selecting key modules with high sensitivity to glitch propagation threshold for simulation, wherein the glitch propagation threshold is used to determine whether the glitch propagates downstream; wherein the digital circuit selection rules also include: if the selected key module is large in scale and the simulation speed is slow, then an important sub-module in the key module is selected for simulation.

[0050] Those skilled in the art should understand that the technical features mentioned in the embodiments of the present invention, such as "more," "ranked higher," and "high sensitivity," can all be concluded by comparing them with preset thresholds. For example, selecting digital circuits with more data path operations and higher dynamic power consumption for simulation actually means selecting digital circuits with more data path operations than a preset threshold and higher dynamic power consumption than a preset ranking for simulation.

[0051] Step S12: Select one or more non-critical modules that were not selected as typical modules, and perform digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; perform simulation again on the netlist of the same typical module, and adjust the glitch propagation threshold according to the simulation results before applying it to the glitch power consumption calculation of other non-critical modules.

[0052] Specifically, Spice simulation is first performed on selected critical modules in the digital circuit. The simulation results accurately reflect the glitches and power consumption of these critical modules. For non-critical modules not selected in the digital circuit, one or more modules are chosen as typical modules. Digital simulation is then performed on these selected typical modules using different x-parameters (i.e., the glitch width is x% of the cell delay, used to determine whether the glitch can propagate downstream) to obtain the corresponding glitches and power consumption. Simultaneously, Spice simulation is also performed on the same typical module. Correlation analysis is performed between the Spice simulation results and the digital simulation results to obtain similar x-parameters. These x-parameters are then applied to other non-critical modules to obtain the glitches and power consumption of other modules in the digital circuit.

[0053] In some examples, the glitch power consumption analysis and reduction method for integrated circuit chips before tape-out provided in this embodiment of the invention further includes reducing glitch power consumption in the data path of key modules through any of the following power reduction methods:

[0054] Energy saving method 1) Use digital circuit standard library cells instead of synthesis tools (such as EDA) to build critical circuits. It should be noted that the digital circuit standard cell library includes layout library, symbol library, circuit logic library, etc.; it contains combinational logic, sequential logic, functional units and special type units, and is the foundation of the back-end design process of integrated circuit chips; using pre-designed and optimized library cells for automatic logic synthesis and layout placement and routing can greatly improve design efficiency and speed up the time to market.

[0055] Power saving method 2) Select standard library units of digital circuits with similar delays so that the delays of signals input to different input terminals of the digital logic circuit at the output terminal are similar. For example, by selecting standard library units of digital circuits with similar delays, the delays of signals input to different input terminals in a full adder to the sum output terminal are similar.

[0056] Power saving method 3) For input signals that traverse a small number of logic layers, add several dummy units along their input path to increase the number of logic layers they traverse, so that the number of logic layers traversed by multiple input signals after instantiation of each digital circuit standard library cell is the same. For example, if multiple input signals after instantiation of each cell all pass through 6 full adders, then the output delay will also be similar.

[0057] It is worth noting that if the number of logic layers is different or the delays differ greatly, a low-power delay matcher (such as a buffer or a similar circuit (such as a pair of inverters)) needs to be inserted to match the delay difference. When the delay is difficult to match or the power consumption of the glitches is large, a register should be added after it to interrupt the propagation path of the glitches.

[0058] To facilitate understanding by those skilled in the art, the following is combined with Figure 3 The following example illustrates a 6-input addition tree: There are three layers of logic in the diagram. The first layer consists of full adder 1 and full adder 2. The second layer consists of full adder 3 and a dummy unit. The third layer consists of full adder 4. The six input signals are in1, in2, in3, in4, in5, and in6.

[0059] Assuming the delays from the three inputs (input A, input B, and input C) of the full adder to the sum output are similar, and the delay from input A to the carry output is similar to its delay to the sum output, the input paths of full adder 4 (inputs A and B) both experience two layers of full adder delay. If input C of full adder 4 is directly connected to the sum output of full adder 2, there would only be one layer of full adder delay, resulting in glitch power consumption for full adder 4. Therefore, in this embodiment, the sum output of full adder 2 is buffered by a dummy unit, thereby matching the delay of one full adder and ensuring that the three input delays of full adder 4 are similar, reducing glitch power consumption. In this embodiment, the dummy unit is preferably a low-power unit.

[0060] In some examples, the glitch power consumption analysis and power consumption reduction method for integrated circuit chips before tape-out provided in this embodiment of the invention further includes optimizing the input signal of the integrated circuit chip with optimized glitch power consumption, and using multiple delay matchers (including buffers or pairs of inverters, etc.) to transmit the input signal to match the delay between each input signal.

[0061] Specifically, the inputs of integrated circuit chips with optimized glitch power consumption are optimized: if the inputs are directly connected to the critical circuits in the above sub-modules, multiple buffers or multiple pairs of inverters are used to transmit the signals to these inputs, and they are connected to these sub-modules in appropriate locations. If there are multiple inputs, the corresponding buffer positions between the multiple inputs need to be close, and the delays of the multiple inputs need to be matched.

[0062] In some examples, when the same integrated circuit chip is instantiated multiple times, a delay matcher array with the same number of columns as the number of input signals is set up, and each column includes the same number of delay matchers as the number of instantiations; the output signal of each row of delay matchers in the delay matcher array is transmitted to each input port of the corresponding instantiated integrated circuit chip.

[0063] For example, such as Figure 4 The example shown illustrates the same submodule instantiated four times. The submodule has two inputs, in1 and in2. The internal circuit structure of this submodule can be found in [reference needed]. Figure 3 . Figure 4 in1 and in2 are connected to Figure 3 in1, in2, Figure 3 The other four inputs (in3~in6) are grounded. If the delays of in1 and in2 before entering the submodule differ significantly, large glitch power consumption will still occur in the submodule circuit. Therefore, this embodiment of the invention... Figure 4The physical distribution and connection of input signals sig1 and sig2 avoids introducing large capacitances into the input signal connections, thus preventing significant delays and delay mismatches between input signals, thereby avoiding large glitches and power consumption within the submodule. Specifically, a 4x2 buffer matrix is ​​formed, with each column containing 4 buffers serving 4 instantiations. For example, the output signal of buffer 11 is input to the in1 input of submodule instance 1, the output signal of buffer 21 is input to the in2 input of submodule instance 1, the output signal of buffer 12 is input to the in1 input of submodule instance 2, the output signal of buffer 22 is input to the in2 input of submodule 2, and so on.

[0064] Using the glitch power consumption analysis and power reduction method for integrated circuit chips before tape-out provided in this embodiment of the invention, data was obtained after optimizing the glitch power consumption of a sub-module in an example: before optimization, the current consumption was 3.559 mA, and after glitch power consumption optimization, the current consumption was reduced to 2.5962 mA, with a power consumption reduction of up to 28%.

[0065] This invention also provides a method for early glitch power consumption analysis and reduction at the module level before integrated circuit chip tape-out, achieving early glitch power consumption and power reduction at the module level. It should be noted that the technical content in steps S11-S12 above pertains to chip-level early glitch power consumption analysis and power reduction methods, while this embodiment aims to achieve module-level early glitch power consumption analysis and power reduction methods. Specific steps include: simulating the synthesized module netlist of the digital circuit to obtain the synthesized module netlist's comprehensive glitch power consumption, which is used to analyze the magnitude of the module's glitch power consumption.

[0066] Furthermore, this includes comparing different module-level architectures and design methodologies early in the project and selecting those with low glitches and power consumption. It also includes evaluating the effectiveness of different power reduction methods and making trade-offs. Additionally, it includes continuing to try other power reduction methods if glitches and power consumption exceed the design target.

[0067] It should be noted that the synthesized netlist refers to the netlist of the critical modules. The preceding steps provide a method for analyzing the glitches and power consumption of the entire chip. Furthermore, the simulation of critical modules or non-critical modules (which are electrical modules) in the preceding steps is generally performed on the netlist after placement and routing (higher accuracy, slower speed), rather than on the synthesized netlist, thus obtaining a relatively accurate value for the glitches and power consumption of the entire chip. Simulating the synthesized netlist is obviously less accurate than the preceding steps, but the simulation speed is faster, and in the early stages of the chip development process, it is advantageous to evaluate the glitches and power consumption of some critical modules. Because critical modules can have different architectures and design methods, but previously there was no relatively accurate method for evaluating glitches and power consumption, it was impossible to select the architecture and design method of the module based on glitches and power consumption. When simulating these modules, the results of glitches and power consumption under different architectures can be obtained relatively quickly in the early stages of development, thereby selecting the implementation architecture and design method, and simultaneously reducing power consumption. Because this invention provides a power reduction scheme, its effectiveness needs to be evaluated; if the effect is unsatisfactory, this method should be abandoned. If the power reduction effect does not meet the requirements, other power reduction methods should be explored.

[0068] The glitch power consumption analysis and reduction method provided in this invention for supplying integrated circuit chips before tape-out can be implemented on the terminal side or the server side. For the hardware structure of the glitch power consumption analysis terminal for supplying integrated circuit chips before tape-out, please refer to [link to relevant documentation]. Figure 5 This is a schematic diagram of an optional hardware structure of an electronic terminal 500 provided in an embodiment of the present invention. The terminal 500 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The electronic terminal 500 includes: at least one processor 501, a memory 502, at least one network interface 504, and a user interface 506. The various components in the device are coupled together through a bus system 505. It is understood that the bus system 505 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 505 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 The general will label all buses as bus systems.

[0069] The user interface 506 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0070] It is understood that memory 502 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0071] In this embodiment of the invention, the memory 502 is used to store various types of data to support the operation of the electronic terminal 500. Examples of this data include: any executable program for operation on the electronic terminal 500, such as the operating system 5021 and application program 5022; the operating system 5021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 5022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The method for glitch power consumption analysis and power reduction before integrated circuit chip tape-out provided in this embodiment of the invention can be included in the application program 5022.

[0072] The methods disclosed in the above embodiments of the present invention can be applied to processor 501, or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 501 or by instructions in the form of software. The processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 501 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0073] In an exemplary embodiment, the electronic terminal 500 may be used by one or more application-specific integrated circuit (ASIC), DSP, programmable logic device (PLD), or complex programmable logic device (CPLD) to perform the aforementioned method.

[0074] like Figure 6 The diagram illustrates a structural schematic of a glitch power consumption analysis device for integrated circuit chip fabrication before tape-out, according to an embodiment of the present invention. In this embodiment, the glitch power consumption analysis device 600 for integrated circuit chip fabrication before tape-out includes a critical module glitch power consumption analysis module 601 and a non-critical module glitch power consumption analysis module 602.

[0075] The key module glitch power consumption analysis module 601 is used to select one or more key modules in the digital circuit according to the preset digital circuit selection rules, and to simulate the netlist of the selected key modules to obtain the glitch power consumption of these modules.

[0076] In some examples, the preset digital circuit selection rules include any one or more combinations of the following: selecting key modules that have been instantiated multiple times and have high dynamic power consumption for simulation; selecting key modules whose glitch power consumption is highly sensitive to the glitch propagation threshold for simulation, wherein the glitch propagation threshold is used to determine whether the glitch propagates downstream.

[0077] In some examples, the preset digital circuit selection rules also include: if the selected key module is too large and the simulation speed is too slow, then an important sub-module in the key module is selected for simulation.

[0078] The non-critical module glitch power consumption analysis module 601 is used to select one or more non-critical modules as typical modules from the unselected non-critical modules, and to perform digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; and to perform simulation on the netlist of the same typical module again, so as to adjust the glitch propagation threshold according to the simulation results and apply it to the glitch power consumption calculation of other non-critical modules.

[0079] In some examples, the glitch power consumption analysis device 600 also includes a power reduction module 603.

[0080] Optionally, the power consumption reduction module 603 reduces power consumption by using digital circuit standard library units instead of synthesis tools to build critical circuits.

[0081] Optionally, the power consumption reduction module 603 reduces power consumption by selecting digital circuit standard library units with similar delays, so that the delays of signals input to different input terminals of the digital logic circuit at the output terminal are similar.

[0082] Optionally, the power consumption reduction module 603 reduces power consumption in the following way: for input signals that have experienced fewer logic layers, several dummy units are added to their input paths to increase the number of logic layers they have experienced, so that the number of logic layers experienced by multiple input signals after instantiation of each digital circuit standard library unit is the same.

[0083] In some examples, the input signals of integrated circuit chips with optimized glitches and power consumption are optimized by using multiple delay matchers to transmit the input signals to match the delays between each input signal.

[0084] Furthermore, when the same integrated circuit chip is instantiated multiple times, a delay matching array with the same number of columns as the number of input signals is set up, and each column includes a delay matching unit with the same number of instantiations; the output signal of each row of delay matching units in the delay matching unit array is transmitted to each input port of the corresponding instantiated integrated circuit chip.

[0085] It should be noted that the above-described embodiment of the glitch power consumption analysis device for integrated circuit chips before tape-out is only illustrated by the division of the above-described program modules. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program modules to complete all or part of the processing described above. Furthermore, the above-described embodiment of the glitch power consumption analysis device for integrated circuit chips before tape-out and the embodiment of the glitch power consumption analysis and power reduction method for integrated circuit chips before tape-out belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0086] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0087] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact optical discs (CDs), laser optical discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0088] In summary, this application provides a method, apparatus, terminal, and medium for glitch power consumption analysis and reduction before integrated circuit chip tape-out. This invention provides a method for obtaining accurate glitch power consumption at the module level and a method for obtaining relatively accurate glitch power consumption at the chip level. This method is not limited; it can be used even when there is no reference chip under a new process or when there is no similar chip for reference. The power consumption analysis method of this invention has high accuracy because the power consumption of critical modules is obtained through Spice simulation, and non-critical modules are obtained through Spice simulation and digital simulation correlation analysis. This method provides finer granularity and stronger guidance in power consumption analysis. The power consumption analysis method of this invention can be combined with traditional methods to improve the accuracy of traditional methods or to increase the speed at which this method obtains power consumption data. This invention provides a method for evaluating glitch power consumption in the early stages of chip design, thereby allowing for the selection of different architectures. It provides a method for reducing glitch power consumption at the module level; combined with the front-end glitch power consumption evaluation method, critical modules can reduce power consumption by approximately 28%. Therefore, this application effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0089] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for analyzing and reducing power consumption due to glitches before integrated circuit chip tape-out, characterized in that, include: Select one or more key modules in the digital circuit according to the preset digital circuit selection rules, and simulate the netlist of the selected key modules to obtain the glitch power consumption of these modules. Select one or more non-critical modules that were not selected as typical modules, and perform digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; perform simulation on the netlist of the same typical module again, and adjust the glitch propagation threshold according to the simulation results before applying it to the glitch power consumption calculation of other non-critical modules. The preset digital circuit selection rules include any one or more combinations of the following: selecting key modules that have been instantiated multiple times and have high dynamic power consumption for simulation; selecting key modules that are highly sensitive to the glitch propagation threshold for simulation, wherein the glitch propagation threshold is used to determine whether the glitch propagates downstream; The preset digital circuit selection rules also include: if the selected key module is too large and the simulation speed is too slow, then an important sub-module in the key module will be selected for simulation. The simulation is performed using the Spice simulator.

2. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, This also includes reducing power consumption through methods such as: using standard digital circuit library cells instead of synthesis tools to build critical circuits.

3. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, It also includes reducing power consumption by methods such as selecting standard library units of digital circuits with similar delays, so that the delays of signals input to different input terminals of digital logic circuits are similar at the output terminal.

4. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, It also includes reducing power consumption in ways such as: for input signals that have experienced fewer logic layers, add several dummy units on their input path to increase the number of logic layers they have experienced, so that the number of logic layers experienced by multiple input signals after instantiation of each digital circuit standard library unit is the same.

5. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, The input signals of integrated circuit chips with optimized glitch power consumption are optimized by using multiple delay matchers to transmit the input signals to match the delays between each input signal.

6. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, When the same integrated circuit chip is instantiated multiple times, a delay matching array with the same number of columns as the number of input signals is set up, and each column includes the same number of delay matching units as the number of instantiations; The output signal of each row of delay matchers in the delay matcher array is transmitted to each input port of the corresponding sub-instantiated integrated circuit chip.

7. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 1, characterized in that, include: The synthesized module netlist of the digital circuit is simulated to obtain the synthesized glitch power consumption of the synthesized module netlist, which is used to analyze the magnitude of the glitch power consumption of the module.

8. The method for analyzing and reducing power consumption of integrated circuit chips before tape-out according to claim 7, characterized in that, Also includes: Before the integrated circuit chip is fabricated, different module-level architectures and design methods are compared, and the architecture and design method with low glitches and power consumption are selected. The effectiveness of different power reduction methods is evaluated, and each power reduction method is selected based on the evaluation results.

9. A device for analyzing and reducing power consumption of integrated circuit chips before tape-out, characterized in that, include: The key module glitch power consumption analysis module is used to select one or more key modules in the digital circuit according to the preset digital circuit selection rules, and to simulate the netlist of the selected key modules to obtain the glitch power consumption of these modules. The non-critical module glitch power consumption analysis module is used to select one or more non-critical modules as typical modules from the unselected non-critical modules, and to perform digital simulation on the typical modules using different glitch propagation thresholds to obtain the corresponding glitch power consumption; the netlist of the same typical module is then simulated again, and the glitch propagation threshold is adjusted according to the simulation results before being applied to the glitch power consumption calculation of other non-critical modules. The preset digital circuit selection rules include any one or more combinations of the following: selecting key modules that have been instantiated multiple times and have high dynamic power consumption for simulation; selecting key modules that are highly sensitive to the glitch propagation threshold for simulation, wherein the glitch propagation threshold is used to determine whether the glitch propagates downstream; The preset digital circuit selection rules also include: if the selected key module is too large and the simulation speed is too slow, then an important sub-module in the key module will be selected for simulation. The simulation is performed using the Spice simulator.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method for analyzing and reducing power consumption of integrated circuit chips before tape-out as described in any one of claims 1 to 8.

11. An electronic terminal, characterized in that, include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the terminal performs the glitch power consumption analysis and power reduction method before the integrated circuit chip is fabricated as described in any one of claims 1 to 8.

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