A method for conflict detection and queuing of unified shader processor shared register file group mapping

Abstract

This invention relates to a conflict detection and queuing method for shared register file grouping mapping in a unified coloring graphics processor. The method includes the following steps: 1) Physical storage units are divided into 8 banks. Each warp is allocated 16 read operand addresses and 8 write operand addresses for operand collection. These 16 read operand addresses and 8 write operand addresses are decoded and mapped to the 8 banks; 2) A hierarchical grouping address mapping method with pipelined architecture is used. This is achieved by grouping the 16 read operand addresses and 8 write operand addresses of each bank and establishing a pipeline for mapping. This invention primarily addresses the access process of register files, providing a conflict detection and queuing mechanism to resolve bank conflicts that may occur during actual transmission.

Description

Technical Field

[0001] This invention belongs to the field of unified coloring graphics processor technology, specifically relating to a conflict detection and queuing mechanism for shared register file group mapping. Background Technology

[0002] With the increasing popularity of research and applications in data mining, machine learning, high-definition video image processing, and big data in recent years, the traditional CPU performance improvements in computers can no longer meet the growing computing demands of these applications. In this environment, various computing accelerators have emerged, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). Undoubtedly, GPUs are the most widely used, offering speedups of hundreds of times compared to CPUs for certain applications. As computing demands grow and the thread-level parallelism of GPUs increases, GPUs have also begun to be used in general-purpose computing, evolving into General Purpose Computing on Graphics Processing Units (GPGPUs). Today, GPUs no longer refer solely to dedicated graphics acceleration chips; they are more often SoCs (System-on-a-Chip) that can perform computations using massively parallel, thread-level parallelism (TLP). Modern computers can directly leverage the massive thread-level parallelism of GPUs for highly parallel computing. This parallel computing typically utilizes all computation-related hardware and employs appropriate algorithms to achieve significant acceleration.

[0003] The Unified Shading Array (USA) is the computational core of the Unified Shading Graphics Processor (GSP), occupying a considerable area within the GSP layout. Streaming multi-core processors (RFs) are the core components of the Unified Shading architecture GPU for texture processing, and the shading core is the basic shading unit of the USA. The organization of register files is a crucial aspect of its design. Registers are the most efficient storage components on the GPU, stored in register files (RFs). To reduce the cost of context switching, GPUs deploy a large number of register file resources for stream processors. The number of register files varies across stream processors depending on the GPU's computing power. GPU register files are much larger than the cache and are primarily composed of SRAM, making their area footprint significant. Due to the large number of shading cores and the numerous instances per core in a GPU, the number and size of register files are substantial. Therefore, the management and use of register files are crucial for GPU performance.

[0004] In a GPU, each colored core in a streaming multi-core processor exclusively uses the RF (Radio Frequency) within its SM (Streaming Controller). A warp is the basic unit of GPU scheduling and execution. Each warp needs to be allocated its own dedicated architecture register file, indexed by a warp ID, and each architecture register has corresponding physical registers allocated in the register file. Once allocated, registers are not released until the cooperating thread array to which the warp belongs has completed its execution. Therefore, the allocation and release management of register files becomes extremely important, and conflict detection and resolution strategies for read / write addresses are indispensable. Summary of the Invention

[0005] To address the technical problems existing in the background art, this invention provides a conflict detection and queuing method for unified coloring graphics processor shared register file group mapping. It mainly targets the access process of register files and provides a conflict detection and queuing mechanism to solve the bank conflict problem that may occur in actual transmission.

[0006] The technical solution of this invention is as follows: This invention is a conflict detection and queuing method for unified coloring graphics processor shared register file group mapping, which is characterized by the following steps:

[0007] 1) The physical storage unit is divided into 8 banks. Each warp is allocated 16 read operand addresses and 8 write operand addresses for operand collection. These 16 read operand addresses and 8 write operand addresses are decoded and mapped to the 8 banks.

[0008] 2) A hierarchical grouping address mapping method is adopted to establish a pipeline. The 16 read operand addresses and 8 write operand addresses of each group are grouped and a pipeline is established for mapping.

[0009] Furthermore, in step 1), each Bank has 2 read address interfaces and 1 write address interface, and can accept a maximum of 2 read operand addresses and 1 write operand address at the same time.

[0010] Furthermore, the specific steps of step 2) are as follows:

[0011] 2.1) The 16 read operand addresses and 8 write operand addresses were grouped into groups of 4, and the priority of each register group in the read-write mapping operation was specified.

[0012] 2.2) The mapping pattern was analyzed based on the priority relationship and a truth table was listed. The logical expression was further derived based on the truth table and the mapping combinational logic diagram of each level was drawn.

[0013] 2.3) Based on the performance of the pipeline, the generation method of the read and write valid signals during the write operation mapping process was analyzed, and the combinational logic formula was derived through its truth table, and its combinational logic diagram was further obtained.

[0014] 2.4) Separate read and write operations. Read operations require three levels of grouping mapping, while write operations only require two levels of grouping mapping.

[0015] Furthermore, during the read operation in step 2), the process is as follows:

[0016] 3.1) First, divide the 16 read operand addresses into 4 groups, where addr_0, addr_1, addr_8, and addr_9 belong to group_0; addr_2, addr_3, addr_10, and addr_11 belong to group_1; addr_4, addr_5, addr_12, and addr_13 belong to group_2; and addr_6, addr_7, addr_14, and addr_15 belong to group_3.

[0017] 3.2) Each address passes through a decoding unit, which decodes it to obtain the corresponding Bank and generates a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 read valid information register group Reg_rd_level_0. The data stored in Reg_rd_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the level 1 read valid information register group Reg_rd_level_1. The data stored in Reg_rd_level_1 then passes through the last mapping module Allocate_Logic_2 and is sent to the Bank for read operation. At the same time, it is temporarily stored in the level 2 read valid information register group Reg_rd_level_2 for read operand reordering. It is also necessary to determine the number of remaining address information in Reg_rd_level_1 to decide whether to pause the pipeline or send a new rdena signal. Finally, the address in Reg_rd_level_2 is sent to the Bank for the corresponding operation.

[0018] Furthermore, the specific steps of step 3.2) are as follows:

[0019] 3.2.1) Decode the 3-bit Bank judgment bits in the 16 read operand addresses to obtain the Bank number corresponding to the address and generate a valid signal valid_i_bj, where i represents the address number and j represents the Bank number;

[0020] 3.2.2) Each address i has a connection mapped to all banks. Each group contains 4 valid_i_bj values. The validity of the read address is determined based on the value of valid_i_bj and mapped to the 4 registers of Reg_rd_level_0, generating the corresponding valid signal; it is stipulated that the smaller the address number, the higher the priority.

[0021] 3.2.3) The data stored in register group Reg_rd_level_0 will be sent to Reg_rd_level_1 after passing through another mapping module, Allocate_Logic_Level_1. Reg_rd_level_1 is divided into two groups, each containing eight 4-bit registers and their valid signal, which are used to store the corresponding address information sent from the previous level. Each register in Reg_rd_level_0 has a corresponding valid bit. If the valid bit is 1, it means that the information in the register is valid and needs to be mapped to Reg_rd_level_1. If it is 0, it is invalid and does not need to be mapped. When information in Reg_rd_level_0 is mapped to a register in Reg_rd_level_1, the valid bit of the corresponding register in Reg_rd_level_1 is set to 1.

[0022] 3.2.4) The data in Reg_rd_level_1 is sent to Bank and Reg_rd_level_2 after passing through the last mapping module Allocate_Logic_Level_2. The data sent to Bank is 7 bits, which is used as the memory access address for reading operations. This 7-bit data is the address offset decoded from the real address corresponding to the address information in Reg_rd_level_1, i.e., the physical block number, and is no longer the 4-bit index information stored in the previous two levels. The data sent to Reg_rd_level_2 is still the 4-bit index information representing the read address number, used for reordering read operations.

[0023] 3.2.5) During the mapping from Reg_rd_level_1 to Reg_rd_level_2, it is necessary to simultaneously determine the remaining valid information in Reg_rd_level_1 across all 8 banks. This determination is used to decide whether to pause the pipeline or send a new rdena signal. If the remaining valid information in Reg_rd_level_1 of each of the 8 banks is less than or equal to 2, an rdena signal needs to be sent to the outside world, indicating that all data in Reg_rd_level_1 will be sent to the bank in the next cycle, the pipeline resumes operation, and a new set of read addresses needs to be sent to the system to begin mapping. If the remaining valid information in Reg_rd_level_1 of any bank is greater than 2, the pipeline continues to pause until the condition is met.

[0024] Furthermore, the specific process for writing the operation in step 2) is as follows:

[0025] 3.3) First, divide the 8 write operand addresses into 2 groups, where addr_0, addr_1, addr_4, and addr_5 belong to Group_0; and addr_2, addr_3, addr_6, and addr_7 belong to Group_1.

[0026] 3.4) Each write address first passes through a decoding unit to obtain the corresponding Bank and generate a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 write valid information register group Reg_wr_level_0. The data stored in Reg_wr_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the Bank for write operation. At the same time, it is necessary to determine the number of remaining address information in Reg_rd_level_0 in all 8 Banks to decide whether to pause the write pipeline or send a new wrena signal.

[0027] Furthermore, the specific steps of step 3.4) are as follows:

[0028] 3.4.1) By decoding the 3-bit Bank judgment bits in the address information of the 8 write operands, the Bank corresponding to the address is obtained and a valid signal valid_i_bj is generated, where i represents the address number and j represents the Bank number; each address i has a connection mapped to all Banks. For a certain address, when the decoding result is mapped to a certain Bank, valid_i_bj corresponding to that Bank is set to 1, and valid_i_bj corresponding to the other 7 Banks is set to 0; its mapping logic is the same as the mapping logic of address decoding information to Reg_rd_level_0 in the read operation;

[0029] 3.4.2) During a write operation, the write address index information stored in Reg_wr_level_0 is sent to the Bank for write operation after passing through the second mapping module Allocate_Logic_Level_2. The data sent to the Bank is 7 bits, used as the memory access address for the write operation. This 7-bit data is the address offset obtained by decoding the real address corresponding to the index information in Reg_wr_level_0, i.e., the physical block number, and is no longer the 4-bit index information stored in Reg_wr_level_0. Each register in Reg_wr_level_0 has a corresponding Valid bit. If the Valid bit is 1, it indicates that the information in that register is valid and needs to be mapped to the Bank for write operation. Similarly, the smaller the register number in Reg_wr_level_0, the higher the priority. Furthermore, regardless of whether it is group 0 or group 1 of Reg_wr_level_0, when data is sent to the Bank, all data in that group will be shifted forward by one register position. When all data in group 0 has been sent to the Bank for write operation, group 1 begins mapping.

[0030] 3.4.3) During the write operation of Reg_wr_level_0 mapped to the Bank, it is necessary to simultaneously determine the number of remaining valid information in Reg_wr_level_0 of all 8 Banks to decide whether to pause the pipeline or send a new wrena signal. If the number of remaining valid information in Reg_wr_level_0 of each of the 8 Banks is less than or equal to 1, a wrena signal needs to be sent to the outside world, indicating that all data in Reg_wr_level_0 will be sent to the Bank in the next cycle, the pipeline resumes operation, and a new set of write addresses needs to be sent to the system to start mapping. If the number of remaining valid information in Reg_wr_level_0 of any Bank is greater than 1, the pipeline continues to pause until the condition is met.

[0031] In the conflict detection and queuing method for unified coloring graphics processor shared register file grouping mapping provided by this invention, the physical storage unit is divided into 8 banks. Each warp is allocated 16 read operand addresses and 8 write operand addresses for operand collection. These 16 read operand addresses and 8 write operand addresses are decoded and mapped to the 8 banks. Each bank has 2 read address interfaces and 1 write address interface, and can accept a maximum of 2 read operand addresses and 1 write operand address simultaneously. If, after the decoding operation, more than 2 read operand addresses or more than 1 write operand address are mapped to the same bank, a bank conflict will occur. Therefore, read and write operand addresses pointing to the same bank must be reasonably distributed through a conflict detection and queuing mechanism to enter the bank for reading and writing data in batches. We first tried pure hardware and hardware / software combined mapping schemes without pipeline. Finding that none of the previous methods could meet the design goals, this invention proposes a hierarchical grouped address mapping scheme for establishing a pipeline. It details the grouped mapping principle and implementation method for read / write operand addresses, the read / write pipeline pause control conditions, and read operand reordering. The mapping logic relationship at each level is described precisely down to the gate level. Verification shows that the allocation and release logic at each level, as well as the number of operands that the operand collection unit can provide and receive in the absence of Bank conflicts, all meet the design specifications.

[0032] This invention also employs a hierarchical grouped address mapping method to establish a pipeline. This involves grouping the 16 read and 8 write operand addresses into groups and establishing a pipeline for mapping. Read and write operations are performed separately, with read operations requiring three levels of grouping mapping and write operations requiring only two. We grouped the 16 read and 8 write operand addresses into groups of four, defining the priority of each register group in the read-write mapping operation. Based on the priority relationships, we analyzed the mapping pattern and compiled a truth table. Furthermore, based on the truth table, we derived its logical expression and drew the combinational logic diagram for each level. In addition, based on the pipeline performance, we analyzed the generation method of valid read / write signals during the read-write mapping process and derived the combinational logic formula through its truth table, further obtaining its combinational logic diagram. For read operations, the order of the 16 read addresses may be disrupted after passing through the register request and allocation unit in the conflict detection section. For example, read addresses addr_r_2, addr_r_8, and addr_r_9 are mapped to the same bank. In our design, addr_r_8 and addr_r_9 belong to group 0, while addr_r_2 belongs to group 1. Therefore, addr_r_8 and addr_r_9 will first pass through the conflict detection module and be mapped to the corresponding bank, performing read operations and obtaining read operands data 8 and data 9. However, at this point, there is no information indicating that these two data points should be output as data 8 and data 9. Therefore, the read operands obtained through the conflict detection logic need to pass through a reorder unit to finally obtain the correctly ordered read data dou 0–dout 15. Therefore, we set up an additional register, Reg_rd_level_2, to store the address index information and its validity signal. With this design, in the same clock cycle when read operands are obtained from the Bank, the index information and validity value related to these two read operands are stored in Reg_rd_level_2. In the next clock cycle, the read operands from port a and port b are output according to their corresponding index information in Reg_rd_level_2. For example, if the data stored in reg_r_b0_l2_0 is 4'b1000, and valid_r_b0_l2_0 is valid, then the data read from port a of the Bank is output as data 8; if the data stored in reg_r_b0_l2_1 is 4'b1001, and valid_r_b0_l2_1 is valid, then the data read from port b of the Bank is output as data 9. This achieves reordering of read operands, while write operations do not require reordering.

[0033] Therefore, this invention analyzes the traditional graphics processor register scheduling strategy, and based on domestic dedicated graphics processors, explores the design of a unified color array shared register file suitable for domestic technical levels, and invents a technology for accessing register files, providing a conflict detection and queuing mechanism to solve the bank conflict problem that may occur in actual transmission. Attached Figure Description

[0034] Figure 1 This is the overall flow chart for the read operation of this invention;

[0035] Figure 2 The valid_i_bj of the read operation Group_0 in this invention is mapped to the combinational logic diagram of Reg_rd_level_0;

[0036] Figure 3 Generate a combinational logic diagram of the selection control signal for Allocate_r_b0_l0_0 of this invention;

[0037] Figure 4 Generate a combinational logic diagram of the selection control signal for Allocate_r_b0_0_1 in this invention;

[0038] Figure 5 Generate a combinational logic diagram of the selection control signal for Allocate_r_b0_l0_2 of the present invention;

[0039] Figure 6 This is the logical diagram of the read operation Reg_rd_level_0 mapping to the first level of Reg_rd_level_1 in this invention;

[0040] Figure 7 Generate a combinational logic diagram of the selection control signal for Allocate_r_b0_l1_3 of this invention;

[0041] Figure 8 This is the logical diagram for mapping the read operation Reg_rd_level_1 to Reg_rd_level_2 in this invention;

[0042] Figure 9 Generate a combinational logic diagram for rdena for this invention;

[0043] Figure 10 This is the overall workflow for writing operations in this invention;

[0044] Figure 11 This is the logical diagram of Reg_wr_level_0 mapping to Bank in this invention;

[0045] Figure 12 Generate a combinational logic diagram for wrena for this invention. Detailed Implementation

[0046] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] This invention primarily addresses the access process of register files, providing a conflict detection and queuing method for unified coloring graphics processor shared register file group mapping to resolve bank conflicts that may occur during actual transmission. After trying various schemes, this invention ultimately designs a hierarchical group address mapping scheme for establishing a pipeline. The following sections will detail the group mapping principle and implementation method of its read / write operand addresses, read / write pipeline pause control conditions, read operand reordering, etc., and describe the mapping logic relationship of each level down to the gate level.

[0048] See Figure 1 The overall process of establishing the pipelined group mapping read operation is as follows: First, divide the 16 read addresses into 4 groups, where addr_0, addr_1, addr_8, and addr_9 belong to group_0; addr_2, addr_3, addr_10, and addr_11 belong to group_1; addr_4, addr_5, addr_12, and addr_13 belong to group_2; and addr_6, addr_7, addr_14, and addr_15 belong to group_3. Each address passes through a decoding unit, which decodes it to obtain the corresponding Bank and generates a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 read valid information register group Reg_rd_level_0. The data stored in Reg_rd_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the level 1 read valid information register group Reg_rd_level_1. The data stored in Reg_rd_level_1 then passes through the last mapping module Allocate_Logic_2 and is sent to the Bank for read operations. Simultaneously, it is temporarily stored in the level 2 read valid information register group Reg_rd_level_2 for read operand reordering. The number of remaining address information in Reg_rd_level_1 is also checked to determine whether the pipeline should pause or send a new rdena signal. Finally, the addresses in Reg_rd_level_2 are sent to the Bank for the appropriate operation.

[0049] The 3-bit Bank determination bits in the 16 read operand addresses are decoded to obtain the corresponding Bank number and generate a valid signal `valid_i_bj`, where `i` represents the address number and `j` represents the Bank number. Each address `i` has a connection mapped to all Banks. Each Group contains 4 `valid_i_bj` values. The validity of the read address is determined based on the value of `valid_i_bj`, and the result is mapped to the four registers of `Reg_rd_level_0`, generating the corresponding valid signal. Smaller address numbers have higher priority. Taking Group_0 of Bank_0 as an example, `addr_0` has the highest priority, and `addr_9` has the lowest. These are stored in the four registers of Group_0 of `Reg_rd_level_0` according to priority. This provides a combinational logic diagram of the mapping from address decoding information to `Reg_rd_level_0`, as shown in the attached diagram for Group_0 of Bank 0. Figure 2 As shown in the figure. The boxes are used to generate the selection control signals for writing to the relevant registers of group 0 in Reg_rd_level_0, sending the valid value and address information to the corresponding positions in Reg_rd_level_0. The combinational logic diagram for generating the selection control signals based on Allocata_r_b0_l0_0 is attached. Figure 3 As shown. Similar to Allocata_r_b0_l0_0, the combinational logic diagram for generating the selection control signal based on Allocata_r_b0_l0_1 is attached. Figure 4 As shown. Similar to Allocata_r_b0_l0_0 and Allocata_r_b0_l0_1, the combinational logic diagram for generating the selection control signal through Allocata_r_b0_l0_2 is attached. Figure 5 As shown. The logic of Allocata_r_b0_l0_3 is relatively simple, and its combinational logic diagram will not be shown here.

[0050] Data stored in register group Reg_rd_level_0 will be sent to Reg_rd_level_1 after passing through another mapping module, Allocate_Logic_Level_1. Reg_rd_level_1 is divided into two groups, each containing eight 4-bit registers and their valid signal (valid), used to store the corresponding address information sent from the previous level. Each register in Reg_rd_level_0 has a corresponding valid bit. If the valid bit is 1, it indicates that the information in that register is valid and needs to be mapped to Reg_rd_level_1; if it is 0, it is invalid and does not need to be mapped. When information in Reg_rd_level_0 is mapped to a register in Reg_rd_level_1, the valid bit of the corresponding register in Reg_rd_level_1 is set to 1. Similarly, in Reg_rd_level_0, the smaller the register number, the higher the priority. From this, we can obtain the mapping logic diagram from Reg_rd_level_0 to Reg_rd_level_1, i.e., attached... Figure 1 In Allocate_Logic_1, taking group 0 and group 1 as examples, see attached... Figure 6 As shown in the figure, boxes Allocata_r_b0_l1_0–Allocata_r_b0_l1_7 are used to generate selection control signals for writing to the relevant registers in the first group of Reg_rd_level_1, and to send the valid value and address information to the corresponding positions in Reg_rd_level_1. Among them, Allocata_r_b0_l1_0, Allocata_r_b0_l1_6 and Allocata_r_b0_l0_2 have the same structure; Allocata_r_b0_l1_1, Allocata_r_b0_l1_5 and Allocata_r_b0_l0_1 have the same structure; Allocata_r_b0_l1_2, Allocata_r_b0_l1_4 and Allocata_r_b0_l0_0 have the same structure; Allocata_r_b0_l1_7 and Allocata_r_b0_l0_3 have the same structure, and the combinational logic diagram of Allocata_r_b0_l1_3 is attached. Figure 7 As shown.

[0051] The data in Reg_rd_level_1 is sent to the Bank and Reg_rd_level_2 after passing through the last mapping module, Allocate_Logic_Level_2. The data sent to the Bank is 7 bits, used as the memory access address for read operations. This 7-bit data is the address offset decoded from the physical address corresponding to the address information in Reg_rd_level_1, i.e., the physical block number, and is no longer the 4-bit index information stored in the previous two levels. The data sent to Reg_rd_level_2 is still the 4-bit index information representing the read address number, used for read operand reordering. The mapping relationship between the two is exactly the same; Reg_rd_level_2 will be used as an example. Reg_rd_level_2 contains two 4-bit registers and a valid signal (valid), used to store the address information sent from Reg_rd_level_1. Each register in Reg_rd_level_1 has a corresponding valid bit; if the valid bit is 1, it indicates that the information in that register is valid and needs to be mapped to Reg_rd_level_2. When information from Reg_rd_level_1 is mapped to a register in Reg_rd_level_2, the Valid register in the corresponding register in Reg_rd_level_2 is set to 1. Similarly, in Reg_rd_level_1, smaller register numbers have higher priority. Furthermore, regardless of whether it's the first or second group of Reg_rd_level_1, when data is sent to Reg_rd_level_2, all data in that group will be shifted forward by the corresponding number of registers. Mapping begins for the second group only when all data in the first group of Reg_rd_level_1 has been sent to Reg_rd_level_2. Therefore, in practice, only valid data stored in registers Reg_b0_l1_0, Reg_b0_l1_1, Reg_b0_l1_8, and Reg_b0_l1_9 needs to be sent to Reg_rd_level_2; all other data will be stored in these registers from other registers. This yields the mapping from Reg_rd_level_1 to Reg_rd_level_2, i.e., Allocate_Logic_2. Taking Bank_0 as an example, see attached diagram. Figure 8As shown in the figure, boxes Allocata_r_b0_l2_0 and Allocata_r_b0_l2_1 are used to generate selection control signals for writing to relevant registers in Reg_rd_level_2. Specifically, Allocata_r_b0_l2_0 and Allocata_r_b0_l0_2 have the same structure; Allocata_r_b0_l2_1 and Allocata_r_b0_l0_1 have the same structure.

[0052] During the mapping from Reg_rd_level_1 to Reg_rd_level_2, it's necessary to simultaneously determine the remaining valid information in Reg_rd_level_1 across all eight banks. This determination is used to decide whether to pause the pipeline or send a new rdena signal. If the remaining valid information in Reg_rd_level_1 of each of the eight banks is less than or equal to 2, an rdena signal needs to be sent to the outside world, indicating that all data in Reg_rd_level_1 will be sent to the bank in the next cycle, the pipeline resumes operation, and a new set of read addresses needs to be sent to the system to begin mapping. If the remaining valid information in Reg_rd_level_1 of any bank is greater than 2, the pipeline continues to pause until the condition is met. To achieve this, we check the valid signals of the first three registers in each of the two groups in Reg_rd_level_1 of each bank. When less than or equal to 2 of the 6 valid signals in each group are valid, rdena is set to 1; otherwise, it is set to 0. The combinational logic diagram corresponding to the above mapping relationship is attached. Figure 9 As shown.

[0053] Because the order of the 16 read addresses may be disrupted after passing through the register request and allocation unit in the conflict detection section, the read operands obtained through the conflict detection logic need to pass through a reordering unit (ReorderUnit) to finally obtain the correctly ordered read data dou 0–dout 15. Simultaneously with the data mapping from Reg_rd_level_1 to the Bank, a register Reg_rd_level_2 is set up to store the address index information and its valid signals. Reg_rd_level_2 has a depth of 2, storing the index information of one or two read addresses per cycle. The valid_r_b0_l2_0 and valid_r_b0_l2_1 sent from Allocate_Logic_Level_2 serve as valid signals for read operations on the two ports of the Bank, and are also stored in Reg_rd_level_2 as valid signals for reg_r_b0_l2_0 and reg_r_b0_l2_1, respectively. Map valid_r_b0_l2_0 to port a of the Bank, and valid_r_b0_l2_1 to port b of the Bank. In the same cycle when the read operands are obtained from the Bank, the index information and valid value related to these two read operands are stored in Reg_rd_level_2. In the next cycle, the read operands of ports a and b are output according to their corresponding index information in Reg_rd_level_2. In this way, the reordering of read operands is achieved.

[0054] Since there are only 8 operand addresses for write operations, the mapping logic is much simpler than for read operations. Taking Bank0 as an example, the overall write operation flow is shown in the appendix. Figure 10As shown, similar to the read operation, we first divide the 8 write addresses into 2 groups: addr_0, addr_1, addr_4, and addr_5 belong to Group_0; addr_2, addr_3, addr_6, and addr_7 belong to Group_1. Each write address first passes through a decoding unit to obtain the corresponding Bank and generate a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 write valid information register group Reg_wr_level_0. The data stored in Reg_wr_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the Bank for the write operation. At the same time, it is necessary to determine the number of remaining address information in Reg_rd_level_0 in all 8 Banks to decide whether to pause the write pipeline or send a new wrena signal. Write operations do not involve data reordering steps like read operations, so there is no register at the last level where the index is stored as in read operations. Since write operations only have 8 addresses, they only need to be divided into 2 groups, and queuing and conflict scheduling of write addresses can be performed at level 0. Therefore, in the entire conflict detection and allocation process of write operations, only the Reg_wr_level_0 register is used.

[0055] Similar to the read operation, the 3-bit Bank determination bits in the address information of the 8 write operands are decoded to obtain the Bank corresponding to the address and generate a valid signal valid_i_bj, where i represents the address number and j represents the Bank number. Each address i has a connection mapped to all Banks. For a given address, when the decoding result maps to a certain Bank, the valid_i_bj corresponding to that Bank is set to 1, and the valid_i_bj corresponding to the other 7 Banks is set to 0. The mapping logic is the same as the mapping logic from the address decoding information to Reg_rd_level_0 in the read operation.

[0056] During a write operation, the write address index information stored in Reg_wr_level_0 is sent to the Bank for write operation after passing through the second mapping module Allocate_Logic_Level_2. The data sent to the Bank is 7 bits, used as the memory access address for the write operation. This 7-bit data is the address offset obtained by decoding the real address corresponding to the index information in Reg_wr_level_0, i.e., the physical block number, and is no longer the 4-bit index information stored in Reg_wr_level_0. Each register in Reg_wr_level_0 has a corresponding Valid bit. If the Valid bit is 1, it indicates that the information in that register is valid and needs to be mapped to the Bank for write operation. Similarly, smaller register numbers in Reg_wr_level_0 have higher priority. Furthermore, regardless of whether it's group 0 or group 1 of Reg_wr_level_0, when data is sent to the Bank, all data in that group will be shifted forward by one register position. When all data in group 0 has been sent to the Bank for write operation, group 1 begins mapping. Therefore, in actual operation, only the valid data stored in registers Reg_b0_l0_0 and Reg_b0_l0_4 needs to be sent to the Bank; all other data will be stored from other registers into these registers. This can be seen in the attached diagram. Figure 11 The diagram shown illustrates the logical mapping of Reg_wr_level_0 to the Bank.

[0057] During the write operation mapping from Reg_wr_level_0 to the Bank, it is necessary to simultaneously determine the remaining valid information in Reg_wr_level_0 across all eight Banks. This determination is used to decide whether to pause the pipeline or send a new wrena signal. If the remaining valid information in Reg_wr_level_0 of each of the eight Banks is less than or equal to 1, a wrena signal needs to be sent to the outside world, indicating that all data in Reg_wr_level_0 will be sent to the Bank in the next cycle, the pipeline resumes operation, and a new set of write addresses needs to be sent to the system to begin mapping. If the remaining valid information in Reg_wr_level_0 of any Bank is greater than 1, the pipeline continues to pause until the condition is met. To achieve this, the valid signals of the first two registers of each of the two groups in Reg_wr_level_0 of each Bank need to be checked. If less than or equal to one of these four valid signals is valid, wrena_0 is set to 1; otherwise, it is set to 0. The combinational logic corresponding to the above mapping relationship is shown in the appendix. Figure 12 As shown.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A conflict detection and queuing method for unified coloring graphics processor shared register file grouping mapping, characterized in that: The method includes the following steps: 1) The physical storage unit is divided into 8 banks. Each warp is allocated 16 read operand addresses and 8 write operand addresses for operand collection. These 16 read operand addresses and 8 write operand addresses are decoded and mapped to the 8 banks. Each bank has 2 read address interfaces and 1 write address interface, and can accept a maximum of 2 read operand addresses and 1 write operand address at the same time. 2) A hierarchical grouping address mapping method is adopted, which involves grouping the 16 read operand addresses and 8 write operand addresses of each group and establishing a pipeline for mapping; 2.1) The 16 read operand addresses and 8 write operand addresses were grouped into groups of 4, and the priority of each register group in the read-write mapping operation was specified. 2.2) The mapping pattern was analyzed based on the priority relationship and a truth table was listed. The logical expression was further derived based on the truth table and the mapping combinational logic diagram of each level was drawn. 2.3) Based on the performance of the pipeline, the generation method of the valid read and write signals during the write operation mapping process was analyzed, and the combinational logic formula was derived through its truth table, and its combinational logic diagram was further obtained. 2.4) Separate read and write operations, where read operations require three levels of grouping mapping, while write operations only require two levels of grouping mapping; The read operation in step 2) follows the following procedure: 3.1) First, divide the 16 read operand addresses into 4 groups, where addr_0, addr_1, addr_8, and addr_9 belong to group_0; addr_2, addr_3, addr_10, and addr_11 belong to group_1; addr_4, addr_5, addr_12, and addr_13 belong to group_2; and addr_6, addr_7, addr_14, and addr_15 belong to group_3. 3.2) Each address passes through a decoding unit, which decodes it to obtain the corresponding Bank and generates a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 read valid information register group Reg_rd_level_0. The data stored in Reg_rd_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the level 1 read valid information register group Reg_rd_level_1. The data stored in Reg_rd_level_1 then passes through the last mapping module Allocate_Logic_2 and is sent to the Bank for read operation. At the same time, it is temporarily stored in the level 2 read valid information register group Reg_rd_level_2 for read operand reordering. Simultaneously, the number of remaining address information in Reg_rd_level_1 needs to be determined to decide whether to pause the pipeline or send a new rdena signal. Finally, the addresses in Reg_rd_level_2 are sent to the Bank for the corresponding operation. 3.2.1) Decode the 3-bit Bank judgment bits in the 16 read operand addresses to obtain the Bank number corresponding to the address and generate a valid signal valid_i_bj, where i represents the address number and j represents the Bank number; 3.2.2) Each address i has a connection mapped to all banks; each group contains 4 valid_i_bj, and the validity of the read address is determined based on the value of valid_i_bj, and mapped to the 4 registers of Reg_rd_level_0 to generate the corresponding valid signal; it is stipulated that the smaller the address number, the higher the priority; 3.2.3) The data stored in register group Reg_rd_level_0 will be sent to Reg_rd_level_1 after passing through another mapping module, Allocate_Logic_Level_1. Reg_rd_level_1 is divided into two groups, each containing eight 4-bit registers and their valid signal, which are used to store the corresponding address information sent from the previous level. Each register in Reg_rd_level_0 has a corresponding valid bit. If the valid bit is 1, it means that the information in the register is valid and needs to be mapped to Reg_rd_level_1. If it is 0, it is invalid and does not need to be mapped. When information in Reg_rd_level_0 is mapped to a register in Reg_rd_level_1, the valid bit of the corresponding register in Reg_rd_level_1 is set to 1. 3.2.4) The data in Reg_rd_level_1 is sent to Bank and Reg_rd_level_2 after passing through the last mapping module Allocate_Logic_Level_2. The data sent to Bank is 7 bits, which is used as the memory access address for reading operations. This 7-bit data is the address offset decoded from the real address corresponding to the address information in Reg_rd_level_1, i.e., the physical block number, and is no longer the 4-bit index information stored in the previous two levels. The data sent to Reg_rd_level_2 is still the 4-bit index information representing the read address number, used for reordering read operations. 3.2.5) During the mapping from Reg_rd_level_1 to Reg_rd_level_2, it is necessary to simultaneously determine the remaining valid information in Reg_rd_level_1 across all 8 banks. This determination is used to decide whether to pause the pipeline or send a new rdena signal. If the remaining valid information in Reg_rd_level_1 of each of the 8 banks is less than or equal to 2, an rdena signal needs to be sent to the outside world, indicating that all data in Reg_rd_level_1 will be sent to the bank in the next cycle, the pipeline resumes operation, and a new set of read addresses needs to be sent to the system to begin mapping. If the remaining valid information in Reg_rd_level_1 of any bank is greater than 2, the pipeline continues to pause until the condition is met.

2. The conflict detection and queuing method for unified coloring graphics processor shared register file grouping mapping according to claim 1, characterized in that: The specific process for the write operation in step 2) is as follows: 3.3) First, divide the 8 write operand addresses into 2 groups, where addr_0, addr_1, addr_4, and addr_5 belong to Group_0; and addr_2, addr_3, addr_6, and addr_7 belong to Group_1. 3.4) Each write address first passes through a decoding unit to obtain the corresponding Bank and generate a valid signal. These valid signals pass through a mapping module Allocate_Logic_0 and are then sent to the level 0 write valid information register group Reg_wr_level_0. The data stored in Reg_wr_level_0 then passes through another mapping module Allocate_Logic_1 and is sent to the Bank for write operation. At the same time, it is necessary to determine the number of remaining address information in Reg_rd_level_0 in all 8 Banks to decide whether to pause the write pipeline or send a new wrena signal.

3. The conflict detection and queuing method for unified coloring graphics processor shared register file grouping mapping according to claim 2, characterized in that: the specific steps of step 3.4) are as follows: 3.4.1) By decoding the 3-bit Bank judgment bits in the address information of the 8 write operands, the Bank corresponding to the address is obtained and a valid signal valid_i_bj is generated, where i represents the address number and j represents the Bank number; each address i has a connection mapped to all Banks. For a certain address, when the decoding result is mapped to a certain Bank, valid_i_bj corresponding to that Bank is set to 1, and valid_i_bj corresponding to the other 7 Banks is set to 0; its mapping logic is the same as the mapping logic of address decoding information to Reg_rd_level_0 in the read operation; 3.4.2) During a write operation, the write address index information stored in Reg_wr_level_0 is sent to the Bank for write operation after passing through the second mapping module Allocate_Logic_Level_2. The data sent to the Bank is 7 bits, used as the memory access address for the write operation. This 7-bit data is the address offset obtained by decoding the real address corresponding to the index information in Reg_wr_level_0, i.e., the physical block number, and is no longer the 4-bit index information stored in Reg_wr_level_0. Each register in Reg_wr_level_0 has a corresponding Valid bit. If the Valid bit is 1, it indicates that the information in that register is valid and needs to be mapped to the Bank for write operation. Similarly, it is stipulated that the smaller the register number in Reg_wr_level_0, the higher the priority. Furthermore, regardless of whether it is group 0 or group 1 of Reg_wr_level_0, when data is sent to the Bank, all data in that group will be shifted forward by one register position. When all data in group 0 has been sent to the Bank for write operation, group 1 begins mapping. 3.4.3) During the write operation of Reg_wr_level_0 mapped to the Bank, it is necessary to simultaneously determine the number of remaining valid information in Reg_wr_level_0 of all 8 Banks to decide whether to pause the pipeline or send a new wrena signal. If the number of remaining valid information in Reg_wr_level_0 of each of the 8 Banks is less than or equal to 1, a wrena signal needs to be sent to the outside world, indicating that all data in Reg_wr_level_0 will be sent to the Bank in the next cycle, the pipeline resumes operation, and a new set of write addresses needs to be sent to the system to start mapping. If the number of remaining valid information in Reg_wr_level_0 of any Bank is greater than 1, the pipeline continues to pause until the condition is met.

Images