Semiconductor device and method for manufacturing the same

Abstract

The semiconductor structure and manufacturing method provided by the present invention, when the second metal layer is etched using the mask layer as a mask, when the second opening formed in the second metal layer reaches a predetermined depth, a removal process is performed on the second metal layer to remove at least a portion of the residues located on the side wall of the second opening, thereby avoiding the eventual connection of adjacent gate lines of the first metal layer and the second metal layer grooves, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As people's living standards improve, electronic products are used more and more widely, and various semiconductor products are usually used in electronic products. With the development of science and technology and the increase in people's needs, people's performance requirements for semiconductor products are also getting higher and higher.

[0003] Bi-CMOS structure is a commonly used semiconductor structure, and it is necessary to improve the performance of Bi-CMOS products. According to research by technicians, in the process of preparing Bi-CMOS products, the polysilicon layer containing the tungsten layer is not etched cleanly, which may cause the adjacent gate lines to be connected in serious cases. This results in the performance of the Bi-CMOS structure being reduced. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem that adjacent gate lines of the existing semiconductor structure are connected, resulting in reduced performance of the semiconductor structure.

[0005] In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] providing a substrate;

[0007] forming a first metal layer, a second metal layer and a mask layer in sequence on the substrate, wherein the mask layer has a first opening;

[0008] Using the mask layer as a mask, performing a first etching process on the second metal layer, so that the first opening extends to the second metal layer to form a second opening, wherein during the first etching process, a residue is formed at least on a sidewall of the second opening;

[0009] When the depth of the second opening reaches a predetermined depth, performing a removal process on the second metal layer to remove at least part of the residue;

[0010] Using the mask layer as a mask, a second etching process is performed on the second metal layer to enlarge the second opening and extend the second opening to the top surface of the first metal layer.

[0011] Optionally, the ratio of the predetermined depth to the thickness of the second metal layer is in a range of 1 / 2 to 2 / 3.

[0012] Optionally, the gas of the removal process includes: oxygen and carbon tetrafluoride.

[0013] Optionally, the flow rate of the oxygen is 60 SCCM to 100 SCCM, and the flow rate of the carbon tetrafluoride is 5 SCCM to 15 SCCM.

[0014] Optionally, the pressure when performing the removal process is: 0W~20W.

[0015] Optionally, the second etching process includes: a main etching process and an over-etching process, and the method of performing the second etching process on the second metal layer includes:

[0016] A main etching process and an over-etching process are sequentially performed on the second metal layer, wherein the etching gas of the main etching process and the over-etching process is the same, but the gas flow ratios are different.

[0017] Optionally, the etching gas of the first etching process and the main etching process is the same, and the gas flow ratio is the same.

[0018] Optionally, etching gases of the first etching process and the second etching process are: chlorine, nitrogen trifluoride and oxygen.

[0019] Optionally, during the execution of the first etching process and the second etching process, a protective gas is also introduced.

[0020] In order to solve the above problems, the present invention further provides a semiconductor structure, wherein the semiconductor structure is manufactured according to any one of the above-mentioned methods for manufacturing a semiconductor structure.

[0021] A semiconductor structure and manufacturing method of the present invention, when etching the second metal layer with a mask layer as a mask, when the second opening formed in the second metal layer reaches a predetermined depth, a removal process is performed on the second metal layer to remove at least a portion of the residue located on the side wall of the second opening, thereby avoiding the eventual connection of adjacent gate lines of the first metal layer and the second metal layer grooves, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present invention;

[0023] Figure 2 to Figure 7 is a structural schematic diagram of a method for manufacturing a semiconductor structure in one embodiment of the present invention;

[0024] The reference numerals are as follows:

[0025] 1- substrate;

[0026] 2- Oxide layer;

[0027] 3- first metal layer;

[0028] 4- second metal layer;

[0029] 5-mask layer; 50-mask material layer;

[0030] 6-anti-reflection layer; 60-anti-reflection material layer;

[0031] 7- photoresist layer;

[0032] 8- Residue;

[0033] A-slotting;

[0034] B-first opening;

[0035] C-second opening;

[0036] D-Third opening. DETAILED DESCRIPTION

[0037] The following is a further detailed description of a semiconductor structure and a manufacturing method thereof proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. The core idea of ​​the present invention is that when the second metal layer is etched using the mask layer as a mask, when the second opening formed in the second metal layer reaches a predetermined depth, a removal process is performed on the second metal layer to remove at least part of the residue on the sidewall of the second opening, thereby avoiding the final connection of adjacent gate lines of the first metal layer and the second metal layer grooves to improve the performance of the semiconductor structure.

[0038] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present invention; Figure 2 to Figure 7 1 is a schematic diagram of a method for manufacturing a semiconductor structure in an embodiment of the present invention; Figure 1 to Figure 7 The manufacturing method of the semiconductor structure in this embodiment is described. The manufacturing method of the semiconductor structure described below does not deviate from the above core concept.

[0039] In step S10, Figure 1 Combined with Figure 2 As shown, a substrate 1 is provided.

[0040] In this embodiment, the substrate 1 may include semiconductor materials, insulating materials, conductive materials or any combination thereof, and may be a single-layer structure or a multi-layer structure. Therefore, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. It may also include a layered substrate such as, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0041] In step S20, continue to Figure 1 Combined with Figure 3 As shown, a first metal layer 3, a second metal layer 4 and a mask layer 5 are sequentially formed on the substrate 1, and the mask layer 5 has a first opening B. In this embodiment, the material forming the first metal layer 3 is polysilicon, and the material forming the second metal layer 4 is tungsten silicide. And the material forming the mask layer 5 is silicon nitride. In addition, in other embodiments, the method of forming the first metal layer 3 and the second metal layer 4 is physical vapor deposition.

[0042] In addition, in this embodiment, before forming the first metal layer 3, the method further comprises forming an oxide layer 2, wherein the material forming the oxide layer 2 is silicon oxide. And the method of forming the oxide layer 2 comprises: chemical vapor deposition method.

[0043] Further, see Figure 2 Combined with Figure 3 As shown, in this embodiment, the method for forming the mask layer 5 includes the following steps 1 and 2.

[0044] In step one, refer to Figure 2 As shown, a mask material layer 50 , an anti-reflection material layer 60 and a photoresist layer 7 are sequentially formed on the second metal layer 4 , wherein the photoresist layer 7 has a groove A therein.

[0045] In step 2, using the photoresist layer 7 as a mask, the anti-reflection material layer 60 and the mask material layer 50 are etched in sequence to form an anti-reflection layer 6 and the mask layer 5, and the groove A is extended into the mask layer 5 to form a first opening B in the mask layer 5.

[0046] In this embodiment, the photoresist layer 7 may be a positive photoresist or a negative photoresist. The positive and negative properties of the photoresist layer 7 are not specifically limited here and are subject to actual conditions.

[0047] And, Figure 3 Combined with Figure 4As shown, after forming the mask layer 5, the method further includes: removing the photoresist layer 7 and the anti-reflection layer 6. In the present embodiment, the method for removing the photoresist layer 7 and the anti-reflection layer 6 includes: performing an ashing process on the photoresist layer 7 and the anti-reflection layer 6, i.e., introducing oxygen to remove the photoresist layer 7 and the anti-reflection layer 6 by an oxygen burning method.

[0048] In step S20, Figure 1 Combined with Figure 4 and Figure 5 As shown, the mask layer 5 is used as a mask to perform a first etching process on the second metal layer 4 so that the first opening B extends to the second metal layer 4 to form a second opening C, wherein during the first etching process, residues 8 are formed at least on the side walls of the second opening C.

[0049] In this embodiment, when the first etching process is performed on the second metal layer 4, i.e., the tungsten silicide layer, a polymer containing tungsten is formed, and the polymer at least remains on the sidewall of the second opening C to form a residue 8. The residue 8 may also be formed at the bottom of the second opening C. When the residue 8 is formed at the bottom of the second opening C, subsequent etching will be difficult. In addition, the residue 8 will cause adjacent gate lines of the finally formed semiconductor structure to be connected, thus causing the performance of the semiconductor structure to deteriorate.

[0050] In step S30, continue to Figure 3 Combined with Figure 4 As shown, when the depth of the second opening C reaches a predetermined depth, a removal process is performed on the second metal layer 4 to remove at least a portion of the residue 8 .

[0051] In this embodiment, when the second metal layer 4 is etched using the mask layer 5 as a mask, when the second opening C formed in the second metal layer 4 reaches a predetermined depth, a removal process is performed on the second metal layer 4 to remove at least a portion of the residue 8 located on the side wall of the second opening C, thereby avoiding the eventual connection of adjacent gate lines of the grooves of the first metal layer 3 and the second metal layer 4, thereby improving the performance of the semiconductor structure.

[0052] In this embodiment, the ratio of the predetermined depth to the thickness of the second metal layer 4 is in the range of 1 / 2 to 2 / 3. That is, when the depth of the second opening C reaches 1 / 2 to 2 / 3 of the thickness of the second metal layer 4, the removal process is performed to remove at least part of the residue 8.

[0053] Wherein, in this embodiment, the gas of the removal process includes: oxygen and carbon tetrafluoride. The flow rate of the oxygen is: 60SCCM~100SCCM, and the flow rate of the carbon tetrafluoride is: 5SCCM~15SCCM. The pressure when performing the removal process is: 0W~20W. In this embodiment, under the conditions of the above-mentioned removal process, oxygen can react with the residue 8 formed by the polymer containing C and CH, thereby removing the residue 8. In addition, in this embodiment, the time for performing the removal process is 8s, and the power of the removal process is 500W.

[0054] In step S40, combining Figure 5 And participate Figure 6 As shown, with the mask layer 5 as a mask, a second etching process is performed on the second metal layer 4 to enlarge the second opening C, and extend the second opening C to the top surface of the first metal layer 3. In this embodiment, the first etching process and the second etching process are dry etching, and in an optional embodiment, the first etching process and the second etching process can also be wet etching.

[0055] In this embodiment, the second etching process includes: a main etching process and an over-etching process, and a method of performing the second etching process on the second metal layer 4 includes:

[0056] The main etching process and the over-etching process are sequentially performed on the second metal layer 4, wherein the etching gas of the main etching process and the over-etching process is the same, and the gas flow ratio is different. That is, in this embodiment, the main etching process is performed on the second metal layer 4 to expand the second opening C. Afterwards, the over-etching process is continued to be performed on the second metal layer 4, so that the second opening C is completely opened, so that the second opening C is completely opened and stays on the top surface of the first metal layer 3.

[0057] Wherein, in this embodiment, the etching gas of the first etching process and the main etching process is the same, and the gas flow ratio is the same. In this embodiment, the etching gas of the first etching process and the main etching includes: chlorine, nitrogen trifluoride and oxygen. The gas flow rate of the chlorine is 80SCCM, the gas flow rate of the nitrogen trioxide is 80SCCM, and the gas flow rate of the oxygen is 10SCCM. And, the etching time of the first etching process and the main etching process is 15S, the pressure for executing the first etching process and the main etching process is: 75W, and the power for executing the first etching process and the main etching process is: 75W.

[0058] In addition, in this embodiment, the etching gas of the main etching process and the over-etching process is the same, and the gas flow ratio is different. Among them, the etching gas of the main etching process and the over-etching process includes: chlorine, nitrogen trifluoride and oxygen. In this embodiment, the gas flow rate of the over-etching chlorine is 20SCCM, the gas flow rate of the nitrogen trioxide is 80SCCM, and the gas flow rate of the oxygen is 10SCCM. The power of the over-etching process is 300W, the pressure is 75, and the time for executing the over-etching process is 15S.

[0059] In addition, in this embodiment, during the execution of the first etching process and the second etching process, a protective gas is introduced to protect the second metal layer 4 located on the side wall of the second opening C from being corroded during the execution of the first etching process and the second etching process, wherein the protective gas is nitrogen. Further, in this embodiment, the flow rate of the protective gas introduced during the execution of the first etching process and the main etching process is 15 SCCM, and during the execution of the over-etching process, the flow rate of the protective gas introduced is 45 SCCM.

[0060] Further, continue to participate Figure 6 Combined with Figure 7 As shown, after performing the second etching process, the method further includes: using the mask layer 5 as a mask, performing a third etching process on the first metal layer 3, so that the second opening C extends to the first metal layer 3 to form a third opening D. In this embodiment, the second metal layer 4 and the first metal layer 3 located on both sides of the second opening C and the third opening D respectively constitute two gates. In this embodiment, the third etching process is dry etching. In an optional embodiment, the third etching process can also be wet etching. The etching method of the third etching process is not specifically limited here, and is subject to actual conditions.

[0061] Furthermore, this embodiment also discloses a semiconductor structure, which is manufactured according to the semiconductor structure manufacturing method as described above.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; A first metal layer, a second metal layer and a mask layer are sequentially formed on the substrate, wherein the mask layer has a first opening, the second metal layer is formed of tungsten silicide, and the mask layer is formed of silicon nitride; Using the mask layer as a mask, performing a first etching process on the second metal layer, so that the first opening extends to the second metal layer to form a second opening, wherein during the first etching process, a residue is formed at least on a sidewall of the second opening; When the depth of the second opening reaches a predetermined depth, performing a removal process on the second metal layer to remove at least part of the residue, the power when performing the removal process is: 0W to 20W; Using the mask layer as a mask, performing a second etching process on the second metal layer to enlarge the second opening and extend the second opening to the top surface of the first metal layer; The second etching process includes: a main etching process and an over-etching process, and the method of performing the second etching process on the second metal layer includes: performing the main etching process and the over-etching process on the second metal layer in sequence, wherein the etching gas of the main etching process and the over-etching process is the same, but the gas flow ratio is different; After performing the second etching process, performing a third etching process on the first metal layer using the mask layer as a mask, so that the second opening extends to the first metal layer to form a third opening, wherein the second metal layer and the first metal layer located on both sides of the second opening and the third opening respectively constitute two gates; The etching gases of the first etching process and the second etching process are: chlorine, nitrogen trifluoride and oxygen.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The ratio of the predetermined depth to the thickness of the second metal layer is in the range of 1 / 2 to 2 / 3.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The gases used in the removal process include oxygen and carbon tetrafluoride.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The flow rate of the oxygen is 60 SCCM to 100 SCCM, and the flow rate of the carbon tetrafluoride is 5 SCCM to 15 SCCM.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The etching gas of the first etching process and the main etching process is the same, and the gas flow ratio is the same.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: During the execution of the first etching process and the second etching process, a protective gas is also introduced.

7. A semiconductor structure, characterized in that: The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure as claimed in any one of claims 1 to 6.

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