Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes: a plurality of display data lines arranged side by side, at least one first electrostatic discharge (ESD) line group, and a second ESD line group. In the side-by-side arrangement direction of the plurality of display data lines, the plurality of display data lines include at least one peripheral display data line and a plurality of non-peripheral display data lines. Each peripheral display data line is electrically connected to a corresponding first ESD line group; the second ESD line group is connected to the non-peripheral display data lines. With this structure, this application can ensure that the ESD protection function of the remaining display data lines is not affected when some display data lines suffer ESD damage.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to array substrates and display panels. Background Technology

[0002] Organic light-emitting diode (OLED) display devices are widely used in high-performance display fields due to their characteristics such as self-illumination, wide viewing angle, high luminous efficiency, low power consumption, fast response time, and good low-temperature characteristics.

[0003] Existing OLED display devices typically have electrostatic discharge (ESD) protection circuits on the substrate for the display data lines. However, during the screen manufacturing process, ESD discharge often causes ESD damage to the display data lines near the edge of the screen, resulting in abnormal display.

[0004] The current repair method usually involves disconnecting the electrostatic discharge traces. While this ensures that the display data lines can display normally, it renders all electrostatic protection circuits on the screen ineffective. Summary of the Invention

[0005] The main technical problem solved by this application is to provide an array substrate and display panel that can ensure the electrostatic protection function of the remaining display data lines is not affected when some display data lines are damaged by electrostatic discharge.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide an array substrate, including: a plurality of display data lines arranged side by side; in the side-by-side arrangement direction of the plurality of display data lines, the plurality of display data lines include at least one peripheral display data line and a plurality of non-peripheral display data lines; at least one first electrostatic discharge line group, each of the peripheral display data lines being electrically connected to a corresponding first electrostatic discharge line group; and a second electrostatic discharge line group connected to the non-peripheral display data lines.

[0007] The key feature of this application is that it provides independent electrostatic discharge circuits for peripheral display data lines that are prone to electrostatic damage and for non-peripheral display data lines that are not prone to electrostatic damage. Under normal circumstances, electrostatic discharge occurs through a first electrostatic discharge line group when the electrostatic charge generated at the front end of the peripheral display data line is released, while electrostatic charge generated at the front end of the non-peripheral display data line is released through a second electrostatic discharge line group. Even if electrostatic discharge at the front end causes electrostatic damage to any peripheral display data line, resulting in a display abnormality, it will not damage or affect the remaining normally displaying peripheral display data lines and their corresponding first electrostatic discharge line groups, as well as the non-peripheral display data lines and second electrostatic discharge line groups. The electrostatic protection circuits of all display data lines except for the peripheral display data line with the display abnormality can function normally.

[0008] Preferably, in response to electrostatic damage to any of the peripheral display data lines, the corresponding first electrostatic discharge line group is configured to enable the peripheral display data lines to perform normal display operations, and the second electrostatic discharge line group provides normal electrostatic protection for the non-peripheral display data lines.

[0009] Specifically, the electrostatic damage includes electrostatic short-circuit damage between any of the peripheral display data lines and the corresponding first electrostatic discharge line group during the manufacturing process of the array substrate.

[0010] Specifically, in response to the electrostatic short circuit damage occurring on any of the peripheral display data lines, the corresponding first electrostatic discharge line group is configured to have the same data voltage as the peripheral display data line that experienced the electrostatic short circuit damage.

[0011] When electrostatic discharge in the current segment causes electrostatic short circuit damage between the peripheral display data line and the first electrostatic discharge line group, the data voltage of the first electrostatic discharge line group is configured to be the same as the voltage of the damaged peripheral display data line, so as to ensure that the display of the peripheral display data line is normal and will not affect the display of other display data lines or electrostatic protection.

[0012] Preferably, the first electrostatic discharge line group is configured with a data voltage different from that of the corresponding peripheral display data line to provide electrostatic protection for the peripheral display data line.

[0013] In the normal state without electrostatic discharge, the data voltage of the first electrostatic discharge line group is different from the voltage of the corresponding peripheral display data line, making it impossible for the first electrostatic discharge line group to conduct with the peripheral display data line. Only when enough electrostatic charge accumulates on the peripheral display data line can the electrostatic charge be released from the corresponding first electrostatic discharge line group, ensuring the normal display of all display data lines and the normal operation of the electrostatic protection circuit in both the normal state and the electrostatic discharge state.

[0014] Preferably, the array substrate further includes a plurality of positive electrostatic discharge (ESD) switching units and a plurality of negative ESD switching units; the first ESD discharge line group includes a first positive ESD discharge line and a first negative ESD discharge line; one peripheral display data line is electrically connected to the first positive ESD discharge line through a corresponding positive ESD switching unit, and one peripheral display data line is electrically connected to the first negative ESD discharge line through a corresponding negative ESD switching unit; and / or, the second ESD discharge line group includes a second positive ESD discharge line and a second negative ESD discharge line; one non-peripheral display data line is electrically connected to the second positive ESD discharge line through a corresponding positive ESD switching unit, and one non-peripheral display data line is electrically connected to the second negative ESD discharge line through a corresponding negative ESD switching unit.

[0015] Specifically, the positive electrostatic discharge (ESD) switch unit includes an NMOS transistor, and the negative ESD switch unit includes a PMOS transistor; the first positive ESD discharge line has a voltage lower than that of the peripheral display data line electrically connected to it so that the positive ESD switch unit is turned on only during positive ESD discharge; the first negative ESD discharge line has a voltage higher than that of the peripheral display data line electrically connected to it so that the negative ESD switch unit is turned on only during negative ESD discharge.

[0016] Positive and negative electrostatic charges are released through different electrostatic discharge circuits. The NMOS transistor acts as the switch for the positive electrostatic charge discharge circuit, and the PMOS transistor acts as the switch for the negative electrostatic charge discharge circuit.

[0017] Preferably, a spare data line is also included, wherein the first electrostatic discharge line group is a spare data line.

[0018] The substrate is usually equipped with several idle spare data lines, which are located in the non-display area. Even if electrostatic damage occurs, the abnormal voltage of the spare data lines will not be displayed to the user. In addition, the voltage adjustment accuracy of the spare data lines is high, making it convenient to set the voltage.

[0019] Preferably, in the side-by-side arrangement direction, the peripheral display data line is composed of two edge display data lines arranged opposite to each other on both sides of the plurality of non-peripheral display data lines.

[0020] Specifically, the number of the first electrostatic discharge line group is two;

[0021] Specifically, the first electrostatic discharge line group is located on the side of the edge display data line that is electrically connected to it, away from the non-peripheral display data line.

[0022] The first electrostatic discharge line group is closest to the edge display data line, making wiring easier.

[0023] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display panel including any of the above-mentioned array substrates.

[0024] The beneficial effects of this application are as follows: Unlike the prior art, this application sets up independent electrostatic discharge circuits for peripheral display data lines that are prone to electrostatic damage and non-peripheral display data lines that are not prone to electrostatic damage. In the normal state without electrostatic discharge, the first electrostatic discharge line group cannot be connected to the peripheral display data lines. When electrostatic discharge occurs in the current segment, electrostatic charge is released from the corresponding first electrostatic discharge line group, ensuring the normal display of all display data lines in both the normal and electrostatic discharge states, as well as the normal operation of the electrostatic protection circuit. When electrostatic discharge in the current segment causes electrostatic damage to any peripheral display data line, resulting in a display abnormality, it will not damage or affect the remaining normally displaying peripheral display data lines and their corresponding first electrostatic discharge line groups, as well as the non-peripheral display data lines and the second electrostatic discharge line group. The electrostatic protection circuits of all display data lines except for the peripheral display data line with the display abnormality can work normally. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of one embodiment of the array substrate of this application;

[0026] Figure 2 This is a schematic diagram of the specific structure of one embodiment of the array substrate of this application;

[0027] Figure 3 This is a further detailed structural schematic diagram of an embodiment of the array substrate of this application;

[0028] Figure 4 This is a schematic diagram of another embodiment of the array substrate of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] See Figure 1 , Figure 1This is a schematic diagram of an embodiment of the array substrate 1 of this application. The array substrate 1 includes: a plurality of display data lines arranged side by side, at least one first electrostatic discharge line group 13, and a second electrostatic discharge line group 14. In the X-direction of the side-by-side arrangement of the plurality of display data lines, the plurality of display data lines include at least one peripheral display data line 11 and a plurality of non-peripheral display data lines 12. Each peripheral display data line 11 is electrically connected to a corresponding first electrostatic discharge line group 13. The second electrostatic discharge line group 14 is connected to the non-peripheral display data lines 12. Optionally, in this embodiment, the array substrate 1 includes only one second electrostatic discharge line group 14, in which case all non-peripheral display data lines 12 are connected to the second electrostatic discharge line group 14. Of course, in other embodiments, the array substrate 1 may also include more second electrostatic discharge lines 14, in which case the non-peripheral display data lines 12 may be selectively connected to one of the second electrostatic discharge lines 14.

[0031] Multiple display data lines are typically arranged side-by-side on the array substrate 1. These data lines provide data signals to the pixel electrodes within the display area of ​​the screen, enabling the pixel electrodes to display images based on the data signals. Different voltages on the display data lines correspond to different data signals. The display data lines closest to the edge of the array substrate 1 are defined as peripheral display data lines 11, and there can be one or more peripheral display data lines. The display data lines furthest from the edge of the array substrate 1 are defined as non-peripheral display data lines 12. The array substrate 1 typically also includes an electrostatic discharge (ESD) protection circuit for each display data line. This circuit connects to an ESD discharge line to release static electricity on the display data lines, preventing ESD from causing display abnormalities. However, during screen manufacturing, ESD can occur when the screen edge is touched or during the manufacturing process. Because the peripheral display data lines 11 are close to the screen edge, a short circuit between the peripheral display data lines 11 and the ESD discharge line may occur, leading to display abnormalities.

[0032] This application provides independent electrostatic discharge circuits for the peripheral display data line 11, which is prone to electrostatic damage, and the non-peripheral display data line 12, which is not prone to electrostatic damage. Under normal circumstances, the electrostatic charge generated at the front end of the peripheral display data line 11 is released through the first electrostatic discharge line group 13, while the electrostatic charge generated at the front end of the non-peripheral display data line 12 is released through the second electrostatic discharge line group 14. When the electrostatic discharge of the front end causes electrostatic damage to any peripheral display data line 11, resulting in a display abnormality, it will not damage or affect the other normally displaying peripheral display data lines and their corresponding first electrostatic discharge line group 13, as well as the non-peripheral display data lines 12 and the second electrostatic discharge line group 14. The electrostatic protection circuits of all display data lines except the peripheral display data line with the display abnormality can work normally.

[0033] Furthermore, in response to electrostatic damage to any peripheral display data line 11, the corresponding first electrostatic discharge line group 13 is configured to enable the peripheral display data line 11 to perform normal display operation, and the second electrostatic discharge line group 14 provides normal electrostatic protection for the non-peripheral display data line 12.

[0034] Specifically, electrostatic damage includes electrostatic short-circuit damage between any peripheral display data line 11 and the corresponding first electrostatic discharge line group 13 during the manufacturing process of the array substrate 1.

[0035] Specifically, in response to electrostatic short-circuit damage to any peripheral display data line 11, the corresponding first electrostatic discharge line group 13 is configured to have the same data voltage as the peripheral display data line 11 that has experienced electrostatic short-circuit damage.

[0036] When electrostatic discharge in the current segment causes a short circuit between the peripheral display data line 11 and the first electrostatic discharge line group 13, the data voltage of the first electrostatic discharge line group 13 is configured to be the same as the voltage of the damaged peripheral display data line 11. This ensures that the display of the damaged peripheral display data line remains normal and does not affect the display of other display data lines or electrostatic protection. The voltage of the first electrostatic discharge line group 13 can be controlled by an IC chip based on the voltage or grayscale of the corresponding peripheral display data line 11. The voltage control technology of the IC chip is existing technology and will not be described in detail here.

[0037] Furthermore, the first electrostatic discharge line group 13 is configured with a data voltage different from that of the corresponding peripheral display data line 11 to provide electrostatic protection for the peripheral display data line 11.

[0038] In the normal state without electrostatic discharge, the data voltage of the first electrostatic discharge line group 13 is different from the voltage of the corresponding peripheral display data line 11, which makes the first electrostatic discharge line group 13 unable to conduct with the peripheral display data line 11. Only when enough electrostatic charge accumulates on the peripheral display data line 11 can the electrostatic charge be released from the corresponding first electrostatic discharge line group 13, thus ensuring the normal display of all display data lines and the normal operation of the electrostatic protection circuit in both the normal state and the electrostatic discharge state.

[0039] Furthermore, such as Figure 2As shown, the array substrate 1 further includes multiple positive electrostatic discharge (ESD) switching units 15 and multiple negative ESD switching units 16; the first ESD discharge line group 13 includes a first positive ESD discharge line 131 and a first negative ESD discharge line 132; a peripheral display data line 11 is electrically connected to the first positive ESD discharge line 131 through a corresponding positive ESD switching unit 15, and a peripheral display data line 11 is electrically connected to the first negative ESD discharge line 132 through a corresponding negative ESD switching unit 16; the second ESD discharge line group 14 includes a second positive ESD discharge line 141 and a second negative ESD discharge line 142; a non-peripheral display data line 12 is electrically connected to the second positive ESD discharge line 141 through a corresponding positive ESD switching unit 15, and a non-peripheral display data line 12 is electrically connected to the second negative ESD discharge line 142 through a corresponding negative ESD switching unit 16.

[0040] Specifically, such as Figure 3 As shown, the second positive electrostatic discharge line 141 includes two positive power supply voltage terminals PVGH respectively disposed opposite to each other on both sides. The positive power supply voltage terminals PVGH can be arranged side by side with the display data lines, and the two positive power supply voltage terminals PVGH are electrically connected by a laterally extending first metal wire 143. The second negative electrostatic discharge line 142 includes two negative power supply voltage terminals PVGL respectively disposed opposite to each other on both sides. The negative power supply voltage terminals PVGL can be arranged side by side with the display data lines, and the two negative power supply voltage terminals PVGL are electrically connected by a laterally extending second metal wire 144. The positive power supply voltage terminals PVGH and PVGL provide high and low voltages for the horizontal scan lines, respectively. The voltage of PVGH is positive and always higher than the data line voltage, while the voltage of PVGL is negative and always lower than the data line voltage.

[0041] See also Figure 3 Two first positive electrostatic discharge lines 131 and two first negative electrostatic discharge lines 132 are provided, respectively positioned opposite each other on the inner side of the two positive power supply voltage terminals PVGH. Multiple non-peripheral display data lines 12 are provided, arranged side by side on the innermost side of the array substrate 1. Two peripheral display data lines 11 are provided, including a first peripheral display data line 111 and a second peripheral display data line 112, respectively arranged side by side on both sides of the non-peripheral display data lines 12.

[0042] like Figure 3As shown, the positive electrostatic switching unit 15 includes an NMOS transistor 151, and the negative electrostatic switching unit 16 includes a PMOS transistor 161. Each peripheral display data line or non-peripheral display data line is provided with one NMOS transistor 151 and one PMOS transistor 161. Specifically, the source and gate of the NMOS transistor 151 corresponding to the peripheral display data line 11 are electrically connected to either the first peripheral display data line 111 or the second peripheral display data line 112, and the drain of the NMOS transistor 151 is electrically connected to the first positive electrostatic discharge line 131; the source and gate of the NMOS transistor 151 corresponding to the non-peripheral display data line 12 are electrically connected to the non-peripheral display data line 12, and the drain of the NMOS transistor 151 is electrically connected to the second metal line 144; the drain of the PMOS transistor 161 corresponding to the peripheral display data line 11 is electrically connected to either the first peripheral display data line 111 or the second peripheral display data line 112, and the source and gate of the PMOS transistor 161 are electrically connected to the first negative electrostatic discharge line 132; the source and gate of the PMOS transistor 161 corresponding to the non-peripheral display data line 12 are electrically connected to the first metal line 143, and the drain of the NMOS transistor 151 is electrically connected to the non-peripheral display data line 12.

[0043] Positive and negative electrostatic charges are released through different electrostatic discharge circuits. The NMOS transistor acts as the switch for the positive electrostatic charge discharge circuit, and the PMOS transistor acts as the switch for the negative electrostatic charge discharge circuit.

[0044] In the normal state without electrostatic discharge, the first positive electrostatic discharge line 131 has a voltage lower than or higher than the peripheral display data line 11 to which it is electrically connected, preventing the first positive electrostatic discharge line 131 from conducting with its corresponding peripheral display data line 11. Only when enough positive electrostatic charge accumulates on the peripheral display data line 11, exceeding the turn-on voltage of the NMOS transistor 151, will the NMOS transistor 151 conduct, and the positive electrostatic charge will be introduced into the first positive electrostatic discharge line 131. Meanwhile, the negative power supply voltage terminal PVGL always has a voltage lower than the non-peripheral display data line 12 to which it is electrically connected, preventing the negative power supply voltage terminal PVGL from conducting with the non-peripheral display data line 12. Only when enough positive electrostatic charge accumulates on the non-peripheral display data line 12, exceeding the turn-on voltage of the NMOS transistor 151, will the NMOS transistor 151 conduct, and the positive electrostatic charge will be introduced into the negative power supply voltage terminal PVGL. In the normal state without electrostatic discharge, the first negative electrostatic discharge line 132 has a voltage higher than that of the peripheral display data line 11 to which it is electrically connected, or a gray level lower than that of the peripheral display data line 11, so that the first negative electrostatic discharge line 132 cannot be connected to its corresponding peripheral display data line 11. Only when enough negative electrostatic charge accumulates on the peripheral display data line 11, exceeding the turn-on voltage of the PMOS transistor 161, will the PMOS transistor 161 be turned on, and the negative electrostatic charge will be introduced into the first negative electrostatic discharge line 132. Meanwhile, the positive power supply voltage terminal PVGH always has a voltage higher than that of the non-peripheral display data line 12, so that the positive power supply voltage terminal PVGH cannot be connected to the non-peripheral display data line 12. Only when enough negative electrostatic charge accumulates on the non-peripheral display data line 12, exceeding the turn-on voltage of the PMOS transistor 161, will the PMOS transistor 161 be turned on, and the negative electrostatic charge will be introduced into the positive power supply voltage terminal PVGH for release.

[0045] When electrostatic discharge occurring in the current segment causes electrostatic short-circuit damage between the peripheral display data line 11 and the first electrostatic discharge line group 13, such as Figure 3As shown, the short circuit location of the first peripheral display data line 111 is usually point A. At this time, the negative electrostatic charge is easily damaged during the release of the negative electrostatic discharge line 132 on the left. By configuring the data voltage of the left first negative electrostatic discharge line 132 to be the same as the voltage of the damaged first peripheral display data line 111, the normal display of the first peripheral display data line 111 can be ensured. The short circuit location of the second peripheral display data line 112 is usually point B. At this time, the positive electrostatic charge is easily damaged during the release of the right first positive electrostatic discharge line 131. By configuring the data voltage of the right first positive electrostatic discharge line 131 to be the same as the voltage of the damaged second peripheral display data line 112, the normal display of the second peripheral display data line 112 can be ensured, and it will not affect the display of other display data lines or the electrostatic protection.

[0046] Furthermore, the array substrate also includes spare data lines, with the first electrostatic discharge line group 13 serving as a spare data line.

[0047] The array substrate typically has several idle spare data lines located in the non-display area. These spare data lines do not serve a display function. Using these spare data lines as the lines for the first electrostatic discharge line group 13 eliminates the need for additional wiring, simplifying fabrication. Furthermore, even if electrostatic damage occurs, the spare data lines located in the non-display area, for example... Figure 3 The voltage abnormalities of the first negative electrostatic discharge line 132 on the left and the first positive electrostatic discharge line 131 on the right will not be displayed to the user, and the voltage adjustment accuracy of the spare data line is high, and the voltage can be set according to the corresponding convenience.

[0048] In other embodiments, the first electrostatic discharge line group 13 may also be an additional positive power supply voltage terminal PVGH and a negative power supply voltage terminal PVGL, which are used to release negative electrostatic charge and positive electrostatic charge, respectively.

[0049] The peripheral display data lines 11 are not limited to the two display data lines located at the edge. To further expand the protection range of the peripheral display data lines 11, separate electrostatic discharge (ESD) protection circuits can be set for multiple peripheral display data lines 11 near the edge. For example... Figure 4In another embodiment shown, the difference from the previous embodiment is that the peripheral display data line 11 includes four display data lines near the edge, that is, two on each side. Taking the left side as an example, the peripheral display data line 11 includes a first peripheral display data line 111 and a third peripheral display data line 113. On the left side, a first electrostatic discharge line group 13 is also provided for each of the first peripheral display data line 111 and the third peripheral display data line 113. Each first electrostatic discharge line group 13 includes a first positive electrostatic discharge line 131 and a first negative electrostatic discharge line 132 arranged side by side, and is connected to the peripheral display data line through an NMOS transistor 151 and a PMOS transistor 161, respectively. The locations where short circuits are likely to occur include A1 and A2. The connection method between the first electrostatic discharge line group 13 and the NMOS transistor 151 or the PMOS transistor 161 is the same as in the previous embodiment. Each peripheral display data line 11 and non-peripheral display data line 12 is connected to an NMOS transistor 151 and a PMOS transistor 161.

[0050] In another embodiment, a display panel includes the array substrate of any of the above embodiments. Optionally, the display panel may be an OLED display panel, a Micro-LED display panel, etc.

[0051] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a plurality of display data lines arranged side by side; in the side-by-side arrangement direction of the plurality of display data lines, the plurality of display data lines comprises at least one peripheral display data line and a plurality of non-peripheral display data lines; at least one first electrostatic discharge line group, each of the peripheral display data lines is electrically connected to a corresponding first electrostatic discharge line group; a second electrostatic discharge line group connected to the non-peripheral display data lines; wherein, in response to any of the peripheral display data lines being damaged by electrostatic short circuit, the corresponding first electrostatic discharge line group is configured to have the same data voltage as the peripheral display data line damaged by the electrostatic short circuit, so that the peripheral display data line can perform normal display operation, and the second electrostatic discharge line group is used to perform normal electrostatic protection on the non-peripheral display data lines; Meanwhile, the array substrate further comprises: a spare data line, and the first electrostatic discharge line group is a spare data line.

2. The array substrate according to claim 1, wherein the electrostatic damage includes electrostatic short circuit damage between any of the peripheral display data lines and the corresponding first electrostatic discharge line group during the manufacturing process of the array substrate.

3. The array substrate according to claim 1, wherein the first electrostatic discharge line group is configured to have a data voltage different from that of the corresponding peripheral display data line, so as to perform electrostatic protection on the peripheral display data line.

4. The array substrate according to claim 1, wherein the array substrate further comprises a plurality of positive electrostatic switch units and a plurality of negative electrostatic switch units; the first electrostatic discharge line group comprises a first positive electrostatic discharge line and a first negative electrostatic discharge line; one of the peripheral display data lines is electrically connected to the first positive electrostatic discharge line through a corresponding positive electrostatic switch unit, and one of the peripheral display data lines is electrically connected to the first negative electrostatic discharge line through a corresponding negative electrostatic switch unit; and / or, the second electrostatic discharge line group comprises a second positive electrostatic discharge line and a second negative electrostatic discharge line; one of the non-peripheral display data lines is electrically connected to the second positive electrostatic discharge line through a corresponding positive electrostatic switch unit, and one of the non-peripheral display data lines is electrically connected to the second negative electrostatic discharge line through a corresponding negative electrostatic switch unit.

5. The array substrate according to claim 4, wherein the positive electrostatic switch unit comprises an NMOS transistor, the negative electrostatic switch unit comprises a PMOS transistor, the first positive electrostatic discharge line has a voltage lower than that of the peripheral display data line electrically connected thereto so that the positive electrostatic switch unit is only turned on during positive electrostatic discharge, and the first negative electrostatic discharge line has a voltage higher than that of the peripheral display data line electrically connected thereto so that the negative electrostatic switch unit is only turned on during negative electrostatic discharge.

6. The array substrate according to claim 1, wherein in the side-by-side arrangement direction, the peripheral display data line is composed of two edge display data lines arranged opposite to the plurality of non-peripheral display data lines on both sides.

7. The array substrate of claim 6, wherein: a number of the first static electricity releasing line groups is two; the first static electricity releasing line group is located on a side of the edge display data line away from the non-peripheral display data line.

8. A display panel, comprising: the array substrate of any one of claims 1-7.

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