Method for manufacturing silicon-germanium heterojunction transistor

Abstract

The present invention provides a method for manufacturing a silicon-germanium heterojunction transistor. The method comprises providing a substrate on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the first polysilicon layer. Subsequently, portions of the second dielectric layer and the first polysilicon layer are removed by photolithography and etching to form a first stack located above the active area. A third dielectric layer is formed on the first dielectric layer and the stack, and the third dielectric layer between the STI and the stack is opened to expose the first dielectric layer below it. The exposed first dielectric layer is then removed by etching to form a first recess. A first epitaxial layer is formed at the bottom of the first recess, and a fourth dielectric layer is formed on the first epitaxial layer and the third dielectric layer. The method of the present invention connects the SiGe layer to the gate layer solely through epitaxial growth from the bottom up.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a germanium-silicon heterojunction transistor. Background Art

[0002] The rapid development of modern mobile and microwave communications technologies has led to an increasing demand in the communications market for low-cost, high-performance RF / microwave devices. While traditional silicon (Si) devices offer advantages such as low cost and mature process technology, their operating frequency is limited. SiGe (silicon germanium epitaxial layer) devices have attracted significant attention due to their low power consumption, high characteristic frequency, and compatibility with mature Si processes.

[0003] The high-performance mass-produced SiGe HBT (silicon-germanium heterojunction transistor) device structure in existing technology is based on the double-layer polysilicon self-aligned process (DPSA). This structure of the device has very high requirements for SiGe epitaxial technology. Its technical difficulty lies in the connection between the selective epitaxial growth of the base SiGe layer and the external base Poly (gate) layer. Figure 1 The connection region of this type of structure has two opposite directions of epitaxy during SiGe epitaxy: bottom-up epitaxy as shown in ① and top-down epitaxy as shown in ②. These two opposite directions of epitaxy make the connection between the base region and the extrinsic base region more complicated.

[0004] In order to solve the above problems, it is necessary to propose a new method for manufacturing a germanium-silicon heterojunction transistor. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a germanium-silicon heterojunction transistor, which is used to solve the problem of selective epitaxy of the base epitaxial layer of the germanium-silicon heterojunction transistor and the connection with the external base gate layer in the prior art.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a germanium-silicon heterojunction transistor, comprising:

[0007] Step 1: providing a substrate on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the first polysilicon layer, and then removing portions of the second dielectric layer and the first polysilicon layer by photolithography and etching to form a first stack located on the active area;

[0008] Step 2: forming a third dielectric layer on the first dielectric layer and the stack, opening the third dielectric layer between the STI and the stack to expose the first dielectric layer thereunder, and then etching away the exposed first dielectric layer to form a first groove;

[0009] Step 3: forming a first epitaxial layer at the bottom of the first groove, forming a fourth dielectric layer on the first epitaxial layer and the third dielectric layer, and then etching away the second dielectric layer, the third dielectric layer, and the fourth dielectric layer above the first polysilicon layer;

[0010] Step 4: forming a fifth dielectric layer on the fourth dielectric layer, and then removing the first polysilicon layer and the first dielectric layer below the first polysilicon layer to form a second inverted T-shaped groove;

[0011] Step 5: forming a second epitaxial layer at the bottom of the second groove, forming a second polysilicon layer filling the remaining second groove and a sixth dielectric layer located on the second polysilicon layer on the second epitaxial layer, and then etching a portion of the sixth dielectric layer and the second polysilicon layer thereunder, and the fifth dielectric layer to the surface of the fourth dielectric layer to form a first device structure;

[0012] Step 6: forming a seventh dielectric layer on the surface of the first device structure, and then removing a portion of the seventh dielectric layer and the fourth dielectric layer thereunder by photolithography and etching to expose the third dielectric layer;

[0013] Step 7: etching and removing the fourth dielectric layer to form a third groove, and then forming a third polysilicon layer in the third groove;

[0014] Step eight: etching away the exposed third dielectric layer, and then removing a portion of the seventh dielectric layer and the sixth dielectric layer thereunder by photolithography and etching to expose the second polysilicon layer, so as to form a second device structure.

[0015] Preferably, the substrate in step 1 is a silicon substrate.

[0016] Preferably, the material of the first dielectric layer in step 1 is silicon dioxide.

[0017] Preferably, the material of the second dielectric layer in step 1 is silicon nitride.

[0018] Preferably, the material of the third dielectric layer in step 2 is silicon nitride.

[0019] Preferably, in step 2, the exposed first dielectric layer is etched away using a wet etching method.

[0020] Preferably, the first epitaxial layer in step three is a silicon-germanium epitaxial layer.

[0021] Preferably, the material of the fourth dielectric layer in step three is silicon dioxide.

[0022] Preferably, the material of the fifth dielectric layer in step 4 is silicon nitride.

[0023] Preferably, the second epitaxial layer in step five is a silicon-germanium epitaxial layer.

[0024] Preferably, the material of the sixth dielectric layer in step five is silicon nitride.

[0025] Preferably, the material of the seventh dielectric layer in step six is silicon nitride.

[0026] Preferably, the etching method in step seven is wet etching.

[0027] As described above, the method for manufacturing a silicon-germanium heterojunction transistor of the present invention has the following beneficial effects:

[0028] The method of the present invention can connect the SiGe layer and the gate layer only through epitaxy from bottom to top. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram showing a structure of a silicon-germanium heterojunction transistor during the manufacturing process of the prior art is shown;

[0030] Figure 2 Display as Figure 1 A magnified schematic diagram of point A;

[0031] Figure 3 Shown is a schematic diagram of the process flow of the present invention;

[0032] Figure 4 Shown is a schematic diagram of forming a stack of layers according to the present invention;

[0033] Figure 5 It is a schematic diagram showing the formation of the first epitaxial layer and a partial structure thereon according to the present invention;

[0034] Figure 6 Schematic diagram showing the formation of the fifth dielectric layer according to the present invention;

[0035] Figure 7 Shown is a schematic diagram of a second groove forming an inverted T shape according to the present invention;

[0036] Figure 8 Shown is a schematic diagram of the structure of a first device formed according to the present invention;

[0037] Figure 9Schematic diagram showing the formation of a seventh dielectric layer on the surface of the first device structure according to the present invention, followed by photolithography and etching to remove a portion of the seventh dielectric layer and the fourth dielectric layer thereunder so as to expose the third dielectric layer;

[0038] Figure 10 Shown is a schematic diagram of forming a third groove according to the present invention;

[0039] Figure 11 Schematic diagram showing the formation of a third polysilicon layer filling the third groove according to the present invention;

[0040] Figure 12 Schematic diagram showing the etching removal of the exposed third dielectric layer according to the present invention;

[0041] Figure 13 Shown is a schematic diagram of the second device structure of the present invention. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] See also Figure 3 The present invention provides a method for manufacturing a germanium-silicon heterojunction transistor, comprising:

[0044] Step 1: Please refer to Figure 4 A substrate 01 is provided. An STI is formed on the substrate 01 to define an active area. A first dielectric layer 02 is formed on the substrate 01. A first polysilicon layer 03 is formed on the first dielectric layer 02. A second dielectric layer 04 is formed on the first polysilicon layer 03. Then, a portion of the second dielectric layer 04 and the first polysilicon layer 03 is removed by photolithography and etching. That is, a photoresist layer is formed on the second dielectric layer 04. The photoresist layer is opened by photolithography to expose a portion of the second dielectric layer 04 to define an etching area of the second dielectric layer 04 and the first polysilicon layer 03. Then, the exposed second dielectric layer 04 and the first polysilicon layer 03 thereunder are etched to form a first stack located on the active area.

[0045] In an embodiment of the present invention, the substrate 01 in step 1 is a silicon substrate.

[0046] In an embodiment of the present invention, the material of the first dielectric layer 02 in step 1 is silicon dioxide, which can generally be formed by a chemical vapor deposition method.

[0047] In an embodiment of the present invention, the material of the second dielectric layer 04 in step 1 is silicon nitride, which can generally be formed by a chemical vapor deposition method.

[0048] Step 2: Form a third dielectric layer 05 on the first dielectric layer 02 and the stack, and open the third dielectric layer 05 between the STI and the stack. Specifically, the third dielectric layer 05 between the STI and the stack can be opened by photolithography and etching to expose the first dielectric layer 02 thereunder. The exposed first dielectric layer 02 is then etched away to form a first groove.

[0049] In an embodiment of the present invention, the material of the third dielectric layer 05 in step 2 is silicon nitride.

[0050] In an embodiment of the present invention, the material of the first dielectric layer 02 in step 1 is silicon dioxide, and the exposed first dielectric layer 02 is removed by etching using a wet etching method in step 2.

[0051] Step 3: Form a first epitaxial layer 06 at the bottom of the first groove, and form a fourth dielectric layer 07 on the first epitaxial layer 06 and the third dielectric layer 05. Then, remove the second dielectric layer 04, the third dielectric layer 05 and the fourth dielectric layer 07 above the first polysilicon layer 03 by etching. The etching method is dry etching to form Figure 5 The structure shown;

[0052] In an embodiment of the present invention, the first epitaxial layer 06 in step three is a silicon-germanium epitaxial layer.

[0053] In an embodiment of the present invention, the material of the fourth dielectric layer 07 in step three is silicon dioxide, which can generally be formed by a chemical vapor deposition method.

[0054] Step 4: Form a fifth dielectric layer 08 on the fourth dielectric layer 07. Figure 6 The structure shown in FIG. 1 is then formed by removing the first polysilicon layer 03 and the first dielectric layer 02 below the first polysilicon layer 03 to form a second inverted T-shaped groove. Specifically, the first polysilicon layer 03 can be removed by dry etching, and then the first dielectric layer 02 can be removed by wet etching to form a second inverted T-shaped groove. Figure 7 The structure shown;

[0055] In an embodiment of the present invention, the material of the fifth dielectric layer 08 in step 4 is silicon nitride, which can generally be formed by chemical vapor deposition.

[0056] Step 5: Form a second epitaxial layer 09 at the bottom of the second groove, and form a second polysilicon layer 03 filling the remaining second groove on the second epitaxial layer 09 and a sixth dielectric layer 11 located on the second polysilicon layer 03. Then, partially etch the sixth dielectric layer 11 and the second polysilicon layer 03, the fifth dielectric layer 08 to the fourth dielectric layer 07 below it, that is, etch away the sixth dielectric layer 11. Figure 7 Part of the outer structure of the structure shown is used to form a first device structure, forming a Figure 8 The structure shown;

[0057] In an embodiment of the present invention, the second epitaxial layer 09 in step five is a silicon-germanium epitaxial layer.

[0058] In an embodiment of the present invention, the material of the sixth dielectric layer 11 in step five is silicon nitride, which can generally be formed by chemical vapor deposition.

[0059] Step 6: Form a seventh dielectric layer 12 on the surface of the first device structure, then remove part of the seventh dielectric layer 12 and the fourth dielectric layer 07 thereunder by photolithography and etching to expose the third dielectric layer 05. The etching method is dry etching to form Figure 9 The structure shown;

[0060] In an embodiment of the present invention, the material of the seventh dielectric layer 12 in step six is silicon nitride, which can generally be formed by chemical vapor deposition.

[0061] Step 7: Etch and remove the fourth dielectric layer 07 to form a third groove, forming a Figure 10 The structure shown in FIG. 1 is then formed to fill the third groove with a third polysilicon layer 13. At this time, part of the third dielectric layer 05 is exposed, forming a structure as shown in FIG. Figure 11 The structure shown, that is, the SiGe layer and the gate layer can be connected only by epitaxy in the bottom-up direction;

[0062] In an embodiment of the present invention, the material of the fourth dielectric layer 07 is silicon dioxide, and the etching method in step seven is wet etching.

[0063] Step eight, etching to remove the exposed third dielectric layer 05, the etching method is dry etching, forming a structure as shown in 12, and then removing part of the seventh dielectric layer 12 and the sixth dielectric layer 11 thereunder by photolithography and etching to expose the second polysilicon layer 03, so as to form a structure as shown in Figure 13 The second device structure is shown.

[0064] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0065] In summary, the method of the present invention can connect the SiGe layer and the gate layer only through epitaxy from the bottom up, simplifying the connection problem between the two. Therefore, the present invention effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a germanium-silicon heterojunction transistor, characterized in that: At least: Step 1: providing a substrate on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the first polysilicon layer, and then removing portions of the second dielectric layer and the first polysilicon layer by photolithography and etching to form a first stack located on the active area; Step 2: forming a third dielectric layer on the first dielectric layer and the stack, opening the third dielectric layer between the STI and the stack to expose the first dielectric layer thereunder, and then etching away the exposed first dielectric layer to form a first groove; Step 3: forming a first epitaxial layer at the bottom of the first groove, forming a fourth dielectric layer on the first epitaxial layer and the third dielectric layer, and then etching away the second dielectric layer, the third dielectric layer, and the fourth dielectric layer above the first polysilicon layer; Step 4: forming a fifth dielectric layer on the fourth dielectric layer, and then removing the first polysilicon layer and the first dielectric layer below the first polysilicon layer to form a second inverted T-shaped groove; Step 5: forming a second epitaxial layer at the bottom of the second groove, forming a second polysilicon layer filling the remaining second groove and a sixth dielectric layer located on the second polysilicon layer on the second epitaxial layer, and then etching a portion of the sixth dielectric layer and the second polysilicon layer thereunder, and the fifth dielectric layer to the surface of the fourth dielectric layer to form a first device structure; Step 6: forming a seventh dielectric layer on the surface of the first device structure, and then removing a portion of the seventh dielectric layer and the fourth dielectric layer thereunder by photolithography and etching to expose the third dielectric layer; Step 7: etching and removing the fourth dielectric layer to form a third groove, and then forming a third polysilicon layer filling the third groove; Step eight: etching away the exposed third dielectric layer, and then removing a portion of the seventh dielectric layer and the sixth dielectric layer thereunder by photolithography and etching to expose the second polysilicon layer, so as to form a second device structure.

2. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The substrate in step 1 is a silicon substrate.

3. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the first dielectric layer in step 1 is silicon dioxide.

4. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the second dielectric layer in step 1 is silicon nitride.

5. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the third dielectric layer in step 2 is silicon nitride.

6. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 3, wherein: In step 2, the exposed first dielectric layer is etched away using a wet etching method.

7. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The first epitaxial layer in step three is a silicon-germanium epitaxial layer.

8. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the fourth dielectric layer in step three is silicon dioxide.

9. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the fifth dielectric layer in step 4 is silicon nitride.

10. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The second epitaxial layer in step five is a silicon-germanium epitaxial layer.

11. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the sixth dielectric layer in step five is silicon nitride.

12. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the seventh dielectric layer in step six is silicon nitride.

13. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 8, wherein: The etching method in step seven is wet etching.

Images