Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, an ohmic contact, and a spacer. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap that is greater than a bandgap of the first nitride semiconductor layer. The ohmic contact is disposed on the first nitride semiconductor layer. The spacer is disposed adjacent to a sidewall of the ohmic contact, wherein the sidewall of the ohmic contact has a relatively rough surface.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202080003533.9, filed on November 30, 2020, entitled “Semiconductor Device and Method of Manufacturing the Same”. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a high electron mobility transistor (HEMT). BACKGROUND

[0003] Semiconductor components including a direct bandgap, such as semiconductor elements including III-V materials or III-V compounds, can be operated under various conditions or environments (e.g., different voltages or frequencies) due to their properties.

[0004] The aforementioned semiconductor components can include a HEMT, a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), or a modulation doped field effect transistor (MODFET). SUMMARY

[0005] According to one aspect of the present disclosure, a semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, an ohmic contact, and a spacer. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than a bandgap of the first nitride semiconductor layer. The ohmic contact is disposed on the first nitride semiconductor layer. The spacer is disposed adjacent to a sidewall of the ohmic contact, wherein the sidewall of the ohmic contact has a relatively rough surface.

[0006] According to one aspect of the present disclosure, a semiconductor device structure includes a first nitride semiconductor layer, a second nitride semiconductor layer, an ohmic contact, a first passivation layer, and a second passivation layer. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than a bandgap of the first nitride semiconductor layer. The ohmic contact is disposed on the first nitride semiconductor layer. The first passivation layer is disposed on the second nitride semiconductor layer. The second passivation layer is disposed on the ohmic contact and the first passivation layer, wherein the ohmic contact has a sidewall between the first passivation layer and the second passivation layer, and the sidewall has a relatively rough surface.

[0007] According to one aspect of the disclosure, a method of manufacturing a semiconductor device includes the following steps. A semiconductor stack is provided, the semiconductor stack including a substrate, a first nitride semiconductor layer on the substrate, and a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer has a bandgap that is greater than a bandgap of the first nitride semiconductor layer. A first ohmic contact is formed on the first nitride semiconductor layer. A spacer is formed attached to a sidewall of the first ohmic contact. Annealing is performed after forming the spacer, such that a profile of the first ohmic contact is changed due to the annealing operation, and such that the sidewall of the first ohmic contact has a relatively rough surface. A second ohmic contact is formed after forming the spacer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Aspects of the disclosure will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which various features are not necessarily drawn to scale. It should be noted that various features can not be drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity.

[0009] FIG. 1A is a side view of a semiconductor device according to some embodiments of the disclosure;

[0010] FIG. 1B is an enlarged side view of a semiconductor structure according to some embodiments of the disclosure;

[0011] FIG. 1C is an enlarged side view of a semiconductor structure according to some embodiments of the disclosure;

[0012] FIG. 1D is an enlarged side view of a semiconductor structure according to some embodiments of the disclosure;

[0013] FIG. 2A 、 FIG. 2B 、 FIG. 2C 、 FIG. 2D 、 FIG. 2E 、 FIG. 2F and FIG. 2G illustrate several operations for manufacturing a semiconductor device according to some embodiments of the disclosure;

[0014]

[0015] FIG. 3A 、 FIG. 3B 、 FIG. 3C 、 FIG. 3D 、 FIG. 3E and FIG. 3F illustrate several operations for manufacturing a semiconductor device according to some embodiments of the disclosure;

[0016] ​​

[0017] FIG. 4A is a side view of a semiconductor device according to some embodiments of the disclosure;

[0018] FIG. 4B is an enlarged side view of a semiconductor structure according to some embodiments of the disclosure; and

[0019] FIG. 5A 、 FIG. 5B 、 FIG. 5C 、 FIG. 5D 、 FIG. 5E and FIG. 5F illustrate several operations for fabricating a semiconductor device according to some embodiments of the disclosure.

[0020] DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to provide a thorough description of embodiments. These are, of course, merely examples and are not intended to be limiting. In the disclosure, descriptions of a first feature forming over or on a second feature can encompass embodiments where the first feature and the second feature form in direct contact, and can further encompass embodiments where additional features can form between the first feature and the second feature such that the first feature and the second feature do not form in direct contact. Additionally, reference numerals and / or letters in the following description are meant to be examples only and are not intended to be limiting.

[0022] Embodiments of the present disclosure are described in detail below. It should be appreciated, however, that the many applicable concepts provided by the present disclosure can be implemented in a variety of specific contexts. The described specific embodiments are merely illustrative and not limiting of the scope of the present disclosure.

[0023] Direct bandgap materials such as III-V compounds can include, but are not limited to, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), etc.

[0024] FIG. 1A is a side view of a semiconductor device 1 according to some embodiments of the disclosure.

[0025] As shown in FIG. 1, semiconductor device 1 can include substrate 10, semiconductor layer 12, semiconductor layer 14, conductive junction 16, spacer 18, passivation layer 22, another passivation layer 24, yet another passivation layer 25, and conductive structure 16. FIG. 1A

[0026] construction 16, spacer 18, passivation layer 22, another passivation layer 24, yet another passivation layer 25, and conductive structure 16. ​​

[0027] The substrate 10 may comprise, for example, but not limited to, silicon (Si), doped silicon (doped Si), silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other suitable materials. For example, in some embodiments, the substrate 10 may comprise an intrinsic semiconductor material. For example, in some other embodiments, the substrate 10 may comprise a p-type semiconductor material. For example, in some other embodiments, the substrate 10 may comprise a silicon layer doped with boron (B). For example, in some other embodiments, the substrate 10 may comprise a silicon layer doped with gallium (Ga). For example, in some other embodiments, the substrate 10 may comprise an n-type semiconductor material. For example, in some other embodiments, the substrate 10 may comprise a silicon layer doped with arsenic (As). For example, in some other embodiments, the substrate 10 may comprise a silicon layer doped with phosphorus (P).

[0028] Semiconductor layer 12 may be disposed on substrate 10. Semiconductor layer 12 may contain a III-V material. Semiconductor layer 12 may be a nitride semiconductor layer. Semiconductor layer 12 may contain, for example, but not limited to, group III nitrides. Semiconductor layer 12 may contain, for example, but not limited to, GaN. Semiconductor layer 12 may contain, for example, but not limited to, AlN. Semiconductor layer 12 may contain, for example, but not limited to, InN. Semiconductor layer 12 may contain, for example, but not limited to, compound In. x Al y Ga 1−x−y N, where x+y≤1. Semiconductor layer 12 may contain, for example, but not limited to, the compound Al. y Ga (1-y) N, where y≤1.

[0029] Buffer layer or nucleation layer ( FIG. 1A (Not shown) A buffer layer (not shown) may be formed or disposed between substrate 10 and semiconductor layer 12. The buffer layer may contain a nitride. In some embodiments, the buffer layer may contain, for example, but not limited to, aluminum nitride (AlN) or other suitable materials. In some other embodiments, the buffer layer may contain, for example, but not limited to, aluminum gallium nitride (AlGaN) or other suitable materials. The buffer layer may contain a multilayer structure. The buffer layer may contain a superlattice structure of cyclically stacked two or more materials. The buffer layer may contain a monolayer structure.

[0030] Semiconductor layer 14 may be disposed on semiconductor layer 12. Semiconductor layer 14 may contain a III-V material. Semiconductor layer 14 may be a nitride semiconductor layer. Semiconductor layer 14 may contain, for example, but not limited to, group III nitrides. Semiconductor layer 14 may contain, for example, but not limited to, compounds Al. y Ga (1-y)N, where y ≤ 1. Semiconductor layer 14 may contain, for example, but not limited to, GaN. Semiconductor layer 14 may contain, for example, but not limited to, AlN. Semiconductor layer 14 may contain, for example, but not limited to, InN. Semiconductor layer 14 may contain, for example, but not limited to, compound In. x Al y Ga 1−x−y N, where x+y≤1. A heterojunction can be formed between semiconductor layer 14 and semiconductor layer 12. Semiconductor layer 14 can have a band gap greater than that of semiconductor layer 12. For example, semiconductor layer 14 can contain AlGaN with a band gap of about 4 eV, and semiconductor layer 12 can contain GaN with a band gap of about 3.4 eV.

[0031] In semiconductor device 1, semiconductor layer 12 can be used as a channel layer. In semiconductor device 1, semiconductor layer 12 can be used as a channel layer disposed on substrate 10. In semiconductor device 1, semiconductor layer 14 can be used as a barrier layer. In semiconductor device 1, semiconductor layer 14 can be used as a barrier layer disposed on semiconductor layer 12.

[0032] In semiconductor device 1, the band gap of semiconductor layer 12 may be smaller than the band gap of semiconductor layer 14 to form a two-dimensional electron gas (2DEG) in semiconductor layer 12. In semiconductor device 1, the band gap of semiconductor layer 12 may be smaller than the band gap of semiconductor layer 14 to form a 2DEG in semiconductor layer 12, and the 2DEG is close to or adjacent to the interface (or boundary) between semiconductor layer 14 and semiconductor layer 12. In semiconductor device 1, the band gap of semiconductor layer 14 may be larger than the band gap of semiconductor layer 12 to form a 2DEG in semiconductor layer 12. In semiconductor device 1, the band gap of semiconductor layer 14 may be larger than the band gap of semiconductor layer 12 to form a 2DEG in semiconductor layer 12, and the 2DEG is close to or adjacent to the interface (or boundary) between semiconductor layer 14 and semiconductor layer 12.

[0033] Conductive structure 16 may be disposed on semiconductor layer 12. Conductive structure 16 may be surrounded by semiconductor layer 14. Conductive structure 16 may be surrounded by spacer 18. Conductive structure 16 may be surrounded by passivation layer 22. Conductive structure 16 may be surrounded by passivation layer 24. Conductive structure 16 may contain conductive material. Conductive structure 16 may contain semiconductor material. Conductive structure 16 may contain metal. Conductive structure 16 may contain, for example, but not limited to, Al, Ti, and Si, or other suitable materials.

[0034] In semiconductor device 1, conductive structure 16 can be used as, for example, but not limited to, a drain conductor. In semiconductor device 1, conductive structure 16 can be used as, for example, but not limited to, a source conductor. In semiconductor device 1, conductive structure 16 can have an ohmic contact for the drain conductor. In semiconductor device 1, conductive structure 16 can have an ohmic contact for the source conductor.

[0035] Spacer 18 may be located on semiconductor layer 14. Spacer 18 may be disposed on passivation layer 22. Spacer 18 is located on passivation layer 22. Spacer 18 may be in direct contact with passivation layer 22. Spacer 18 may cover the sidewall of conductive structure 16. FIG. 1A (Not shown in the image). The spacer 18 may cover the two sidewalls of the conductive structure 16 ( FIG. 1A (Not shown in the image). Spacer 18 may surround conductive structure 16. Spacer 18 may enclose conductive structure 16. Spacer 18 may be in direct contact with the sidewall of conductive structure 16. FIG. 1A (Not shown in the image). The spacer 18 can directly contact the two sidewalls of the conductive structure 16. FIG. 1A (Not shown in the image). Spacer 18 may contain a dielectric material. Spacer 18 may contain an insulating material. Spacer 18 may contain a nitride. Spacer 18 may contain, for example, but not limited to, silicon nitride (Si3N4) or other suitable materials. Spacer 18 may contain an oxide. Spacer 18 may contain (but not limited to) silicon oxide (SiO2) or other suitable materials. Spacer 18 may electrically isolate conductive structure 16. Spacer 18 may be heat-resistant. Spacer 18 may withstand temperatures above 600°C. Spacer 18 may withstand temperatures above 800°C. Spacer 18 may withstand temperatures above 1000°C.

[0036] Passivation layer 22 may be disposed on semiconductor layer 14. Passivation layer 22 may surround conductive structure 16. Passivation layer 22 may have a portion covered by conductive structure 16. Passivation layer 22 may surround conductive structure 26. Passivation layer 22 may have a portion beneath conductive structure 26. Passivation layer 22 may contain a dielectric material. Passivation layer 22 may contain a nitride. Passivation layer 22 may contain, for example, but not limited to, silicon nitride (Si3N4) or other suitable materials. Passivation layer 22 may contain an oxide. Passivation layer 22 may contain, for example, but not limited to, silicon oxide (SiO2) or other suitable materials. Passivation layer 22 may electrically isolate conductive structure 16.

[0037] Passivation layer 24 may be disposed on passivation layer 22. Passivation layer 24 may surround conductive structure 16. Passivation layer 24 may cover conductive structure 16. Passivation layer 24 may surround spacer 18. Passivation layer 24 may be in direct contact with spacer 18. Passivation layer 24 may cover spacer 18. Passivation layer 24 may surround conductive structure 26. Passivation layer 24 may have a portion covered by conductive structure 26. Passivation layer 24 may contain dielectric material. Passivation layer 24 may contain nitride. Passivation layer 24 may contain, for example, but not limited to, silicon nitride (Si3N4) or other suitable materials. Passivation layer 24 may contain oxide. Passivation layer 24 may contain, for example, but not limited to, silicon oxide (SiO2) or other suitable materials. Passivation layer 24 may electrically isolate conductive structure 16. Passivation layer 24 may electrically isolate conductive structure 26.

[0038] The conductive structure 26 may be disposed on the semiconductor layer 14. The conductive structure 26 may contain a metal. The conductive structure 26 may contain, for example, but not limited to, gold (Au), platinum (Pt), titanium (Ti), palladium (Pd), nickel (Ni), tungsten (W), or other suitable materials. The conductive structure 26 may contain a metal compound. The conductive structure 26 may contain, for example, but not limited to, titanium nitride (TiN), or other suitable materials.

[0039] Passivation layer 25 may be disposed on passivation layer 24. Passivation layer 25 may be disposed on conductive structure 26. Passivation layer 25 may cover passivation layer 24. Passivation layer 25 may cover conductive structure 26. Passivation layer 25 may be in direct contact with passivation layer 24. Passivation layer 25 may contain a dielectric material. Passivation layer 25 may contain a nitride. Passivation layer 25 may contain, for example, but not limited to, silicon nitride (Si3N4) or other suitable materials. Passivation layer 25 may contain an oxide. Passivation layer 25 may contain, for example, but not limited to, silicon oxide (SiO2) or other suitable materials. Passivation layer 25 may electrically isolate conductive structure 26.

[0040] Passivation layer 25 may have the same material as passivation layer 24. Passivation layer 25 and passivation layer 24 may have the same material. When passivation layer 25 and passivation layer 24 have the same material, no interface is observed between them. When passivation layer 25 and passivation layer 24 have the same material, they can be considered as a single passivation layer.

[0041] Passivation layer 25 may have a different material than passivation layer 24. Passivation layer 25 and passivation layer 24 may have different materials. When passivation layer 25 and passivation layer 24 have different materials, an interface between passivation layer 25 and passivation layer 24 can be observed. When passivation layer 25 and passivation layer 24 have different materials, a convex surface of passivation layer 24 facing passivation layer 25 can be observed.

[0042] In semiconductor device 1, conductive structure 26 can be used as a gate conductor. In semiconductor device 1, conductive structure 26 can be configured to control 2DEGs in semiconductor layer 12. In semiconductor device 1, a voltage can be applied to conductive structure 26 to control 2DEGs in semiconductor layer 12. In semiconductor device 1, a voltage can be applied to conductive structure 26 to control 2DEGs in semiconductor layer 12 and beneath conductive structure 26. In semiconductor device 1, a voltage can be applied to conductive structure 26 to control the connection or disconnection between conductive structures 16.

[0043] In some other embodiments, the semiconductor device 1 may further include a doped semiconductor layer between the semiconductor layer 14 and the conductive structure 26. FIG. 1A (Not shown in the image). The doped semiconductor layer may contain doped III-V material. The doped semiconductor layer may contain p-type III-V material. The doped semiconductor layer may contain, for example, but not limited to, p-type III nitrides. The doped semiconductor layer may contain, for example, but not limited to, p-type GaN. The doped semiconductor layer can realize enhancement-mode semiconductor devices.

[0044] In some embodiments, conductive structure 16 can be used as a source conductor or a drain conductor of semiconductor device 1, and conductive structure 26 can be used as a gate conductor of semiconductor device 1. Although in FIG. 1A The conductive structure 26, which can be used as a gate conductor, is located between the conductive structure 16, which can be used as a source conductor and a drain conductor. However, in other embodiments of this disclosure, the conductive structure 26 and the conductive structure 16 may be configured differently according to design requirements.

[0045] FIG. 1B According to some embodiments of this disclosure, such as FIG. 1A An enlarged view of the structure of the dashed rectangle A shown.

[0046] like FIG. 1B As shown, semiconductor layer 14, conductive structure 16, spacer 18, passivation layer 22 and passivation layer 24 can be contained within the dashed rectangle A.

[0047] refer to FIG. 1BThe conductive structure 16 may have a sidewall 161. The sidewall 161 may have a relatively rough surface. The sidewall 161 may be adjacent to the spacer 18. The sidewall 161 may be adjacent to the surface 182 of the spacer 18. The surface 182 is relatively perpendicular to the passivation layer 22. In other words, the surface 182 and the surface 221 of the passivation layer 22 may form approximately a right angle. The sidewall 161 may be immediately adjacent to the passivation layer 22. The sidewall 161 may be immediately adjacent to the surface 221 of the passivation layer 22. The sidewall 161 may be immediately adjacent to the passivation layer 24.

[0048] The spacer 18 may have surfaces 181 and 182. Surface 181 may have a relatively smooth surface. Surface 181 may have a convex surface. Surface 181 may have a convex surface facing the passivation layer 24. Surface 182 may have a relatively smooth surface. Surface 182 may have a relatively flat surface. Surface 182 may have a relatively uniform surface. Surface 182 may be adjacent to the conductive structure 16. Surface 182 may be adjacent to the sidewall 161 of the conductive structure 16. Surface 182 may be in close proximity to the passivation layer 22. Surface 182 may be in close proximity to surface 221 of the passivation layer 22. Surface 182 may be in close proximity to the passivation layer 24.

[0049] The gap (or space) 20 may be defined by the conductive structure 16 and the spacer 18. The gap 20 may also be referred to as an empty region. The gap 20 may be defined between the sidewall 161 of the conductive structure 16 and the surface 182 of the spacer 18. The gap 20 may be defined between the relatively rough sidewall 161 of the conductive structure 16 and the relatively smooth surface 182 of the spacer 18.

[0050] The gap 20 may be defined by the conductive structure 16, the spacer 18, and the passivation layer 22. The gap 20 may be defined between the sidewall 161 of the conductive structure 16, the surface 182 of the spacer 18, and the surface 221 of the passivation layer 22. The gap 20 may be defined between the relatively rough sidewall 161 of the conductive structure 16, the relatively smooth surface 182 of the spacer 18, and the relatively smooth surface 221 of the passivation layer 22.

[0051] The passivation layer 22 may have a surface 221. Surface 221 may have a relatively smooth surface. Surface 221 may be in direct contact with the conductive structure 16. Surface 221 may be in direct contact with the spacer 18. Surface 221 may be in direct contact with the passivation layer 24. Surface 221, surface 181, and sidewall 161 may define a void 20.

[0052] A passivation layer 24 may be disposed on the passivation layer 22, the spacer 18, and the conductive structure 16. The passivation layer 24 may have a material different from that of the spacer 18. For example, the passivation layer 24 may have silicon oxide, and the spacer 18 may have silicon nitride. The passivation layer 24 may have a different material than the passivation layer 22. The passivation layer 24 may conformally cover the spacer 18. The passivation layer 24 may have a surface 241. Surface 241 may have a relatively smooth surface. Surface 241 may have a convex surface. Surface 241 may have a convex surface due to the application of the spacer 18. Surface 241 may have a convex surface similar to surface 181. Surface 241 may have a convex surface conformally to surface 181.

[0053] FIG. 1C It is based on some other embodiments of this disclosure, such as FIG. 1A An enlarged view of the structure within the dashed rectangle A shown.

[0054] like FIG. 1C As shown, semiconductor layer 14, conductive structure 16, spacer 18, passivation layer 22, and passivation layer 24 can be contained within the dashed rectangle A. Except... FIG. 1C The passivation layer 24 and the spacer 18 are made of the same material, FIG. 1C The structure shown is similar to FIG. 1B The structure is shown in the diagram. For example, passivation layer 24 and spacer 18 may be made of silicon nitride. When passivation layer 24 and spacer 18 have the same material, they can be considered as a single layer. When passivation layer 24 and spacer 18 have the same dielectric material, they can be considered as a single passivation layer.

[0055] The gap 20 may be defined by the conductive structure 16, the passivation layer 24, and the spacer 18. See also... FIG. 1C The gap 20 may be defined by the conductive structure 16, the passivation layer 24, and the spacer 18 and passivation layer 22.

[0056] Length T1 can be defined by the conductive structure 16 and the passivation layer 24. Length T1 can be defined by the sidewall 161 of the conductive structure 16 and the surface 241 of the passivation layer 24. Length T2 can be defined by the conductive structure 16 and the passivation layer 24. Length T2 can be defined by the sidewall 161 of the conductive structure 16 and the surface 241 of the passivation layer 24.

[0057] Length T1 can be different from length T2. Length T1 can be shorter than length T2. Due to the application of spacer 18, length T1 can be shorter than length T2. Length T1 can be shorter than length T2 because spacer 18 has a convex profile. Length T1 can be shorter than length T2 because spacer 18 has a convex profile and passivation layer 24 conformally covers spacer 18.

[0058] FIG. 1D It is based on some other embodiments of this disclosure, such as FIG. 1A An enlarged view of the structure within the dashed rectangle A shown.

[0059] like FIG. 1D As shown, semiconductor layer 14, conductive structure 16, spacer 18, passivation layer 22, and passivation layer 24 can be contained within the dashed rectangle A. Except for the elimination of the gap between conductive structure 16 and spacer 18, FIG. 1D The structure shown is similar to FIG. 1B The structure shown.

[0060] Surface 182 may have a relatively rough surface. Surface 182 may have a relatively irregular surface. Surface 182 may have a relatively uneven surface. Surface 182 may be adjacent to the conductive structure 16. Surface 182 may be adjacent to the sidewall 161 of the conductive structure 16. Surface 182 may be in contact with the sidewall 161 of the conductive structure 16. Surface 182 may be in continuous contact with the sidewall 161 of the conductive structure 16. Surface 182 may be in continuous contact with the sidewall 161 of the conductive structure 16, such that there are no gaps between them. Surface 182 may substantially overlap with the sidewall 161. Surface 182 may substantially overlap with the sidewall 161, such that there are no gaps between them. Surface 182 and sidewall 161 may together form the interface or boundary between the spacer 18 and the conductive structure 16.

[0061] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D , FIG. 2E , FIG. 2F and FIG. 2G Several operations for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0062] refer to FIG. 2AA substrate 10 is provided. In some embodiments, substrate 10 may comprise a silicon substrate. In some embodiments, substrate 10 may be an intrinsic silicon substrate. In some embodiments, substrate 10 may be doped with a dopant. In some embodiments, substrate 10 may comprise a p-type semiconductor substrate. In some embodiments, substrate 10 may be doped with at least one of boron (B) and gallium (Ga) to form a p-type semiconductor substrate. In some embodiments, substrate 10 may comprise an n-type semiconductor substrate. In some embodiments, substrate 10 may be doped with at least one of phosphorus (P) and arsenic (As) to form an n-type semiconductor substrate.

[0063] In some embodiments, a semiconductor layer 12 is disposed on a substrate 10. In some embodiments, the semiconductor layer 12 may be formed by chemical vapor deposition (CVD) and / or another suitable deposition step. In some embodiments, the semiconductor layer 12 may be formed on the substrate 10 by CVD and / or another suitable deposition step. In some embodiments, a buffer layer may be disposed between the substrate 10 and the semiconductor layer 12. The buffer layer may be formed by CVD and / or another suitable deposition step.

[0064] In some embodiments, semiconductor layer 14 is disposed on semiconductor layer 12. In some embodiments, semiconductor layer 14 can be formed by CVD and / or another suitable deposition step. In some embodiments, semiconductor layer 14 can be formed on semiconductor layer 12 by CVD and / or another suitable deposition step. It should be noted that semiconductor layer 14 can be formed after semiconductor layer 12 is formed. When semiconductor layer 14 is disposed on semiconductor layer 12, a heterojunction can be formed. The band gap of semiconductor layer 14 can be larger than the band gap of semiconductor layer 12. Due to the polarization phenomenon of the heterojunction formed between semiconductor layer 14 and semiconductor layer 12, 2DEG can be formed in semiconductor layer 12. Due to the polarization phenomenon of the heterojunction formed between semiconductor layer 14 and semiconductor layer 12, 2DEG can be formed in semiconductor layer 12 and close to the interface between semiconductor layer 12 and semiconductor layer 14.

[0065] In some embodiments, a passivation layer 22 is disposed on the semiconductor layer 14. In some embodiments, the passivation layer 22 can be formed by a deposition step. In some embodiments, the passivation layer 22 can be formed on the semiconductor layer 14 by CVD and / or another suitable deposition step.

[0066] refer to FIG. 2BA conductive structure 16 is disposed on the passivation layer 22. The conductive structure 16 may be disposed on the semiconductor layer 12. The conductive structure 16 may be surrounded by the semiconductor layer 14 by etching a portion of it. The conductive structure 16 may be surrounded by the passivation layer 22 by etching a portion of it. In some embodiments, the conductive layer 16 may be formed by CVD and / or another suitable deposition step. In some embodiments, the conductive structure 16 may be formed on the passivation layer 22 by CVD and / or another suitable deposition step and patterning.

[0067] Reference FIG. 2C Spacers 18 are formed. In some embodiments, spacers 18 may be disposed on passivation layer 22. In some embodiments, spacers 18 may be disposed adjacent to conductive structure 16. In some embodiments, spacers 18 may be formed by CVD and / or another suitable deposition step. In some embodiments, spacers 18 may be formed on passivation layer 22 by CVD and / or another suitable deposition step. Spacers 18 may be formed to have surface 181. Spacers 18 may be patterned to have surface 181. It should be noted that surface 181 may have a convex surface.

[0068] refer to FIG. 2D It is possible to do as FIG. 2C Heat treatment or thermal operation is performed on the structure shown. Thermal operation may include, for example, but not limited to, annealing techniques (e.g., rapid thermal annealing (RTA)) or other suitable techniques. In some embodiments, thermal operation may be performed in a temperature range from approximately 600°C to approximately 800°C.

[0069] In some other embodiments, the thermal operation can be performed in a temperature range from about 650°C to about 750°C. In some other embodiments, the thermal operation can be performed at about 700°C. In some embodiments, the thermal operation can last for a duration of about 10 seconds to about 50 seconds. In some other embodiments, the thermal operation can last for a duration of about 20 seconds to 40 seconds. In some other embodiments, the thermal operation can be performed for about 30 seconds.

[0070] Also refer to FIG. 2DThe annealing process alters the profile of the conductive structure 16. In some embodiments, the profile of the conductive structure 16 may be altered due to the annealing operation. Due to the annealing operation, the conductive structure 16 may have relatively rough sidewalls 161. The spacer 18 may be unaffected by the annealing operation. Even if the annealing operation is performed, the spacer 18 may have a relatively smooth surface 181. Even if the annealing operation is performed, the spacer 18 may have a relatively smooth surface 182. The profile of the spacer 18 may be unaffected by the annealing operation. It should be noted that even if the annealing operation is performed, the surface 181 of the spacer 18 may be raised. See also... FIG. 2D A gap 20 is formed. The gap 20 may be formed by an annealing operation. The gap 20 may be defined by the spacer 18 and the conductive structure 16. The gap 20 may be defined by the surface 182 of the spacer 18 and the sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the surface 182 of the spacer 18 and the sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the relatively smooth surface 182 of the spacer 18 and the relatively rough sidewall 161 of the conductive structure 16. The gap 20 may be enclosed by the surface 182 of the spacer 18 and the sidewall 161 of the conductive structure 16. The gap 20 may be enclosed by the relatively smooth surface 182 of the spacer 18 and the relatively rough sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the surface 182 of the spacer 18 and the sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the relatively smooth surface 182 of the spacer 18 and the relatively rough sidewall 161 of the conductive structure 16. In some embodiments, the gap 20 may be defined by the passivation layer 22, the spacer 18, and the conductive structure 16. The gap 20 may be defined by the passivation layer 22, the surface 182 of the spacer 18, and the sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the passivation layer 22, the surface 182 of the spacer 18, and the sidewall 161 of the conductive structure 16. The gap 20 may be surrounded by the passivation layer 22, the relatively smooth surface 182 of the spacer 18, and the relatively rough sidewall 161 of the conductive structure 16. The gap 20 can be enclosed by the passivation layer 22, the surface 182 of the spacer 18, and the sidewall 161 of the conductive structure 16. The gap 20 can be enclosed by the passivation layer 22, the relatively smooth surface 182 of the spacer 18, and the relatively rough sidewall 161 of the conductive structure 16. The gap 20 can be surrounded by the passivation layer 22, the surface 182 of the spacer 18, and the sidewall 161 of the conductive structure 16. The gap 20 can be surrounded by the passivation layer 22, the relatively smooth surface 182 of the spacer 18, and the relatively rough sidewall 161 of the conductive structure 16.

[0071] refer to FIG. 2EA passivation layer 24 is formed. The passivation layer 24 can be formed by CVD and / or another suitable deposition step. The passivation layer 24 can be disposed on the passivation layer 22. The passivation layer 24 can be disposed on the spacer 18. The passivation layer 24 can be disposed on the conductive structure 16. The passivation layer 24 can conformally cover the passivation layer 22. The passivation layer 24 can conformally cover the spacer 18. The passivation layer 24 can conformally cover the conductive structure 16. The passivation layer 24 can be formed to have a surface 241. The surface 241 can have a relatively smooth surface. The surface 241 can have a convex surface. The surface 241 can have a convex surface similar to surface 181.

[0072] Reference FIG. 2F A conductive layer 26' is formed. The conductive layer 26' may be disposed on the passivation layer 24. The conductive layer 26' may be disposed on the semiconductor layer 14. The conductive layer 26' may be surrounded by the passivation layer 22 by etching a portion of the passivation layer 22. In some embodiments, the conductive layer 26' may be formed by CVD and / or another suitable deposition step. In some embodiments, the conductive layer 26' may be formed on the passivation layer 24 by CVD and / or another suitable deposition step.

[0073] Reference FIG. 2G This forms a conductive structure 26. The conductive structure 26 can be patterned. This can be achieved through etching. FIG. 2F A portion of the conductive layer 26' shown is used to pattern the conductive structure 26. It should be noted that no residue is left on the surface 241 when the conductive structure 26 is formed. No residue is left on the convex surface 241 when the conductive structure 26 is formed. (Source: FIG. 2F No residue of the conductive layer 26' shown will remain on surface 241. It should be noted that no residue can adhere to surface 241 when the conductive structure 26 is formed. No residue adheres to the convex surface 241 when the conductive structure 26 is formed. FIG. 2F Residues from the conductive layer 26' shown must not adhere to surface 241. Surface 241 can be cleaned after patterning the conductive structure 26.

[0074] As semiconductor devices are scaled down, defects such as residues that cannot be completely removed during manufacturing can affect the electrical performance of the semiconductor devices. Such defects should be prevented. Since spacer 18 can withstand the temperatures of the annealing process during manufacturing, the profile of spacer 18 can remain unchanged. Because the profile of spacer 18 is unaffected by the annealing process, processes such as passivation layer formation can be performed such that passivation layer 24 conformally covers spacer 18, and neither passivation layer 24 nor spacer 18 is recessed into the sidewalls of conductive structure 16. Because the profile of spacer 18 is unaffected by the annealing process, subsequent processes such as gate conductor formation and field plate formation can be performed without leaving residues on the sidewalls adjacent to conductive structure 16. In other words, when excess material is etched to form conductive structure 26, no residue is left on passivation layer 24 because it has a concave surface near the sidewalls of conductive structure 16.

[0075] FIG. 3A , FIG. 3B , FIG. 3C , FIG. 3D , FIG. 3E and FIG. 3F Several operations for manufacturing a semiconductor device according to certain other embodiments of this disclosure are illustrated.

[0076] refer to FIG. 3A A structure including a substrate 10, a semiconductor layer 12, a semiconductor layer 14, a passivation layer 22, and a conductive structure 16 is provided. FIG. 3A (Not shown in the image). This structure can be compared with the reference. FIG. 2B The structures illustrated and described are the same or similar, and can be referenced. FIG. 2A and FIG. 2B The illustrated and described operations are used to manufacture it.

[0077] refer to FIG. 3B , can FIG. 3A The structure shown is subjected to heat treatment or hot operation. Hot operation may include, but is not limited to, annealing techniques (e.g., RTA technique) or other suitable techniques.

[0078] In some embodiments, the thermal operation can be performed in a temperature range from about 600°C to about 800°C. In some other embodiments, the thermal operation can be performed in a temperature range from about 650°C to about 750°C. In some other embodiments, the thermal operation can be performed at about 700°C. In some embodiments, the thermal operation can last for a duration from about 10 seconds to about 50 seconds. In some other embodiments, the thermal operation can last for a duration from about 20 seconds to 40 seconds. In some other embodiments, the thermal operation can be performed for about 30 seconds.

[0079] Thermal operation or heat treatment can alter the conductive structure.16 For example... FIG. 3B As shown, the contour of the conductive structure 16 is altered through thermal processing. After thermal processing, the sidewalls of the conductive structure 16 can shrink to form an uneven surface 161. Due to thermal processing, the conductive structure 16 can have relatively rough sidewalls 161.

[0080] Reference FIG. 3C A spacer 18 is formed. The spacer 18 can be disposed on the passivation layer 22. The spacer 18 can be disposed adjacent to the conductive structure 16.

[0081] Spacer 18 can be formed by, for example, but not limited to, CVD or other suitable techniques. Spacer 18 can be formed to have a surface 181. Spacer 18 can be patterned to have a curved surface 181. Surface 181 can have a convex surface.

[0082] Spacer 18 may contact the sidewall 161 of conductive structure 16. Spacer 18 may generally contact the sidewall 161 of conductive structure 16. Spacer 18 may directly contact the sidewall 161 of conductive structure 16. Spacer 18 may be in continuous contact with the sidewall 161 of conductive structure 16. Spacer 18 may be engaged with the sidewall 161 of conductive structure 16. Spacer 18 and the sidewall 161 of conductive structure 16 may be tightly engaged. Spacer 18 may be formed to fit tightly within the uneven sidewall 161 of conductive structure 16. Spacer 18 may be formed to match the uneven sidewall 161 of conductive structure 16.

[0083] exist FIG. 3D , FIG. 3E and FIG. 3F The operations performed in the reference can be compared with those in the reference. FIG. 2E , FIG. 2F and FIG. 2G The operations described and explained are the same or similar.

[0084] It should be noted that no residue is left on surface 241 when the conductive structure 26 is formed. No residue is left on the convex surface 241 when the conductive structure 26 is formed. FIG. 3E No residue of the conductive layer 26' shown will remain on surface 241. It should be noted that no residue can adhere to surface 241 when the conductive structure 26 is formed. No residue adheres to the convex surface 241 when the conductive structure 26 is formed. FIG. 3E Residues from the conductive layer 26' shown must not adhere to surface 241. Surface 241 can be cleaned after patterning the conductive structure 26.

[0085] FIG. 4A This is a side view of a semiconductor device 2 according to some embodiments of the present disclosure.

[0086] like FIG. 4A As shown, semiconductor device 2 is similar to FIG. 1A The semiconductor device 1 shown is different in that... FIG. 4A The semiconductor device 2 shown does not include any spacers. The semiconductor device 2 may not have any spacers adjacent to the conductive structure 16. According to some embodiments of this disclosure... FIG. 4A The detailed structure of the dashed rectangle B in the image is shown in... FIG. 4B The diagram is shown in the image.

[0087] FIG. 4B According to some embodiments of this disclosure, such as FIG. 4A An enlarged view of the structure of the dashed rectangle B shown.

[0088] like FIG. 4B As shown, passivation layer 24 can be disposed on passivation layer 22. Passivation layer 24 can be disposed on conductive structure 16. Passivation layer 24 can cover conductive structure 16. Passivation layer 24 can have surface 242. Surface 242 can have a relatively rough surface. Surface 242 can have an uneven surface. Surface 242 can have an uneven surface because the sidewall 161 of conductive structure 16 has a relatively rough surface. Surface 242 can have an uneven surface. Surface 242 can have an uneven surface because the sidewall 161 of conductive structure 16 has a relatively rough surface and passivation layer 24 conformally covers the sidewall 161 of conductive structure 16.

[0089] Reference FIG. 4B Residue 28 is disposed on surface 242. Residue 28 can remain on surface 242. Residue 28 can adhere to surface 242. Residue 28 can have a similar appearance to... FIG. 4A The conductive structure 26 shown is made of the same material. Residue 28 may originate from... FIG. 4A The conductive structure 26 is shown. It should be noted that residue 28 can affect electrical performance. Residue 28 may affect electrical performance when the semiconductor device 2 is scaled down.

[0090] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5D , FIG. 5E and FIG. 5F Several operations for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated. FIG. 5A , FIG. 5B , FIG. 5C, FIG. 5D , FIG. 5E and FIG. 5F Describes the use of manufacturing FIG. 4A Several operations of the semiconductor device 2 shown.

[0091] refer to FIG. 5A It provides a substrate 10, a semiconductor layer 12, a semiconductor layer 14, and a passivation layer 22. Regarding... FIG. 2A The above description of the operation can be applied to FIG. 5A .

[0092] refer to FIG. 5B The conductive structure 16 is disposed on the passivation layer 22. Regarding... FIG. 2B The above description of the operation can be applied to FIG. 5B .

[0093] Reference FIG. 5C The process involves heat treatment. In some embodiments, a thermal operation may be performed. In some embodiments, an annealing operation may be performed. In some embodiments, a real-time annealing (RTA) operation may be performed. In some embodiments, the annealing operation may be performed at a temperature between about 600°C and 800°C. In some embodiments, the annealing operation may be performed at a temperature between about 650°C and 750°C. In some embodiments, the annealing operation may be performed at a temperature of about 700°C. In some embodiments, the annealing operation may last for a duration between about 10 seconds and 50 seconds. In some embodiments, the annealing operation may last for a duration between about 20 seconds and 40 seconds. In some embodiments, the annealing operation may last for a duration of about 30 seconds.

[0094] Same reference FIG. 5C The conductive structure 16 may be affected by the annealing operation, which alters the profile of the conductive structure 16. In some embodiments, the profile of the conductive structure 16 may be altered due to the annealing operation. As a result of the annealing operation, the conductive structure 16 may have relatively rough sidewalls 162. It should be noted that after the annealing operation, the sidewalls 162 of the conductive structure 16 may have an uneven surface.

[0095] refer to FIG. 5D A passivation layer 24 is formed. The passivation layer 24 can be formed by CVD and / or another suitable deposition step. The passivation layer 24 can be disposed on the passivation layer 22. The passivation layer 24 can be disposed on the conductive structure 16. The passivation layer 24 can conformally cover the passivation layer 22. The passivation layer 24 can conformally cover the conductive structure 16. The passivation layer 24 can be formed to have a surface 242. The surface 242 can have a flat surface. The surface 242 can have a non-flat surface similar to the sidewall 162.

[0096] ReferenceFIG. 5E A conductive layer 26' is formed. The conductive layer 26' may be disposed on the passivation layer 24. The conductive layer 26' may be disposed on the semiconductor layer 14. The conductive layer 26' may be surrounded by the passivation layer 22 by etching a portion of the passivation layer 22. In some embodiments, the conductive layer 26' may be formed by CVD and / or another suitable deposition step. In some embodiments, the conductive layer 26' may be formed on the passivation layer 24 by CVD and / or another suitable deposition step.

[0097] Reference FIG. 5F This forms a conductive structure 26. The conductive structure 26 can be patterned. This can be achieved through etching. FIG. 5E A portion of the conductive layer 26' shown is used to pattern the conductive structure 26. Residue 28 can be etched... FIG. 5E The conductive layer shown is formed at time 26'.

[0098] It should be noted that when the conductive structure 26 is formed, residue 28 may be left on the surface 242. Residue 28 may remain on the uneven surface 242 when the conductive structure 26 is formed. FIG. 5E Residue 28 of the conductive layer 26' shown may remain on surface 242. It should be noted that residue 28 may adhere to surface 242 when the conductive structure 26 is formed. Residue 28 may also adhere to uneven surface 242 when the conductive structure 26 is formed. FIG. 5E The residue 28 of the conductive layer 26' shown can be attached to the surface 242.

[0099] As used herein, for ease of description, spatially related terms such as “below,” “under,” “lower part,” “upper,” “upper part,” “lower part,” “left side,” “right side,” etc., may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations shown in the figures, spatially related terms are intended to cover different orientations of the apparatus in use or operation. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptive symbols used herein may be interpreted accordingly. It should be understood that when a component is “connected” or “coupled” to another component, the component may be directly connected or coupled to the other component, or there may be an intermediate component.

[0100] The terms “approximately,” “substantially,” “largely,” and “about” as used herein are used to describe and account for small variations. When used in conjunction with an event or situation, the term can refer to the exact occurrence of the event or situation, or approximately the occurrence of the event or situation. As used herein, with respect to a given value or range, the term “about” generally refers to a range of ±10%, ±5%, ±1%, or ±0.5% of the given value or range. This range can be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed in this disclosure include endpoints. The term “largely coplanar” can refer to two surfaces located within a few micrometers (μm) along the same plane, such as within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to “largely” identical values ​​or characteristics, the term can refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the average value.

[0101] The foregoing briefly describes several embodiments and details of this disclosure. The embodiments described in this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or obtain the same or similar advantages introduced in the embodiments of this disclosure. These equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer; An ohmic contact is disposed on the first nitride semiconductor layer; as well as A spacer is disposed adjacent to the sidewall of the ohmic contact, wherein the sidewall of the ohmic contact has a relatively rough surface; A first passivation layer is disposed between the second nitride semiconductor layer and the spacer, and the relatively rough surface of the sidewall of the ohmic contact is located above the first passivation layer. The surface of the spacer on the sidewall away from the ohmic contact is a smooth convex surface.

2. The semiconductor device according to claim 1, characterized in that, The surface of the spacer adjacent to the sidewall in contact with the ohm has a relatively smooth surface.

3. The semiconductor device according to claim 1, characterized in that, The surface of the spacer adjacent to the sidewall in ohmic contact is relatively rougher than the surface of the spacer away from the sidewall in ohmic contact.

4. The semiconductor device according to claim 3, characterized in that, The surface of the spacer adjacent to the sidewall in ohmic contact is substantially in contact with the sidewall in ohmic contact.

5. The semiconductor device according to claim 1, characterized in that, The spacer is configured to contact the surface of the first passivation layer, and the surface of the first passivation layer has a relatively smooth surface.

6. The semiconductor device according to claim 5, characterized in that, A gap is defined between the sidewall of the ohmic contact, the spacer, and the surface of the first passivation layer.

7. The semiconductor device according to claim 1, characterized in that, It also includes a second passivation layer disposed on the first passivation layer and covering the ohmic contact and the spacer.

8. The semiconductor device according to claim 1, characterized in that, A gap is defined between the sidewall of the ohmic contact and the surface of the spacer.

9. A semiconductor device, characterized in that, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer; An ohmic contact is disposed on the first nitride semiconductor layer; A first passivation layer is disposed on the second nitride semiconductor layer; as well as A second passivation layer is disposed on the ohmic contact and the first passivation layer, wherein the ohmic contact has a sidewall located between the first passivation layer and the second passivation layer, and the sidewall has a relatively rough surface; It also includes a spacer located between the first passivation layer and the second passivation layer, and adjacent to the sidewall of the ohmic contact; the surface of the spacer away from the sidewall of the ohmic contact is a smooth convex surface.

10. The semiconductor device according to claim 9, characterized in that, The ohmic contact is configured to contact the surface of the first passivation layer, and the surface of the first passivation layer has a relatively smooth surface.

11. The semiconductor device according to claim 9, characterized in that, The second passivation layer extends from the first passivation layer to a position above the sidewall of the ohmic contact.

12. The semiconductor device according to claim 9, characterized in that, The surface of the second passivation layer near the sidewall of the ohmic contact has a relatively smooth surface.

13. The semiconductor device according to claim 9, characterized in that, The second passivation layer contacts and covers the surface of the spacer.

14. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor stack is provided, the semiconductor stack including a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer has a band gap greater than that of the first nitride semiconductor layer; A first ohmic contact is formed on the first nitride semiconductor layer; A spacer is formed that is attached to the sidewall of the first ohmic contact; Annealing is performed before or after the formation of the spacer, such that the profile of the first ohmic contact is altered by the annealing operation, and the sidewalls of the first ohmic contact have a relatively rough surface; and A second ohmic contact is formed after the spacer is formed; the surface of the spacer's sidewall away from the first ohmic contact is a smooth convex surface.

15. The method according to claim 14, characterized in that, After annealing, the surface of the spacer adjacent to the sidewall in contact with the first ohm has a relatively smooth surface.

16. The method according to claim 14, characterized in that, After annealing, the surface of the spacer adjacent to the sidewall in the first ohmic contact is relatively rougher than the surface of the spacer away from the sidewall in the first ohmic contact.

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