Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate and includes a titanium nitride barrier layer and a titanium aluminum layer. The titanium aluminum layer is disposed on the titanium nitride barrier layer, and the thickness of the titanium aluminum layer is between twice and three times the thickness of the titanium nitride barrier layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device with a gate structure and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor integrated circuit technology, the circuit designs in newer products are smaller and more complex than those of previous generations. To meet the demands of innovative products, the number and density of functional devices per chip area are increasing, and the size of each device must be correspondingly reduced. Generally speaking, polysilicon is commonly used as the gate electrode in semiconductor devices such as metal oxide semiconductors (MOS). However, with the trend toward shrinking semiconductor device sizes, conventional polysilicon gates face performance issues such as boron penetration and the inevitable depletion effect. These issues increase the effective thickness of the gate dielectric layer, reduce gate capacitance, and degrade the device's driving force. Therefore, work function metals suitable for pairing with high-k gate dielectrics are being used to replace traditional polysilicon gates as control electrodes. Typically, metal gate stacks with work function metals and high-k gate dielectrics are formed using a replacement metal gate (RMG) fabrication process. The performance of the RMG fabrication process directly affects the quality of the metal gate and the operating performance of the corresponding semiconductor device. Therefore, improving the manufacturing yield of semiconductor devices by modifying the gate structure design and / or the manufacturing process design associated with the RMG fabrication process has long been a research topic for researchers in this field. Summary of the Invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof, which improves related manufacturing process problems and increases production yield by controlling the thickness ratio of the titanium aluminum layer and the titanium nitride barrier layer in the gate structure.

[0004] One embodiment of the present invention provides a semiconductor device comprising a substrate and a gate structure. The gate structure is disposed on the substrate and includes a titanium nitride barrier layer and a titanium aluminum (TiA) layer. The TiA layer is disposed on the TiN barrier layer, and the TiA layer has a thickness ranging from twice to three times the thickness of the TiN barrier layer.

[0005] One embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a gate structure on a substrate, the gate structure comprising a titanium nitride barrier layer and a titanium aluminum layer. The titanium aluminum layer is disposed on the titanium nitride barrier layer, and the thickness of the titanium aluminum layer is between twice and three times the thickness of the titanium nitride barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0007] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0008] Figures 3 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein

[0009] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0010] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0011] Figure 6 for Figure 5 Schematic diagram of the situation afterwards.

[0012] Figure 7 FIG. 4 is a schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0013] Description of main component symbols

[0014] 10 base

[0015] 22 Gate dielectric layer

[0016] 24 Bottom barrier layer

[0017] 32 spacer structure

[0018] 34 dielectric layer

[0019] 42 work function layer

[0020] 44 Titanium nitride layer

[0021] 44' Titanium Nitride Barrier Layer

[0022] 45 middle layer

[0023] 46 Titanium layer

[0024] 47 Titanium-aluminum layer

[0025] 48 aluminum layers

[0026] 100 semiconductor devices

[0027] GS gate structure

[0028] S11 Step

[0029] S12 Step

[0030] S13 Step

[0031] S14 Step

[0032] TK1 thickness

[0033] TK2 thickness

[0034] TK3 thickness

[0035] TK4 thickness

[0036] TK5 thickness

[0037] TK6 thickness

[0038] TK7 thickness

[0039] TR Groove

[0040] Z direction DETAILED DESCRIPTION

[0041] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0042] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0043] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0044] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0045] See also Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. Figure 1As shown, the semiconductor device 100 includes a substrate 10 and a gate structure GS. The gate structure GS is disposed on the substrate 10 and includes titanium nitride (TiN x ) barrier layer 44' and a titanium aluminide (TiAl x ) layer 47. The titanium aluminum layer 47 is disposed on the titanium nitride barrier layer 44', and the thickness of the titanium aluminum layer 47 (eg Figure 1 The thickness TK3 shown in FIG is between the thickness of the titanium nitride barrier layer 44 ′ (eg Figure 1 The thickness TK3 of the titanium aluminum layer 47 is preferably between twice the thickness TK1 (shown in FIG. 1 ) and three times the thickness of the titanium nitride barrier layer 44' (e.g., thickness TK1). In other words, the titanium aluminum layer 47 is thicker than the titanium nitride barrier layer 44', and the ratio between the thickness TK3 of the titanium aluminum layer 47 and the thickness TK1 of the titanium nitride barrier layer 44' is controlled. For example, the thickness TK3 of the titanium aluminum layer 47 may be greater than or equal to twice the thickness TK1 of the titanium nitride barrier layer 44' and less than or equal to three times the thickness TK1 of the titanium nitride barrier layer 44' (i.e., the ratio of thickness TK3 to thickness TK1 may be between 2 and 3). This can improve the manufacturing process associated with forming the gate structure GS and thereby improve the production yield of the semiconductor device 100.

[0046] In some embodiments, a vertical direction (eg Figure 1 The direction Z shown in FIG. 1 may be considered the thickness direction of the substrate 10. The substrate 10 may have an upper surface and a bottom surface opposite each other in the direction Z, and the gate structure GS may be disposed on one side of the upper surface, but is not limited thereto. A horizontal direction substantially perpendicular to the direction Z may be substantially parallel to the upper surface and / or the bottom surface of the substrate 10, but is not limited thereto. Furthermore, as described herein, the distance in the direction Z between a relatively higher position or / and component in the vertical direction (e.g., the direction Z) and the bottom surface of the substrate 10 may be greater than the distance in the direction Z between a relatively lower position or / and component in the direction Z and the bottom surface of the substrate 10. The lower portion or bottom portion of each component may be closer to the bottom surface of the substrate 10 in the direction Z than the upper portion or top portion of the component. A component above a component may be considered to be relatively farther from the bottom surface of the substrate 10 in the direction Z, while a component below a component may be considered to be relatively closer to the bottom surface of the substrate 10 in the direction Z, but is not limited thereto.

[0047] In some embodiments, the substrate 10 may include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrates formed of suitable materials and / or structures. The gate structure GS, a portion of the substrate 10, and other components formed in or on the substrate 10 (e.g., source / drain structures, not shown) may form a semiconductor unit (e.g., a transistor unit), but is not limited thereto. In some embodiments, the gate structure GS may be formed by a replacement metal gate (RMG) fabrication process, but is not limited thereto. For example, the semiconductor device 100 may further include a spacer structure 32 and a dielectric layer 34 disposed on the substrate 10. The spacer structure 32 may surround a trench TR in the substrate 10. The trench TR may be formed by removing a dummy gate, and the gate structure GS may be disposed in the trench TR, but is not limited thereto. The spacer structure 32 may include a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials, and the dielectric layer 34 may include silicon oxide or other suitable insulating materials.

[0048] In some embodiments, the gate structure GS may further include a gate dielectric layer 22, a bottom barrier layer 24, and a work function layer 42. The work function layer 42 may be disposed below the titanium nitride barrier layer 44', the bottom barrier layer 24 may be disposed below the work function layer 42, and the gate dielectric layer 22 may be disposed below the bottom barrier layer 24. The gate dielectric layer 22 may include a high-k dielectric layer such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k dielectric materials. The bottom barrier layer 24 may include tantalum nitride, titanium nitride, or other suitable conductive barrier materials, and the work function layer 42 may include a single layer or multiple layers of work function materials, such as tantalum nitride, titanium nitride, titanium carbide, titanium aluminum alloy, titanium aluminum carbide, or other suitable N-type and / or P-type work function materials.

[0049] In some embodiments, the work function layer 42, the titanium nitride barrier layer 44', and the titanium aluminum layer 47 may each have a U-shaped structure in a cross-sectional view of the gate structure GS. The bottom barrier layer 24 and the gate dielectric layer 22 may be formed before the aforementioned dummy gate and may each have a straight-line structure in a cross-sectional view of the gate structure GS, but this is not limiting. In some embodiments, the bottom barrier layer 24 and the gate dielectric layer 22 may be formed after the trench TR is formed and may each have a U-shaped structure in a cross-sectional view of the gate structure GS. In some embodiments, the gate structure GS may be a structure formed by sequentially stacking the gate dielectric layer 22, the bottom barrier layer 24, the work function layer 42, the titanium nitride barrier layer 44', and the titanium aluminum layer 47 in a direction Z. Therefore, the titanium aluminum layer 47 may be considered the topmost layer in the gate structure GS.

[0050] In some embodiments, the gate structure GS may further include an intermediate layer 45 disposed between the titanium aluminum layer 47 and the titanium nitride barrier layer 44'. The intermediate layer 45 may directly connect the titanium aluminum layer 47 and the titanium nitride barrier layer 44' and may include titanium and nitrogen. In some embodiments, the nitrogen concentration of the intermediate layer 45 may gradually decrease in a vertical direction (e.g., direction Z) extending toward the interface between the intermediate layer 45 and the titanium aluminum layer 47. The nitrogen concentration of the intermediate layer 45 may be lower than the nitrogen concentration of the titanium nitride barrier layer 44', and the nitrogen concentration may be expressed as an atomic percentage of nitrogen or other suitable concentration units. Furthermore, the thickness of the intermediate layer 45 may be less than the thickness TK1 of the titanium nitride barrier layer 44' and the thickness TK3 of the titanium aluminum layer 47. The intermediate layer 45 may be considered a transition layer for the nitrogen in the titanium nitride barrier layer 44' to extend outward, but the present invention is not limited thereto. In some embodiments, the titanium nitride barrier layer 44′ and the intermediate layer 45 can be considered as a titanium nitride barrier layer. Therefore, the titanium nitride barrier layer can directly contact the titanium aluminum layer 47, and the nitrogen concentration of an upper portion of the titanium nitride barrier layer (e.g., the intermediate layer 45) gradually decreases in a vertical direction (e.g., direction Z) extending toward the interface between the titanium nitride barrier layer and the titanium aluminum layer 47. The thickness TK3 of the titanium aluminum layer 47 can be greater than or equal to the thickness of the titanium nitride barrier layer (e.g., the thickness TK3 of the titanium aluminum layer 47). Figure 1 and is less than or equal to three times the thickness TK2 of the titanium nitride barrier layer, but is not limited thereto.

[0051] See also Figures 1 to 6 . Figure 2 FIG1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3 to 6 The figure shows a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 4 Draws Figure 3 Schematic diagram of the situation afterwards, Figure 5 Draws Figure 4 Schematic diagram of the situation afterwards, Figure 6 Draws Figure 5 The following diagram shows the situation: Figure 1 can be considered as depicting Figure 6 The following is a schematic diagram of the situation, but it is not limited to this. Figure 1 As shown, the method for fabricating a semiconductor device of this embodiment may include the following steps: forming a gate structure GS on a substrate 10, wherein the gate structure GS includes a titanium nitride barrier layer 44' and a titanium aluminum layer 47. The titanium aluminum layer 47 is disposed on the titanium nitride barrier layer 44', and the thickness TK3 of the titanium aluminum layer 47 is between twice and three times the thickness TK1 of the titanium nitride barrier layer 44'.

[0052] To further illustrate, the method for manufacturing the semiconductor device of this embodiment may include but is not limited to the following steps. First, Figure 2 and Figure 3 As shown, after forming the spacer structure 32, the dielectric layer 34, and the trench TR on the substrate 10, step S11 is performed to form a titanium nitride layer 44 and a titanium layer 46 on the substrate 10, and the titanium layer 46 is formed on the titanium nitride layer 44. In some embodiments, the gate dielectric layer 22, the bottom barrier layer 24, and a dummy gate (not shown) can be first formed on the substrate 10, and then the spacer structure 32 and the dielectric layer 34 are formed and the dummy gate is removed to form the trench TR. The work function layer 42, the titanium nitride layer 44, and the titanium layer 46 can be formed after the trench TR is formed and can each be at least partially formed in the trench TR, but the present invention is not limited thereto. The above-mentioned manufacturing method can be regarded as a high-k first manufacturing process, but the manufacturing method of the gate structure of the present invention is not limited thereto. In some embodiments, a dummy gate (not shown), a spacer structure 32, and a dielectric layer 34 may be first formed on the substrate 10, and then the dummy gate is removed to form a trench TR. After the trench TR is formed, a gate dielectric layer 22, a bottom barrier layer 24, a work function layer 42, a titanium nitride layer 44, and a titanium layer 46 are formed. The gate dielectric layer 22, the bottom barrier layer 24, the work function layer 42, the titanium nitride layer 44, and the titanium layer 46 may be respectively at least partially formed in the trench TR, and this manufacturing method may be regarded as a high-k last manufacturing process, but is not limited to this.

[0053] In some embodiments, by controlling the relative thickness of the titanium layer 46 and the titanium nitride layer 44, the thickness of the titanium layer 46 can be increased while the titanium nitride layer 44 has a certain thickness to maintain its barrier effect. This allows sufficient titanium to inter-diffusion with the aluminum in the aluminum layer to form the desired titanium-aluminum layer after the aluminum layer is subsequently formed on the titanium layer 46. In contrast, if the thickness ratio of the titanium nitride layer 44 is relatively high, the titanium in the titanium layer 46 is likely to be restricted by the titanium nitride layer 44 and unable to effectively inter-diffusion with the aluminum in the aluminum layer, resulting in uneven surface, thickness, and / or composition of the formed titanium-aluminum layer, which can lead to related process problems, such as dishing during the chemical mechanical polishing process of the aluminum layer and / or the formation of voids in the aluminum layer. Therefore, while controlling the thickness ratio of the titanium nitride layer 44 to a certain ratio to provide the desired barrier effect, increasing the thickness ratio of the titanium layer 46 can improve the above-mentioned manufacturing process problems, thereby achieving the effects of improving the manufacturing process yield, enhancing the electrical performance of the semiconductor device, and / or enhancing the reliability of the semiconductor device. Therefore, in some embodiments, the thickness of the titanium layer 46 (e.g. Figure 3 The thickness TK5 shown in FIG. 5 may be greater than the thickness of the titanium nitride layer 44 (eg, Figure 3 ), and the thickness TK5 of the titanium layer 46 is less than or equal to five times the thickness TK4 of the titanium nitride layer 44 .

[0054] like Figures 3 and 4 As shown, in some embodiments, at least a portion of the titanium nitride layer 44 may become a titanium nitride barrier layer 44' after the titanium layer 46 is formed, and an intermediate layer 45 may be formed between the titanium nitride barrier layer 44' and the titanium layer 46. In some embodiments, the intermediate layer 45 may be considered a material layer formed by interdiffusion between the titanium nitride layer 44 and the titanium layer 46. Therefore, the intermediate layer 45 may directly connect the titanium layer 46 and the titanium nitride barrier layer 44', and the intermediate layer 45 may include titanium and nitrogen. Therefore, after the intermediate layer 45 is formed, the thickness of the titanium nitride layer 44 and the titanium layer 46 may be relatively small, but the thickness of the titanium layer 46 (e.g., Figure 4 The thickness TK7 shown in FIG may still be greater than the thickness of the titanium nitride layer 44 (eg Figure 4). In some embodiments, after the intermediate layer 45 is formed, the thickness TK7 of the titanium layer 46 may be between twice and three times the thickness TK6 of the titanium nitride layer 44. In other words, the thickness TK7 of the titanium layer 46 may be greater than or equal to twice the thickness TK6 of the titanium nitride layer 44 and less than or equal to three times the thickness TK6 of the titanium nitride layer 44, and the ratio of the thickness TK7 to the thickness TK6 may be between 2 and 3, but is not limited thereto. Furthermore, in some embodiments, the nitrogen concentration of the intermediate layer 45 may gradually decrease in a vertical direction (e.g., direction Z) extending toward the interface between the intermediate layer 45 and the titanium layer 46, but is not limited thereto.

[0055] Then, if Figure 2 as well as Figures 4 and 5 As shown, step S12 may be performed to form an aluminum layer 48 on the titanium layer 46, and the thickness of the aluminum layer 48 is greater than the thickness of the titanium layer 46. Figure 2 as well as Figures 5 and 6 As shown, step S13 can be performed to perform a reflow process after forming the aluminum layer 48. In some embodiments, the reflow process can include a thermal reflow process or other methods that can achieve the desired reflow effect. The reflow process can be used to move the voids in the aluminum layer 48 upward to a region near the upper surface of the aluminum layer 48. The reflow process can also be used to promote cross-diffusion between the aluminum layer 48 and the titanium layer 46. As a result, the titanium layer 46 and a portion of the aluminum layer 48 can be converted into a titanium-aluminum layer 47 after the reflow process. Therefore, in some embodiments, the titanium-aluminum layer 47 can be partially formed within the trench TR on the substrate 10 and partially formed outside the trench TR, but the present invention is not limited thereto. In some embodiments, the reflow process can be performed sequentially with the film formation process for forming the aluminum layer 48 in the same process chamber, thereby reducing the negative impact of the external environment and reducing the impact on the overall process time, especially when the reflow process time needs to be increased to achieve the above-mentioned effect, but the present invention is not limited thereto.

[0056] Afterwards, if Figure 6 、 Figure 1 as well as Figure 2As shown, step S14 may be performed, in which a chemical mechanical polishing (CMP) process is performed after the reflow process to remove the aluminum layer 48 and the titanium aluminum layer 47, the intermediate layer 45, the titanium nitride barrier layer 44', and the work function layer 42 outside the trench TR to form the gate structure GS. In some embodiments, the aluminum layer 48 can be completely removed by the aforementioned CMP process, so the titanium aluminum layer 47 can be the topmost layer in the gate structure GS, such as the topmost layer in the center region of the gate structure GS, but this is not limited to the above. In some embodiments, a portion of the aluminum layer 48 can remain on the titanium aluminum layer 47 after the CMP process, so the gate structure GS can include the aluminum layer 48 disposed on the titanium aluminum layer 47, but this is not limited to the above. Furthermore, in some embodiments, before forming the aluminum layer 48, since the thickness of the titanium layer may be greater than or equal to twice the thickness of the titanium nitride layer and less than or equal to three times the thickness of the titanium nitride layer, after forming the gate structure GS, the thickness TK3 of the titanium aluminum layer 47 in the gate structure GS may be between twice and three times the thickness TK1 of the titanium nitride barrier layer 44'.

[0057] The following description will focus on different embodiments of the present invention. To simplify the description, the following description will focus on the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate cross-reference between the embodiments.

[0058] See also Figure 7 、 Figure 3 as well as Figure 5 . Figure 7 The figure shows a method for manufacturing a semiconductor device according to another embodiment of the present invention. Figure 3 can be considered as depicting Figure 7 Schematic diagram of the previous situation, and Figure 5 can be considered as depicting Figure 7 Schematic diagram of the situation afterward. Figure 3 and Figure 7 As shown, in some embodiments, after the aluminum layer 48 is formed, no significant intermediate layer may be formed between the titanium layer 46 and the titanium nitride layer 44. Figure 7 and Figure 5 As shown, in some embodiments, the intermediate layer 45 may be formed between the titanium layer 46 and the titanium nitride layer 44 after the aluminum layer 48 is subjected to a reflow process, and at least a portion of the titanium nitride layer 44 may become the titanium nitride barrier layer 44' after the reflow process, but the present invention is not limited thereto.

[0059] In summary, in the semiconductor device and its manufacturing method of the present invention, by controlling the thickness ratio of the titanium nitride layer and the titanium layer during film formation and performing a reflow process before the chemical mechanical polishing process, the titanium layer can provide sufficient titanium to cross-diffusion with the aluminum in the aluminum layer to form a titanium aluminum layer with better uniformity, thereby improving related manufacturing process problems during the chemical mechanical polishing process and achieving the effects of improving the manufacturing process yield and / or enhancing the reliability of the semiconductor device.

[0060] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: substrate; as well as A gate structure is disposed on the substrate, wherein the gate structure comprises: a titanium nitride barrier layer; and a titanium aluminide layer disposed on the titanium nitride barrier layer, wherein the thickness of the titanium aluminide layer is between twice and three times the thickness of the titanium nitride barrier layer; an intermediate layer disposed between the titanium aluminum layer and the titanium nitride barrier layer, wherein the intermediate layer directly connects the titanium aluminum layer and the titanium nitride barrier layer, and the intermediate layer comprises titanium and nitrogen, wherein the nitrogen concentration of the intermediate layer gradually decreases in a vertical direction extending toward the interface between the intermediate layer and the titanium aluminum layer, The method of forming the gate structure includes: A titanium layer is formed on the titanium nitride barrier layer. forming an aluminum layer on the titanium layer; and A reflow process is performed after the aluminum layer is formed, wherein the titanium layer and a portion of the aluminum layer are transformed into the titanium aluminum layer after the reflow process. 2 . The semiconductor device as claimed in claim 1 , wherein the titanium aluminum layer is the uppermost layer in the gate structure.

3. The semiconductor device according to claim 1 , wherein the gate structure further comprises: a work function layer disposed below the titanium nitride barrier layer; a bottom barrier layer disposed below the work function layer; as well as The gate dielectric layer is disposed below the bottom barrier layer.

4. A method for manufacturing a semiconductor device, comprising: A gate structure is formed on a substrate, wherein the gate structure comprises: a titanium nitride barrier layer; and a titanium aluminide layer disposed on the titanium nitride barrier layer, wherein the thickness of the titanium aluminide layer is between twice and three times the thickness of the titanium nitride barrier layer; The method of forming the gate structure includes: forming a titanium nitride layer on the substrate; forming a titanium layer on the titanium nitride layer, wherein the thickness of the titanium layer is greater than the thickness of the titanium nitride layer, wherein at least a portion of the titanium nitride layer becomes the titanium nitride barrier layer after forming the titanium layer, forming an aluminum layer on the titanium layer; and A reflow process is performed after the aluminum layer is formed, wherein the titanium layer and a portion of the aluminum layer are transformed into the titanium aluminum layer after the reflow process. 5 . The method for manufacturing a semiconductor device as claimed in claim 4 , wherein the thickness of the titanium layer is between twice and three times the thickness of the titanium nitride layer. 6 . The method for manufacturing a semiconductor device according to claim 4 , wherein an intermediate layer is formed between the titanium nitride barrier layer and the titanium layer, the intermediate layer directly connects the titanium layer and the titanium nitride barrier layer, and the intermediate layer comprises titanium and nitrogen. 7 . The method for fabricating a semiconductor device according to claim 6 , wherein a nitrogen concentration of the intermediate layer gradually decreases in a vertical direction extending toward an interface between the intermediate layer and the titanium layer.

8. The method for fabricating a semiconductor device according to claim 4 , wherein the titanium aluminum layer is partially formed within the trench on the substrate and partially formed outside the trench, and the method for forming the gate structure further comprises: A chemical mechanical polishing process is performed after the reflow process to remove the titanium aluminum layer outside the trench. 9 . The method for fabricating a semiconductor device as claimed in claim 8 , wherein the aluminum layer is completely removed by the chemical mechanical polishing process. 10 . The method for manufacturing a semiconductor device as claimed in claim 4 , wherein the titanium aluminum layer is the uppermost layer in the gate structure.

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