A floating gate two-dimensional heterojunction memristor and its preparation method
By constructing floating gate two-dimensional heteromemristors, the stability and miniaturization problems of traditional memristors are solved, and stable conversion of high-impedance states and long-term information storage are achieved, which is suitable for neuromorphic calculations and flexible electronic devices.
Patent Information
- Application Number
- CN202210919398.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-02
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2042-08-02
AI Technical Summary
Traditional memristors have poor stability, poor reusability and difficulty in miniaturization, and block-based devices have challenges in mechanical flexibility and heterogeneity integration.
The floating gate two-dimensional heteromemory resistor is adopted, and the structure consists of an Ag electrode layer, a SiO2/Si substrate layer, a MoS2 carrier transport layer, an Au electrode layer, an h-BN insulated dielectric layer and an Au nanoparticle charge trapping layer. It is prepared by chemical vapor deposition and mechanical peeling method to ensure the stability and flexibility of the MoS2/h-BN/AuNPs devices.
The device is stable conversion between different impedance states, the high-resistance state and the low-resistance state maintain good stability within 12,000 s, and the switching ratio remains at the order of 104 after 3,000 repeated operations, and has excellent information storage and erasing performance.
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Figure CN115394858B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of memory, and in particular relates to a floating gate two-dimensional heterojunction memristor and a preparation method thereof. Technical Background
[0002] Memories based on traditional silicon and germanium semiconductors play a vital role in contemporary electronic information and computing. Over the past few decades, as transistor channel dimensions have continued to shrink, short-channel effects have become increasingly pronounced, making it increasingly difficult to further improve memory performance by shrinking transistor dimensions. Consequently, Moore's Law will be difficult to maintain under the von Neumann computing architecture. Therefore, the development of new material systems or novel device structures is necessary to meet society's demand for high-performance information processing and storage.
[0003] Synaptic devices based on memristors are the foundation for building neuromorphic networks. Neuromorphic computing has the characteristics of fast computing speed and low power consumption, and is expected to break through the bottleneck of von Neumann computing architecture. Therefore, memristor memory is expected to provide new ideas for solving the problems faced by traditional semiconductor devices. Traditional memristors based on transition metal oxides (TMOs) such as TiO x ,MoO x The switching mechanism of memristors such as TMDCs and h-BN is primarily the formation and destruction of an internal conductive channel. This switching mechanism irreversibly damages the conductive channel, causing device performance degradation after repeated switching cycles, resulting in poor reusability and stability. Furthermore, due to the poor mechanical flexibility of traditional bulk materials, memristors based on bulk materials are difficult to scale down and integrate heterogeneously. Compared to traditional TMO memristors, atomically thin TMDCs and layered two-dimensional materials such as h-BN offer the potential to achieve richer and more stable device performance due to their unique electrical properties, good mechanical flexibility, and ease of heterogeneous integration.
[0004] Therefore, in order to solve the problems of poor stability, poor reusability and difficulty in miniaturization of traditional memristors, the present invention designs a memristor based entirely on two-dimensional materials, which has excellent stability, stronger robustness and excellent impedance switching characteristics compared to traditional TMO memristors.
[0005] References:
[0006] [1]Hou ? Summary of the Invention
[0007] The main innovation of this invention is to construct a new type of floating-gate heterojunction memristor (constructed entirely from low-dimensional materials, with unique advantages in miniaturization and flexibility), whose performance characteristics are:
[0008] The present invention discloses a floating gate two-dimensional heterojunction memristor. The memristor comprises, from bottom to top, an Ag electrode layer, a SiO2 / Si substrate layer, and a MoS2 carrier transport layer. Au electrodes are provided at opposite ends of the upper surface of the MoS2 carrier transport layer. The upper surface formed by the Au electrode and the MoS2 carrier transport layer is covered with an h-BN insulating dielectric layer. The h-BN insulating dielectric layer forms a groove corresponding to the upper surface formed by the Au electrode and the MoS2 carrier transport layer. An Au nanoparticle (AuNPs) charge capture layer is provided in the groove and on the upper surface of the h-BN insulating dielectric layer. The AuNPs charge capture layer, the h-BN insulating dielectric layer, and the MoS2 carrier transport layer constitute a two-dimensional heterojunction MoS2 / h-BN / AuNPs with impedance storage characteristics.
[0009] As a further improvement, the SiO2 / Si substrate layer described in the present invention includes a Si substrate layer and a SiO2 passivation layer from bottom to top.
[0010] As a further improvement, the MoS2 carrier transport layer and the AuNPs charge capture layer described in the present invention are separated by an h-BN insulating dielectric layer.
[0011] As a further improvement, the thickness of the AuNPs charge capture layer of the present invention is 50-100 nm, and the AuNPs charge capture layer is Au nanoparticles.
[0012] The present invention also discloses a method for preparing a floating gate two-dimensional heterojunction memristor, and the preparation steps are as follows:
[0013] 1) Depositing an Ag electrode on the back of a SiO2 / Si substrate using thermal evaporation, wherein the thickness of the Ag film is controlled to be 100-200 nm;
[0014] 2) Growing a MoS2 carrier transport layer on a SiO2 / Si substrate using chemical vapor deposition (CVD);
[0015] 3) depositing Au electrodes on the surface of the MoS2 carrier transport layer through micro-nano processing;
[0016] 4) Using mechanical exfoliation, PDMS was used to exfoliate the bulk h-BN to obtain a two-dimensional h-BN insulating dielectric film;
[0017] 5) Using a transfer platform, the two-dimensional h-BN insulating dielectric film on the PDMS is transferred to the surface of the MoS2 carrier transport layer on which the Au electrode is deposited, forming an h-BN insulating dielectric layer;
[0018] 6) Au nanoparticles were synthesized using a hydrothermal method and spin-coated on the surface of the h-BN insulating dielectric layer to form an AuNPs charge capture layer of the floating gate, thereby obtaining a floating gate type two-dimensional heterojunction memristor containing a two-dimensional heterojunction MoS2 / h-BN / AuNPs.
[0019] As a further improvement, the present invention first deposits the Au electrode on the surface of the MoS2 carrier transport layer through micro-nano processing technology, and then transfers the h-BN insulating dielectric layer to the surface of the MoS2 carrier transport layer with the electrode deposited to obtain a MoS2 / h-BN heterojunction.
[0020] As a further improvement, the thermal evaporation process of the Ag electrode at the bottom of the SiO2 / Si described in the present invention needs to be completed before the growth of the MoS2 carrier transport layer, and the thickness of the Ag electrode is 100-200nm.
[0021] As a further improvement, the growth of the MoS2 carrier transport layer in step 2) of the present invention is completed in a dual-temperature tube furnace, and the specific growth parameters are: the sulfur precursor S is placed in the first temperature zone, and MoO3 and SiO2 / Si substrate are placed near the second temperature zone, wherein the temperature control program of the first temperature zone is set to: RT (room temperature) (5 min) → 40°C (21 min) → 40°C (10 min) → 175°C (5 min). The temperature control program of the second temperature zone is set to: RT (5 min) → 60°C (5 min) → 60°C (20 min) → 680°C (5 min) → 800°C. The MoS2 thickness obtained under these growth conditions is 1-2 nm.
[0022] The beneficial effects of the present invention are:
[0023] 1) By applying a negative back-gate voltage to the MoS2 / h-BN / AuNPs device, the device can be placed in a low-resistance state, while applying a positive back-gate voltage can place the device in a high-resistance state. In other words, the MoS2 / h-BN / AuNPs device can be switched between different impedance states by applying different back-gate voltages.
[0024] 2) Due to the good charge capture ability and stability of Au nanoparticles, the high-resistance and low-resistance states of the memristor show good stability within the time scale of 12,000 s.
[0025] 3) Thanks to the charge trapping mechanism of the floating gate memristor, the MoS2 channel of the MoS2 / h-BN / AuNPs device is not easily damaged during the switching process. Therefore, after more than 3000 repeated switching cycles, the device's on / off ratio can still maintain 10 4 Magnitude.
[0026] 4) The MoS2 carrier transport layer and the AuNPs charge capture layer are separated by the h-BN insulating dielectric layer, which prevents the charge of the floating gate from leaking into the channel and prolongs the storage time.
[0027] 5) The thickness of the AuNPs charge capture layer, which is composed of Au nanoparticles, is between 50 and 100 nm. This thickness ensures a high charge capture efficiency for the floating gate layer and improves the on / off ratio.
[0028] 6) In the preparation method, the Au electrode is first deposited on the surface of the MoS2 carrier transport layer using micro-nano processing technology, and then the h-BN insulating dielectric layer is transferred to the surface of the MoS2 carrier transport layer with the electrode deposited to obtain a MoS2 / h-BN heterojunction. The order of depositing the electrode and transferring the h-BN ensures that the h-BN insulating layer completely covers the MoS2 channel and the metal electrode, ensuring that the Au nanoparticles are completely separated from the MoS2 channel.
[0029] 7) The thermal evaporation process of the Ag electrode at the bottom of SiO2 / Si needs to be completed before the growth of the MoS2 carrier transport layer. The process sequence of thermal evaporation of the Ag electrode first and then growing MoS2 can avoid the high temperature during the evaporation process of the Ag electrode causing damage to the MoS2 channel.
[0030] 8) The growth of the MoS2 carrier transport layer in step 2) is completed in a dual-temperature tube furnace, and specific growth parameters are set. The MoS2 grown under these specific growth parameters has a unique size and high carrier mobility, which ensures the unique impedance storage characteristics of the memristor.
[0031] 9) Compared to conventional bulk-based memristors, the memristive memory in this invention is constructed from zero-dimensional and two-dimensional nanomaterials, offering unique advantages in miniaturization and flexibility. Considering the device exhibits excellent information storage and erasure performance, as well as good stability and reusability, the MoS2 / h-BN / AuNPs floating-gate memristor introduced in this invention has promising development prospects and practical value. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 is a schematic diagram of the MoS2 / h-BN / AuNPs memristor structure;
[0033] Figure 2 This is the conversion diagram between high resistance state (HRS) and low resistance state (LRS) of MoS2 / h-BN / AuNPs memristor under +8V and -8V gate voltage control;
[0034] Figure 3 This is the IV curve change diagram of MoS2 / h-BN / AuNPs memristor under -2V~-20V gate voltage regulation;
[0035] Figure 4 This is the characteristic diagram of the switching ratio of MoS2 / h-BN / AuNPs memristor changing with the number of switching times;
[0036] Figure 5 is the impedance stability diagram of the memristor in high-resistance and low-resistance states;
[0037] Figure 6 It is a schematic diagram of the CVD equipment structure and MoS2 growth parameters;
[0038] Figure 7 This is a top-down schematic diagram of the MoS2 / h-BN / AuNPs memristor structure.
[0039] In the figure, 1 is the h-BN insulating dielectric layer, 2 is the Au electrode, 3 is the MoS2 carrier transport layer, 4 is the Si substrate layer, 5 is the Ag electrode layer, 6 is the SiO2 passivation layer, and 7 is the Au nanoparticles;
[0040] Figure 8 This is the IV curve of the MoS2 device (without AuNPs and h-BN) under gate voltage control;
[0041] Figure 9 This is the IV curve of the MoS2 / h-BN device (without AuNPs) under gate voltage regulation. DETAILED DESCRIPTION
[0042] The technical solution of the present invention will be further described below with reference to the accompanying drawings through specific implementation examples:
[0043] Figure 1 is a schematic diagram of the MoS2 / h-BN / AuNPs memristor structure; Figure 7 The figure shows a top-down schematic diagram of the MoS2 / h-BN / AuNPs memristor structure. From bottom to top, the memristor comprises an Ag electrode layer 5, a SiO2 / Si substrate layer 4, and a MoS2 carrier transport layer 3. Au electrodes 2 are provided at opposite ends of the upper surface of the MoS2 carrier transport layer 3. The upper surface formed by the two Au electrodes 2 and the MoS2 carrier transport layer 3 is covered with an h-BN insulating dielectric layer 1. The h-BN insulating dielectric layer 1 forms a groove corresponding to the upper surface formed by the Au electrodes 2 and the MoS2 carrier transport layer 3. Within the groove, on the upper surface of the h-BN insulating dielectric layer 1, lies the AuNPs charge capture layer. The AuNPs charge capture layer, h-BN insulating dielectric layer 1, and MoS2 carrier transport layer 3 form a two-dimensional MoS2 / h-BN / AuNPs heterojunction with impedance storage properties. The SiO2 / Si substrate layer 4 is comprised of a Si substrate layer 4 and a SiO2 passivation layer 6 from bottom to top. The MoS2 carrier transport layer 3 and the AuNPs charge capture layer are separated by an h-BN insulating dielectric layer 1. The AuNPs charge capture layer has a thickness of 50-100 nm and is composed of Au nanoparticles 7.
[0044] The structural and performance advantages of the prepared MoS2 / h-BN / AuNPs memristor are:
[0045] 1. In the absence of the h-BN insulating dielectric layer 1 and the AuNPs charge trapping layer, the MoS2 device alone does not exhibit memristive properties (see Figure 8 );
[0046] 2. In the case of h-BN insulating dielectric layer 1 but lacking AuNPs, the MoS2 / h-BN heterojunction device does not exhibit memristive properties (see Figure 9 );
[0047] 3. h-BN is transferred to the MoS2 channel surface by transfer, which avoids damage to the channel material caused by the high temperature during the thermal deposition of the insulating dielectric layer 1, thereby improving the life and stability of the device. In contrast, the memristor reported by Zhou et al. uses A2O3 as the dielectric layer [1]. The channel material needs to undergo a high-temperature thermal deposition process, so the stability and fatigue resistance of this device are lower than those of the device.
[0048] 4. The use of Au nanoparticles 7 as the charge capture layer effectively improves the stability of the memristor compared to the use of CdSe quantum dots as the charge capture layer reported by Zhou et al. [1], making the memristor have a longer retention time in the low resistance state, thereby increasing the information storage time.
[0049] Detailed device fabrication process
[0050] Synthesis of CVDMoS2, Figure 6 Schematic diagram of the photolithography and deposition process of Au / Cr electrodes on the MoS2 surface;
[0051] First, SiO2 / Si sheets were cut into 1cm*1cm sizes, ultrasonicated in ethanol and deionized water for several minutes each, and then blown dry to obtain a clean SiO2 / Si substrate. MoS2 was then grown on the surface of the SiO2 / Si substrate using a dual-temperature zone tube furnace. The specific growth conditions were as follows: sulfur precursor (S) was placed in the first temperature zone, and MoO3 and SiO2 / Si substrate (as shown in the attached figure) were placed near the second temperature zone. Figure 6 The temperature control program for the first zone was as follows: RT (room temperature) (5 min) → 40°C (21 min) → 40°C (10 min) → 175°C (5 min). The temperature control program for the second zone was as follows: RT (5 min) → 60°C (5 min) → 60°C (20 min) → 680°C (5 min) → 800°C. Under these growth conditions, the MoS2 thickness achieved was 1-2 nm.
[0052] Deposition of Ag film
[0053] A SiO2 / Si sheet with MoS2 grown on it was selected, and a specific area of the Si surface was shielded using tape as a shielding layer. Then, a Ag electrode pattern was deposited on the lower surface of the Si using a thermal evaporation device.
[0054] Deposition of Au electrode 2
[0055] First, the pattern of the Au electrode 2 is printed on the MoS2 surface using a semiconductor photolithography process. Then, a 20nm Au film is deposited on the MoS2 surface using electron beam thermal evaporation. Finally, the electrode pattern is deposited on the MoS2 surface by peeling it off in acetone.
[0056] Preparation of two-dimensional h-BN insulating dielectrics
[0057] h-BN is prepared using a mechanical exfoliation method: Scotch tape is applied to one side of the bulk h-BN, and PDMS is applied to the other side. The PDMS is then quickly peeled off, separating the bulk h-BN. This process is repeated multiple times to achieve nanometer-thick h-BN adhered to the PDMS (nearly transparent under a microscope).
[0058] Preparation of MoS2 / h-BN heterojunction
[0059] Using a mechanical transfer platform, h-BN is transferred to the MoS2 surface where the Au electrode 2 is deposited. During the transfer process, the angle and position are adjusted to ensure that the h-BN insulating dielectric film completely covers the MoS2 channel area. The electrode is first deposited on the MoS2 surface, and then the h-BN is transferred to cover the entire MoS2 and electrode area. This ensures that the floating gate's Au nanoparticles 7 are completely isolated from the MoS2 channel, preventing charge leakage.
[0060] Preparation of AuNPs charge capture layer on MoS2 / h-BN / AuNPs surface
[0061] First, Au nanoparticles 7 were synthesized by a hydrothermal method and dissolved in chloroform. Then, 0.5 ml of the Au nanoparticle 7 colloidal solution was spin-coated onto the MoS2 / h-BN heterojunction surface at a spin coater speed of 4500 rpm for 60 seconds.
[0062] The above is the entire process of preparing MoS2 / h-BN / AuNPs memristor.
[0063] Performance testing and effect analysis of floating-gate two-dimensional heterojunction memristor containing two-dimensional heterojunction MoS2 / h-BN / AuNPs
[0064] In order to test the electrical transport and impedance control properties of the MoS2 / h-BN / Au memristor, the MoS2 / h-BN / Au memristor was first integrated on a PCB using solder, and then the device was connected to a semiconductor analyzer via gold wires.
[0065] Figure 2 This is a diagram showing the transition between high resistance state (HRS) and low resistance state (LRS) of the MoS2 / h-BN / AuNPs memristor under +8V and -8V gate voltage control; it shows that under -8V back gate voltage control, the impedance of the device changes from the initial state (originalstate) to the low resistance state (LRS), and then under +8V back gate voltage control, the device changes from the low resistance state (LRS) to the high resistance state (HRS).
[0066] Figure 3 The figure shows the change of the IV curve of the MoS2 / h-BN / AuNPs memristor under the control of the gate voltage of -2V to -20V; it shows the gradual change process of the device from the HRS state to the LRS state under the control of a series of different negative gate voltages, indicating that the MoS2 / h-BN / Au memristor can be in multiple different stable impedance states (this feature gives the device the application potential of multi-bit information storage).
[0067] Figure 4 This is the characteristic diagram of the switching ratio of MoS2 / h-BN / AuNPs memristor changing with the number of switching times; Figure 5 These are the impedance stability diagrams of the memristor in high-resistance and low-resistance states, respectively showing the repeated switching endurance and impedance state stability of the MoS2 / h-BN / Au device. Figure 4 The results show that the device maintains an on / off ratio of 10 after more than 3000 repeated switching cycles. 4 It has excellent robustness and durability. Figure 5 The results show that the device exhibits good stability in both high-resistance and low-resistance states within a time scale of 12,000 seconds. This performance indicator is significantly higher than that of other memristors based on two-dimensional materials, demonstrating excellent information storage stability.
[0068] The above are the performance indicators of the devices involved in the present invention under specific structural parameters. It should be pointed out that within the framework of the core technical features of the present invention, the optimization and improvement of the devices in the present invention should also be regarded as the scope of protection of the present invention.
Claims
1. A floating gate two-dimensional heterojunction memristor, characterized in that: The memristor comprises, from bottom to top, an Ag electrode layer (5), a SiO2 / Si substrate layer (4), and a MoS2 carrier transport layer (3); Au electrodes (2) are provided at opposite ends of the upper surface of the MoS2 carrier transport layer (3); the upper surface formed by the Au electrode (2) and the MoS2 carrier transport layer (3) is covered with an h-BN insulating dielectric layer (1); the h-BN insulating dielectric layer (1) forms a groove corresponding to the upper surface formed by the Au electrode (2) and the MoS2 carrier transport layer (3); the AuNPs charge capture layer is located in the groove and on the upper surface of the h-BN insulating dielectric layer (1); the AuNPs charge capture layer, the h-BN insulating dielectric layer (1), and the MoS2 carrier transport layer (3) constitute a two-dimensional heterojunction MoS2 / h-BN / AuNPs with impedance storage characteristics.
2. The floating gate two-dimensional heterojunction memristor according to claim 1, characterized in that: The SiO2 / Si substrate layer (4) comprises, from bottom to top, a Si substrate layer (4) and a SiO2 passivation layer (6).
3. The floating gate two-dimensional heterojunction memristor according to claim 1, characterized in that: The MoS2 carrier transport layer (3) and the AuNPs charge capture layer are separated by an h-BN insulating dielectric layer (1).
4. The floating gate two-dimensional heterojunction memristor according to claim 1, characterized in that The thickness of the AuNPs charge capture layer is 50-100 nm, and the AuNPs charge capture layer is Au nanoparticles (7).
5. A method for preparing a floating gate two-dimensional heterojunction memristor according to claim 1, 3 or 4, characterized in that: The preparation steps are as follows: 1) Depositing an Ag electrode on the back of a SiO2 / Si substrate using thermal evaporation, wherein the thickness of the Ag film is controlled to be 100-200 nm; 2) Growing a MoS2 carrier transport layer on a SiO2 / Si substrate using chemical vapor deposition (CVD); 3) depositing the Au electrode (2) on the surface of the MoS2 carrier transport layer through a micro-nano processing process; 4) Using mechanical exfoliation, PDMS was used to exfoliate the bulk h-BN to obtain a two-dimensional h-BN insulating dielectric film; 5) using a transfer platform to transfer the two-dimensional h-BN insulating dielectric film on the PDMS to the surface of the MoS2 carrier transport layer on which the Au electrode (2) is deposited, thereby forming an h-BN insulating dielectric layer (1); 6) Au nanoparticles (7) are synthesized using a hydrothermal method, and the Au nanoparticles are spin-coated on the surface of the h-BN insulating dielectric layer (1) to form an AuNPs charge capture layer of a floating gate, thereby obtaining a floating gate type two-dimensional heterojunction memristor comprising a two-dimensional heterojunction MoS2 / h-BN / AuNPs.
6. The method for preparing a floating gate two-dimensional heterojunction memristor according to claim 5, characterized in that: First, an Au electrode (2) is deposited on the surface of a MoS2 carrier transport layer (3) by micro-nano processing technology, and then an h-BN insulating dielectric layer (1) is transferred to the surface of the MoS2 carrier transport layer (3) on which the electrode is deposited, thereby obtaining a MoS2 / h-BN heterojunction.
7. The method for preparing a floating gate two-dimensional heterojunction memristor according to claim 5, wherein: The thermal evaporation process of the Ag electrode at the bottom of the SiO2 / Si needs to be completed before the growth of the MoS2 carrier transport layer (3), and the thickness of the Ag electrode is 100-200nm.
8. According to the preparation method of the floating gate two-dimensional heterojunction memristor according to claim 5, the growth of the MoS2 carrier transport layer (3) in the step 2) is completed in a dual-temperature tube furnace, and the specific growth parameters are: the sulfur precursor S is placed in the first temperature zone, and MoO3 and SiO2 / Si substrate are placed near the second temperature zone, wherein the temperature control program of the first temperature zone is set to: RT (room temperature) (5min) → 40℃ (21min) → 40℃ (10min) → 175℃ (5min), and the temperature control program of the second temperature zone is set to: RT (5min) → 60℃ (5min) → 60℃ (20min) → 680℃ (5min) → 800℃, and the MoS2 thickness obtained under the growth parameters is 1-2nm.