Resistive random access memory and methods of making the same

Abstract

The application provides a resistive random access memory and a preparation method thereof. The resistive random access memory comprises the following steps: depositing metal on a bottom layer to form a lower electrode metal structure, etching the lower electrode metal structure to form regularly distributed linear lower electrodes; forming a ReRAM switching layer on the lower electrodes; filling a dielectric material layer on the ReRAM switching layer, the dielectric material layer being filled between two adjacent ReRAM switching layers and covering the ReRAM switching layer; and arranging a metal contact of the lower electrode on the dielectric material layer, the metal contact extending between the two adjacent ReRAM switching layers to form the resistive random access memory. The application can improve the storage unit density and avoid damage to the structure caused by the etching process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and more specifically, to a resistive random access memory and its fabrication method. Background Technology

[0002] Currently, resistive random access memory (ReRAM) has become a strong competitor to polysilicon floating gate (FG) memory due to its outstanding advantages, such as high programming / erasing speed, high device density, miniaturization, low power consumption, radiation resistance, data retention after power failure, and compatibility with CMOS (Complementary Metal-Oxide Semiconductor) technology. As a memory that uses a non-charge storage mechanism, it has great potential for development in high-end applications at the 32nm process node and below.

[0003] However, as the integration density of semiconductor devices continues to increase, the critical dimension (CD) of memory cells is becoming smaller and smaller, while the stacking density is constantly increasing. This results in an increasingly larger aspect ratio (AR) in the etching process, making it increasingly difficult to control the deposition / sputtering, cleaning, and profile during metal etching. In addition, the ReRAM etching process requires a combination of processes such as reactive ion etching (RIE), ion beam etching (IBE), and bombardment. Multiple etching processes can cause repeated damage to the ReRAM sidewalls, leading to difficulties in fabrication and compromised performance.

[0004] Specifically, existing preparation methods and processes face the following problems: 1. Etching is becoming increasingly difficult, which can easily lead to insufficient or excessive etching; 2. Cleaning and drying after etching are becoming increasingly difficult; 3. For some etched layer composites containing a large amount of metal, traditional methods cannot be used for etching, making it very difficult to clean up metal sputtering, and the morphology of the etched structure is also very difficult to control.

[0005] Therefore, there is an urgent need for a fabrication process that can reduce the fabrication difficulty of resistive random access memory (RRAM) and improve the fabrication quality. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide a resistive random access memory and its fabrication method, so as to solve the problems of high difficulty in existing fabrication processes and the inability to guarantee product performance.

[0007] The present invention provides a method for fabricating a resistive random access memory (ReRAM), comprising: depositing metal on a substrate to form a lower electrode metal structure, and etching the lower electrode metal structure to form regularly distributed linear lower electrodes; forming a ReRAM switching layer on the lower electrodes; filling a dielectric material layer on the ReRAM switching layer, wherein the dielectric material layer fills between two adjacent ReRAM switching layers and covers the ReRAM switching layer; and forming metal contacts for the lower electrodes on the dielectric material layer, wherein the metal contacts extend between two adjacent ReRAM switching layers to form a resistive random access memory.

[0008] In addition, an alternative technical solution is that the process of forming a ReRAM switching layer on the lower electrode includes: growing a ReRAM switching layer on the lower electrode by atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or evaporation and / or sputtering and / or thermal growth; wherein the ReRAM switching layer is distributed in a fin-like structure.

[0009] Alternatively, an alternative technical solution is to remove the ReRAM switching layer located at the bottom between two adjacent lower electrodes, so that the two adjacent ReRAM switching layers are spaced apart from each other.

[0010] In addition, an optional technical solution is that the process of filling the dielectric material layer on the ReRAM switching layer includes: setting a dielectric material layer covering the ReRAM switching layer on the ReRAM switching layer by atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or thermal growth; planarizing the dielectric material layer to a preset etching position, the preset etching position being not lower than the upper surface of the ReRAM switching layer, so as to form the basic structure of resistive random access memory.

[0011] In addition, an alternative technical solution is that the process of setting the metal contact of the lower electrode on the dielectric material layer includes: setting a metal hole between two adjacent ReRAM switching layers; filling the metal hole with a metal dielectric, the surface of which extends to the upper surface of the planarized dielectric material layer.

[0012] In addition, an alternative technical solution is that the longitudinal section of the metal hole is conical, and the cross-section of the metal hole is circular or elliptical.

[0013] Alternatively, the metal holes can be formed within the base structure using methods such as ALD, PVD, CVD, thermal growth, electroplating, vapor deposition, or sputtering.

[0014] In addition, an optional technical solution is to, after forming the ReRAM switching layer on the lower electrode, perform photolithography on the ReRAM switching layer, with the photolithography direction perpendicular to the extension direction of the lower electrode; fill the photolithography location with developer and perform etching to form a cross-sectional switching matrix.

[0015] In addition, alternative technical solutions include using non-metals, metal oxides, metal nitrides, and inert metals as materials for the ReRAM switching layer.

[0016] According to another aspect of the present invention, a resistive random access memory (RRAM) is provided, which is prepared using the above-described method for preparing a resistive RRAM.

[0017] Using the aforementioned resistive random access memory (RRAM) and its fabrication method, metal deposition is performed on the bottom layer to form a lower electrode metal structure. The lower electrode metal structure is then etched to form regularly distributed linear lower electrodes. A ReRAM switching layer is then formed on the lower electrodes, and a dielectric material layer is filled on the ReRAM switching layer. The dielectric material layer fills the space between two adjacent ReRAM switching layers and covers the ReRAM switching layer. Finally, metal contacts for the lower electrodes are formed on the dielectric material layer, extending to the space between two adjacent ReRAM switching layers to form the resistive random access memory. This method can increase the memory cell density and, for relatively simple metal etching, avoid damage to other structures of the memory caused by the etching process, simplifying the manufacturing process and improving the manufacturing yield.

[0018] To achieve the foregoing and related objectives, one or more aspects of the invention include the features that will be described in detail below. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to encompass all such aspects and their equivalents. Attached Figure Description

[0019] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings:

[0020] Figure 1 This is a flowchart of a method for fabricating resistive random access memory according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a resistive random access memory (RRAM) fabrication method according to an embodiment of the present invention.

[0022] The reference numerals in the figures include: 1. Lower electrode metal structure; 2. Bottom layer; 3. Lower electrode; 4. ReRAM switching layer; 5. Developing adhesive; 6. Dielectric material layer; 7. Metal hole.

[0023] In all the accompanying drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed Implementation

[0024] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0026] To describe in detail the resistive random access memory and its fabrication method of the present invention, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 A schematic flowchart of a method for fabricating resistive random access memory according to an embodiment of the present invention is shown.

[0028] like Figure 1 As shown, the method for fabricating resistive random access memory (RAM) according to an embodiment of the present invention includes:

[0029] S110: Metal deposition is performed on the bottom layer 2 to form the lower electrode metal structure 1, and the lower electrode metal structure 1 is etched to form a regularly distributed linear lower electrode 3.

[0030] S120: A ReRAM switching layer 4 is formed on the lower electrode 3.

[0031] The process of forming the ReRAM switching layer 4 on the lower electrode 3 includes: growing the ReRAM switching layer 4 on the lower electrode 3 by atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or evaporation and / or sputtering and / or thermal growth; wherein the ReRAM switching layer 4 is distributed in a fin-like structure, and this distribution of the ReRAM switching layer 4 can effectively adjust the distance between two adjacent lower electrodes 3, which can effectively reduce the overall size of the memory.

[0032] In addition, the ReRAM switching layer 4 located at the bottom between two adjacent lower electrodes 3 can be selectively removed so that the two adjacent ReRAM switching layers 4 are spaced apart from each other, so that the ReRAM switching layer 4 only covers the two sides and the top surface of the lower electrode 3.

[0033] The material of the ReRAM switching layer 4 may include non-metals, metal oxides, metal nitrides, metal compounds, and inert metals.

[0034] S130: A dielectric material layer 6 is filled on the ReRAM switching layer 4. The dielectric material layer 6 fills the space between two adjacent ReRAM switching layers 4 and covers the ReRAM switching layer 4.

[0035] Specifically, a dielectric material layer 6 covering the ReRAM switching layer 4 is formed on the ReRAM switching layer 4 by atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or thermal growth. The dielectric material layer 6 is planarized to a preset etching position, which is not lower than the upper surface of the ReRAM switching layer 4, so as to form the basic structure of the resistive random access memory. This effectively controls the thickness of the lower electrode 3 and prevents it from being corroded or damaged during subsequent chemical processing.

[0036] In the process of planarizing the dielectric material layer 6, a certain height of the dielectric material layer 6 needs to be reserved on the upper surface of the ReRAM switching layer 4, instead of directly planarizing it to the height of the lower electrode 3. This process can simplify the subsequent metal contact setup, eliminate the need for surface metal layer setup, simplify the process, and effectively control the surface consistency and thickness of the dielectric material layer 6.

[0037] S140: A metal contact for the lower electrode 3 is provided on the dielectric material layer 6, and the metal contact extends between two adjacent ReRAM switching layers 4 to form a resistive random access memory.

[0038] The process of setting the metal contact of the lower electrode 3 on the dielectric material layer 6 includes: setting a metal hole 7 between two adjacent ReRAM switching layers 4; filling the metal hole 7 with a metal dielectric, the surface of which extends to the upper surface of the planarized dielectric material layer 6.

[0039] Specifically, the metal hole 7 can be directly set on the planarized dielectric material layer 6 and located between two adjacent ReRAM switching layers 4, and the depth of the metal hole 7 extends to the upper surface of the dielectric material layer 6.

[0040] In one specific embodiment of the present invention, the longitudinal section of the metal hole 7 can be set as a conical structure, and the cross section of the metal hole 7 is a circular or elliptical structure. Specifically, the width of the metal hole 7 can be flexibly adjusted according to the structure or requirements of the lower electrode 3.

[0041] In addition, the aforementioned metal holes 7 can be set in the base structure through various methods such as ALD, PVD, CVD, thermal growth, electroplating, vapor deposition or sputtering.

[0042] As a specific example, in this embodiment, the method for fabricating resistive random access memory may include:

[0043] Step 1: Deposit metal on the bottom layer 2 to form the lower electrode metal structure 1;

[0044] Step 2: Etch the lower electrode metal structure 1 to form a regularly distributed linear lower electrode 3;

[0045] Step 3: Form a ReRAM switching layer 4 on the lower electrode 3;

[0046] Step 4: Set up developer 5 for photolithography to form a cross-sectional exchange matrix as shown in Step 5;

[0047] Step 6: Fill the ReRAM switching layer 4 with dielectric material layer 6;

[0048] Step 7: Planarize the dielectric material layer 6 and process it to a preset etching position. This preset etching position is higher than the upper surface of the ReRAM switching layer 4 so that the dielectric material layer 6 completely covers the ReRAM switching layer 4.

[0049] Step 8: Set the metal contact of the lower electrode 3 on the dielectric material layer 6. The metal contact extends between two adjacent ReRAM switching layers 4 to form a resistive random access memory.

[0050] In the above embodiment, after forming the ReRAM switching layer 4 on the lower electrode 3, the method further includes: performing photolithography on the ReRAM switching layer 4, with the photolithography direction perpendicular to the extension direction of the lower electrode 3; filling the photolithography location with developer 5 and etching it to form a cross-sectional switching matrix. This structure can reduce the spacing between memory cells, thereby increasing the density of resistive random access memory per unit area.

[0051] According to another aspect of the present invention, a resistive random access memory (RRAM) is provided, which is prepared using the above-described method for preparing a resistive RRAM.

[0052] It should be noted that the above embodiments of resistive random access memory can be referred to the description in the embodiments of the preparation method of resistive random access memory, and will not be repeated here.

[0053] According to the resistive random access memory and its fabrication method of the present invention, the spatial spacing between the memory cells of ReRAM can be reduced, thereby effectively improving the density of the resistive random access memory. By selectively setting the thickness of the ReRAM switching layer, the thickness of the lower electrode layer and the surface roughness threshold can be effectively controlled, improving the surface uniformity and consistency. At the same time, the lower electrode can be tightly wrapped and covered by the ReRAM switching layer, so that it will not be damaged by other etching and / or cleaning steps, thus improving the fabrication yield.

[0054] As referred above Figure 1 and Figure 2 The resistive random access memory (RANM) and its fabrication method according to the present invention are described by way of example. However, those skilled in the art should understand that various modifications can be made to the RANM and its fabrication method proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A method for fabricating a resistive random access memory (RANM), characterized in that, include: Metal deposition is performed on the bottom layer to form a lower electrode metal structure, and the lower electrode metal structure is etched to form a regularly distributed linear lower electrode. A ReRAM switching layer is formed on the lower electrode, and the ReRAM switching layer located at the bottom between two adjacent lower electrodes is removed so that the two adjacent ReRAM switching layers are spaced apart from each other, and the ReRAM switching layer only covers the side and top surfaces of the lower electrode; A dielectric material layer is filled on the ReRAM switching layer, the dielectric material layer filling between two adjacent ReRAM switching layers and covering the ReRAM switching layer. A metal contact for the lower electrode is provided on the dielectric material layer, and the metal contact extends between two adjacent ReRAM switching layers to form the resistive random access memory.

2. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The process of forming a ReRAM switching layer on the lower electrode includes: The ReRAM switching layer is grown on the lower electrode by means of atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or evaporation and / or sputtering and / or thermal growth; The ReRAM switching layer is distributed in a fish fin structure.

3. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The process of filling the dielectric material layer on the ReRAM switching layer includes: A dielectric material layer covering the ReRAM switching layer is formed on the ReRAM switching layer by means of atomic layer deposition and / or chemical vapor deposition and / or physical vapor deposition and / or thermal growth. The dielectric material layer is planarized to a preset etching position, which is not lower than the upper surface of the ReRAM switching layer, to form the basic structure of the resistive random access memory.

4. The method for fabricating a resistive random access memory as described in claim 3, characterized in that, The process of forming a metal contact for the lower electrode on the dielectric material layer includes: A metal via is provided between two adjacent ReRAM switching layers; A metal dielectric is filled into the metal hole, and the surface of the metal dielectric extends to the upper surface of the planarized dielectric material layer.

5. The method for fabricating a resistive random access memory as described in claim 4, characterized in that, The longitudinal section of the metal hole is conical, and the cross section of the metal hole is circular or elliptical.

6. The method for fabricating a resistive random access memory as described in claim 4, The metal holes are formed within the base structure by means of ALD, PVD, CVD, thermal growth, electroplating, vapor deposition, or sputtering.

7. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, After forming the ReRAM switching layer on the lower electrode, the method further includes: Photolithography is performed on the ReRAM switching layer, and the direction of the photolithography is perpendicular to the extension direction of the lower electrode; The photolithographic locations are filled with developer and etched to form a cross-sectional exchange matrix.

8. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The materials of the ReRAM switching layer include non-metals, metal oxides, metal nitrides, and inert metals.

9. A resistive random access memory, characterized in that, The resistive random access memory (RRAM) is prepared using the preparation method described in any one of claims 1 to 8.

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