Switching converter and control circuit and control method thereof

Abstract

A switching converter, a control circuit and a control method thereof are disclosed. The switching converter includes a power switching circuit having a power switch, and converts an input voltage signal into an output voltage signal by turning on and off the power switch. The control circuit includes a switch control circuit and a dummy load control circuit. The switch control circuit receives a feedback voltage signal representing the output voltage signal, and generates a switch control signal based on the feedback voltage signal to control the operation of the power switching circuit. The dummy load control circuit is coupled to the switch control circuit, and generates a dummy load control signal based on the operation of the switch control circuit to adjust a power value consumed by a dummy load coupled between an output terminal of the switching converter and a reference ground.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to a switching converter and its control circuit and control method. Background Technology

[0002] Switching converters are widely used in the power supply field. Typically, to reduce losses, the switching frequency gradually decreases as the load decreases. However, under light load or no-load conditions, the switching frequency may decrease to fall into the audio range, thus causing audio noise.

[0003] To address the above problems, this invention proposes a switching converter that can avoid audio noise even when operating under light load or no load. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a switching converter and its control circuit and control method to avoid the generation of audio noise by the switching converter under light load or no load.

[0005] According to one embodiment of the present invention, a control circuit for a switching converter is disclosed, wherein the switching converter includes a power switching circuit having a power switch, which converts an input voltage signal into an output voltage signal by turning the power switch on and off. The control circuit includes: a switch control circuit that receives a feedback voltage signal characterizing the output voltage signal and generates a switch control signal based on the feedback voltage signal to control the operation of the power switching circuit; and a dummy load control circuit coupled to the switch control circuit that generates a dummy load control signal based on the operation of the switch control circuit to adjust the power consumed by the dummy load coupled between the output terminal of the switching converter and a reference ground.

[0006] According to another embodiment of the present invention, a switching converter is disclosed, including a power switching circuit with a power switch, which converts an input voltage signal into an output voltage signal by turning the power switch on and off, and a control circuit as described above.

[0007] According to another embodiment of the present invention, a control method for a switching converter is disclosed, wherein the switching converter includes a power switching circuit having a power switch, and converts an input voltage signal into an output voltage signal by turning the power switch on and off. The control method includes: coupling a dummy load between the output terminal of the switching converter and a reference ground; generating a switching control signal based on a feedback voltage signal characterizing the output voltage signal to control the operation of the power switching circuit; and generating a dummy load control signal based on the switching control signal to adjust the power consumed by the dummy load.

[0008] According to an embodiment of the present invention, a dummy load is coupled between the output of the switching converter and the reference ground. The power consumed by the dummy load is adjusted by generating a dummy load control signal based on the operation of the switching control circuit. This method is simple and easy to implement, and can effectively avoid the generation of audio noise. Attached Figure Description

[0009] To better understand this invention, it will be described in detail with reference to the following drawings:

[0010] Figure 1 This is a schematic block diagram of a switching converter 100 according to an embodiment of the present invention;

[0011] Figure 2 This is a circuit diagram of a switching control circuit 201A for a switching converter 100 according to an embodiment of the present invention.

[0012] Figure 3 This is a circuit diagram of a dummy load control circuit 202A for a switching converter 100 according to an embodiment of the present invention.

[0013] Figure 4 This is a circuit diagram of a control circuit 20B for a switching converter 100 according to yet another embodiment of the present invention;

[0014] Figure 5 This is a circuit diagram of a switch control circuit 201B for a control circuit 20B according to an embodiment of the present invention.

[0015] Figure 6 This is a circuit diagram of a dummy load control circuit 202B for a control circuit 20B according to an embodiment of the present invention.

[0016] Figure 7 This is a flowchart of a control method 700 for a switching converter 100 according to an embodiment of the present invention. Detailed Implementation

[0017] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following detailed description of the invention, numerous details are described to better understand it. However, those skilled in the art will understand that the invention can be practiced without these specific details. To clearly illustrate the invention, some detailed descriptions of specific structures and functions have been simplified herein. Furthermore, similar structures and functions that have been described in detail in some embodiments will not be repeated in other embodiments. Although the terminology of the invention is described in connection with specific exemplary embodiments, these terms should not be construed as limiting the exemplary embodiments described herein.

[0018] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0019] Figure 1 This is a schematic block diagram of a switching converter 100 according to an embodiment of the present invention. Figure 1 As shown, the switching converter 100 includes a power switching circuit 10 and a control circuit 20. The power switching circuit 10 includes a power switch, and the switching converter 100 converts the input voltage signal VIN into an output voltage signal VOUT to power an external load (not shown) by turning the power switch on and off. Those skilled in the art will understand that the switching converter 100 can be configured as any suitable DC / DC or AC / DC converter topology, such as synchronous or asynchronous buck, boost, forward, or flyback converters. The power switch of the switching converter 100 can be any controllable semiconductor device, such as a BJT, JFET, MOSFET, or IGBT.

[0020] The control circuit 20 includes a switch control circuit 201, a dummy load control circuit 202, and a dummy load DR, wherein the dummy load DR is coupled between the output of the switching converter 100 and a reference ground. In one embodiment, the dummy load DR is a controllable semiconductor device. In another embodiment, the dummy load is a variable resistor. In one embodiment, the control circuit 20 may be integrated into a single chip. Those skilled in the art will understand that the external load refers to the actual load of the switching converter 100, and the dummy load DR is part of the control circuit 20, which can adjust the power consumed by the dummy load DR to meet the needs of the switching converter 100 and / or the external load.

[0021] The switch control circuit 201 receives a feedback voltage signal VFB that characterizes the output voltage signal VOUT, and generates a switch control signal CTRL based on the feedback voltage signal VFB to control the operation of the power switch circuit 10.

[0022] A dummy load control circuit 202 is coupled to a switch control circuit 201 and generates a dummy load control signal GT based on the operation of the switch control circuit 201 to adjust the power consumed by the dummy load DR. In one embodiment, the dummy load DR is a controllable semiconductor device, and the dummy load control circuit 202 is coupled to the control terminal of the controllable switch device to provide the dummy load control signal GT. The dummy load control circuit 202 generates a control current signal to the control terminal of the controllable switch device to adjust the dummy load control signal GT, thereby adjusting the power consumed by the dummy load DR. In another embodiment, the dummy load DR is a variable resistor, and the dummy load control signal GT increases / decreases the resistance value of the variable resistor to decrease / increase its power consumption.

[0023] In one embodiment, the control circuit 20 further includes a feedback circuit 203. The feedback circuit 203 receives the output voltage signal VOUT and generates a feedback voltage signal VFB based on the output voltage signal VOUT.

[0024] Figure 2 This is a circuit diagram of a switching control circuit 201A for a switching converter 100 according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, the switch control circuit 201A includes a first comparison unit 21, an on-time signal generation unit 22, and a first RS flip-flop 23. The first comparison unit 21 receives a feedback voltage signal VFB and generates a first comparison signal CA1 based on the feedback voltage signal VFB and a reference voltage signal VREF. In one embodiment, the first comparison unit 21 includes a first comparator CMP1, having a non-inverting input, an inverting input, and an output. The non-inverting input receives the reference voltage signal VREF, and the inverting input receives the feedback voltage signal VFB. The first comparator CMP1 compares the feedback voltage signal VFB and the reference voltage signal VREF and generates the first comparison signal CA1 at its output.

[0025] The on-time signal generation unit 22 receives the input voltage signal VIN and the output voltage signal VOUT, and generates an on-time signal TON based on the input voltage signal VIN and the output voltage signal VOUT to adjust the on-time of the power switch. In another embodiment, the on-time signal generation unit 22 does not receive the input voltage signal VIN and the output voltage signal VOUT, but generates the on-time signal TON only based on a fixed signal inside the on-time signal generation unit 22.

[0026] The first RS flip-flop 23 has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S receives a first comparison signal CA1, and the reset terminal R receives an on-time signal TON. Based on the first comparison signal CA1 and the on-time signal TON, the first RS flip-flop 23 generates a switch control signal CTRL at its output terminal Q.

[0027] although Figure 2 The illustrated embodiment employs constant on-time control; however, those skilled in the art will understand that this embodiment is merely illustrative and not intended to limit the invention. Other control methods capable of achieving the same or similar functions, such as voltage control, current control, and off-time control, also satisfy the spirit and scope of this invention.

[0028] Figure 3 This is a circuit diagram of a dummy load control circuit 202A for a switching converter 100 according to an embodiment of the present invention. Figure 3 As shown, the dummy load control circuit 202A receives the switch control signal CTRL generated by the switch control circuit 201, and generates a dummy load control signal GT based on the switch control signal CTRL to control the dummy load DR. The dummy load control circuit 202A includes a timing unit 31, a charge / discharge control unit 32, and a capacitor C. The timing unit 31 receives the switch control signal CTRL to generate a timing signal TE, wherein when the timing duration of the timing unit 31 is less than a first time threshold Tth1, the timing signal TE is in a first state; when the timing duration of the timing unit 31 is greater than the first time threshold Tth1, the timing signal TE is switched to a second state. The capacitor C is coupled between the control terminal of the dummy load DR and the reference ground. The charge / discharge control unit 32 discharges the capacitor C in response to the timing signal TE in the first state, and charges the capacitor C in response to the timing signal TE in the second state. In one embodiment, the timing unit 31 can start timing from the on or off moment of the power switch.

[0029] exist Figure 3In the illustrated embodiment, the timing unit 31 includes a first monostable multivibrator 311 and a first timer 312. The first monostable multivibrator 311 receives a switch control signal CTRL and generates a first short pulse signal SP1 based on the switch control signal CTRL. The first timer 312 receives the first short pulse signal SP1 and generates a timing signal TE based on the first short pulse signal SP1. Specifically, when the power switch is turned on, i.e., when the rising edge of the switch control signal CTRL arrives, the first monostable multivibrator 311 generates the first short pulse signal SP1. The first timer 312 starts timing under the trigger of the first short pulse signal SP1. At this time, the timing signal TE is in a first state (e.g., a high-level state). If the timing duration of the first timer 312 is equal to the first time threshold Tth1 before the next rising edge of the switch control signal CTRL arrives, the timing signal TE is switched to the second state (e.g., low level). Then, when the next rising edge of the switch control signal CTRL arrives, the first timer 312 restarts timing, and the timing signal TE is switched back to the first state. If the next rising edge of the switch control signal CTRL arrives before the timing duration of the first timer 312 equals the first time threshold Tth1, the first timer 312 directly restarts timing, and the timing signal TE remains in the first state. In other words, when the switch period T is greater than the first time threshold Tth1, within the switch period T, the timing signal TE is in the first state during the time interval from 0 to Tth1, and in the second state during the time interval from Tth1 to T. When the switch period T is less than the first time threshold Tth1, the timing signal TE is always in the first state. In one embodiment, the first time threshold Tth1 corresponds to the first frequency threshold fth1, where Tth1 = 1 / 2 / fth1. For example, when the first frequency threshold fth1 is 45kHz, the first time threshold Tth1 is approximately 11μs.

[0030] The charge / discharge control unit 32 includes a discharge current source I1, a charging current source I2, a discharge control switch S1, and a charging control switch S2. Both the discharge control switch S1 and the charging control switch S2 are controlled by a timing signal TE. In response to the timing signal TE in a first state, the discharge control switch S1 controls the discharge current source I1 to discharge the capacitor C, providing a negative control current signal. In response to the timing signal TE in a second state, the charging control switch S2 controls the charging current source I2 to charge the capacitor C, providing a positive control current signal. In one embodiment, the control current signals provided by the discharge current source I1 and the charging current source I2 have equal absolute values.

[0031] Depend on Figure 3It can be seen that when the switching frequency f is less than the first frequency threshold fth1, i.e., T > 2 * Tth1, the duration of the timing signal TE in the first state is less than the duration of the timing signal TE in the second state. The voltage across capacitor C, i.e., the dummy load control signal GT, increases, thereby increasing the power consumed by the dummy load DR. The total load of the switching converter 100 (the sum of the external load and the dummy load) becomes heavier. Through feedback control, the switching frequency f increases. When the switching frequency f increases to the first frequency threshold fth1, i.e., T = 2 * Tth1, the duration of the timing signal TE in the first state is equal to the duration of the timing signal TE in the second state. The dummy load control signal GT remains unchanged, and the power consumed by the dummy load DR also remains unchanged, and the system reaches a stable state. When the switching frequency f is greater than the second frequency threshold fth2, where the second frequency threshold fth2 is twice the first frequency threshold fth2, i.e., T < Tth1, the timing signal TE remains in the first state, the dummy load control signal GT is zero, and thus the power consumed by the dummy load DR is also zero. At this time, the dummy load DR has no effect on the switching converter 100. When the switching frequency f is between the first frequency threshold fth1 and the second frequency threshold fth2, i.e., Tth1 < T < 2*Tth1, the duration of the timing signal TE in the first state is greater than the duration of the timing signal TE in the second state. The dummy load control signal GT is a very small value, thus controlling the power consumed by the dummy load DR to be very small, for example, less than a first power threshold. At this time, since the power consumed by the dummy load DR is very small, its impact on the switching converter 100 is also very small.

[0032] Figure 4 This is a circuit diagram of a control circuit 20B for a switching converter 100 according to yet another embodiment of the present invention. Figure 4 As shown, the control circuit 20B includes a switch control circuit 201B, a dummy load control circuit 202, and a dummy load DR.

[0033] The switch control circuit 201B includes a turn-on control module 24, an error amplification module 25, a turn-off control module 26, and a logic module 27. The turn-on control module 24 generates a turn-on control signal CLK to control the power switch's turn-on. The error amplification module 25 receives a feedback voltage signal VFB and amplifies the difference between a reference voltage signal VREF and the feedback voltage signal VFB to generate an error amplification signal VEA. The turn-off control module 26 is coupled to the error amplification module 25 to receive the error amplification signal VEA and generates a turn-off control signal CA2 based on the error amplification signal VEA to control the power switch's turn-off. The logic module 27 generates a switch control signal CTRL based on the turn-on control signal CLK and the turn-off control signal CA2.

[0034] The dummy load control circuit 202 is coupled to the error amplifier module 25 to receive the error amplification signal VEA, and generates a dummy load control signal GT based on the error amplification signal VEA to adjust the power consumed by the dummy load DR. When the error amplification signal VEA is less than a voltage threshold vth, the power consumed by the dummy load DR increases as the error amplification signal VEA decreases. When the error amplification signal VEA is greater than the voltage threshold vth, the power consumed by the dummy load DR is zero.

[0035] Figure 5 This is a circuit diagram of a switch control circuit 201B for a control circuit 20B according to an embodiment of the present invention. Figure 5 As shown, the switch control circuit 201B includes a turn-on control module 24, an error amplification module 25, a turn-off control module 26, and a logic module 27. The turn-on control module 24 receives the switch control signal CTRL and generates a turn-on control signal CLK based on the CTRL. Figure 5 In the embodiment shown, the conduction control module 24 also receives a load detection signal SL that characterizes the severity of the external load, and generates a conduction control signal CLK based on the switch control signal CTRL and the load detection signal SL. The load detection signal SL can be a signal obtained by detecting the output current of the switch converter 100, as long as it can characterize the severity of the external load on the switch converter 100.

[0036] The conduction control module 24 includes a feedback clock signal generation unit 241, a clock adjustment signal generation unit 242, and a logic unit 243. The feedback clock signal generation unit 241 receives a load detection signal SL and generates a first clock signal CLK1 based on the load detection signal SL. The frequency of the first clock signal CLK1 decreases as the load becomes lighter and increases as the load becomes heavier. In another embodiment, the feedback clock signal generation unit 241 does not receive the load detection signal SL but instead generates a first clock signal CLK1 with a fixed frequency.

[0037] The clock adjustment signal generation unit 242 receives the switch control signal CTRL and generates a second clock signal CLK2 based on the switch control signal CTRL, wherein the frequency f2 of the second clock signal CLK2 is equal to the first frequency threshold fth1. In one embodiment, the clock adjustment signal generation unit 242 includes a second monostable multivibrator 2421 and a second timer 2422. The second monostable multivibrator 2421 receives the switch control signal CTRL and generates a second short pulse signal SP2 based on the switch control signal CTRL. The second timer 2422 receives the second short pulse signal SP2 and generates the second clock signal CLK2 based on the second short pulse signal SP2. Specifically, when the power switch is turned on, that is, when the rising edge of the switch control signal CTRL arrives, the second monostable multivibrator 2421 generates the second short pulse signal SP2, and the second timer 2422 starts timing under the trigger of the second short pulse signal SP2. If the timing duration of the second timer 2422 has reached the second time threshold Tth2 before the next rising edge of the switch control signal CTRL arrives, the second timer 2422 immediately generates a pulse signal as the second clock signal CLK2. In other words, the second timer 2422 generates a pulse signal every second time threshold Tth2. Therefore, the frequency f2 of the second clock signal CLK2 is 1 / Tth2. In one embodiment, the second time threshold Tth2 corresponds to the first frequency threshold fth1, where Tth2 = 1 / fth1. For example, when the first frequency threshold fth1 is 45kHz, the second time threshold Tth2 is approximately 22μs.

[0038] Logic unit 243 receives a first clock signal CLK1 and a second clock signal CLK2, and generates a turn-on control signal CTRL based on the first clock signal CLK1 and the second clock signal CLK2. In one embodiment, when the switching frequency f is greater than a first frequency threshold fth1, logic unit 243 outputs the first clock signal CLK1 as the turn-on control signal CLK; when the switching frequency f is less than the first frequency threshold fth1, logic unit 243 outputs the second clock signal CLK2 as the turn-on control signal CLK.

[0039] Error amplification module 25 receives the feedback voltage signal VFB and amplifies the difference between the reference voltage signal VREF and the feedback voltage signal VFB to generate an error amplification signal VEA. In one embodiment, error amplification module 25 includes an error amplifier EA with a non-inverting input, an inverting input, and an output. The non-inverting input receives the reference voltage signal VREF, and the inverting input receives the feedback voltage signal VFB. Based on the reference voltage signal VREF and the feedback voltage signal VFB, error amplifier EA generates the error amplification signal VEA at its output.

[0040] The shutdown control module 26 is coupled to the error amplification module 25 to receive the error amplification signal VEA and generate a shutdown control signal CA2 based on the error amplification signal VEA. In one embodiment, the shutdown control module 26 also receives a current detection signal VCS characterizing the current flowing through the energy storage element in the switching converter 100, and generates the shutdown control signal CA2 based on the error amplification signal VEA and the current detection signal VCS. Figure 5 In the illustrated embodiment, the shutdown control module 26 receives an error amplification signal VEA and a ramp signal VRAMP, or receives an error amplification signal VEA and a current detection signal VCS, to generate a shutdown control signal CA2. In one embodiment, the shutdown control module 26 includes a second comparator CMP2 with a non-inverting input, an inverting input, and an output. The non-inverting input receives the ramp signal VRAMP or the current detection signal VCS, and the inverting input receives the error amplification signal VEA. Based on the error amplification signal VEA and the ramp signal VRAMP or the current detection signal VCS, the second comparator CMP2 generates the shutdown control signal CA2 at its output.

[0041] Logic module 27 includes a second RS flip-flop, which has a set terminal S, a reset terminal R and an output terminal Q. The set terminal S receives a turn-on control signal CLK and the reset terminal R receives a turn-off control signal CA2. Based on the turn-on control signal CLK and the turn-off control signal CA2, the second RS flip-flop generates a switch control signal CTRL at its output terminal Q.

[0042] Figure 6 This is a circuit diagram of a dummy load control circuit 202B for a control circuit 20B according to an embodiment of the present invention. Figure 6 As shown, the dummy load control circuit 202B receives the error amplification signal VEA generated by the error amplification module 25 of the switch control circuit 201B, and generates a dummy load control signal GT based on the error amplification signal VEA to control the dummy load DR. The dummy load control circuit 202B includes a voltage-to-current conversion unit 33, a current clamping unit 34, and a dummy load control signal generation unit 35. The voltage-to-current conversion unit 33 receives the error amplification signal VEA and generates a conversion current signal it based on the error amplification signal VEA, wherein the conversion current signal it decreases as the error amplification signal VEA decreases. The current clamping unit 34 receives the conversion current signal it and generates a control current signal ic based on the conversion current signal it, wherein when the conversion current signal it is greater than a current threshold ith, the control current signal ic is a zero current signal, and when the conversion current signal it is less than the current threshold ith, the control current signal ic increases as the conversion current signal it decreases. The dummy load control signal generation unit 35 receives the control current signal ic and generates the dummy load control signal GT based on the control current signal ic.

[0043] exist Figure 6 In the illustrated embodiment, the voltage-to-current conversion unit 33 includes a transistor T and a first current mirror M1. The transistor T has a first terminal, a second terminal, and a control terminal, wherein the control terminal receives an error amplification signal VEA, the first terminal generates a first current signal i1, and the second terminal is coupled to a reference ground. The first current mirror M1 has an input terminal and an output terminal, wherein the input terminal receives the first current signal i1, and the output terminal generates a converted current signal it. The current clamping unit 34 includes a current source Ib and a second current mirror M2. The current source Ib provides a second current signal ib. The second current mirror M2 has an input terminal and an output terminal, wherein the input terminal receives the converted current signal it and the second current signal ib, and the output terminal generates a control current signal ic. The dummy load control signal generation unit 35 includes a resistor RG. The resistor RG has a first terminal and a second terminal, wherein the first terminal receives the control current signal ic, and the second terminal is coupled to a reference ground, wherein the voltage across the resistor RG is the dummy load control signal GT.

[0044] Depend on Figure 6 It can be seen that when the error amplification signal VEA is less than a voltage threshold vth, as the error amplification signal VEA decreases, the first current signal i1 decreases, and the conversion current signal it also decreases. At this time, the conversion current signal it is less than the second current signal ib, and the control current signal ic = ib - it. The control current signal ic increases as the conversion current signal it decreases, and the dummy load control signal GT increases, thereby increasing the power consumed by the dummy load DR. When the error amplification signal VEA is greater than the voltage threshold vth, the conversion current signal it is greater than the second current signal ib. At this time, the control current signal ic is a zero current signal, the dummy load control signal GT is zero, and thus the power consumed by the dummy load DR is zero.

[0045] According to embodiments of the present invention, audio noise generated by the switching converter can be effectively avoided. Furthermore, a dummy load control signal GT is generated based on the operation of the switching control circuit to adjust the power consumed by the dummy load DR. This method is simple and easy to implement, and the dummy load DR does not affect the efficiency of the switching converter.

[0046] Figure 7 This is a flowchart of a control method 700 for a switching converter 100 according to an embodiment of the present invention. The switching converter includes a power switch and converts an input voltage signal into an output voltage signal by turning the power switch on and off. The control method 700 includes steps S71 to S73.

[0047] In step S71, a dummy load is coupled between the output of the switching converter and the reference ground.

[0048] In step S72, a switching control signal is generated based on the feedback voltage signal characterizing the output voltage signal to control the operation of the power switching circuit.

[0049] In step S73, a dummy load control signal is generated based on the switch control signal to adjust the power consumed by the dummy load.

[0050] In one embodiment, generating a dummy load control signal based on a switch control signal includes: generating a timing signal based on the switch control signal, wherein when the timing duration is less than a first time threshold, the timing signal is in a first state, and when the timing duration is greater than the first time threshold, the timing signal is switched to a second state; coupling a capacitor between the control terminal of the dummy load and a reference ground to provide the dummy load control signal; and discharging the capacitor in response to the timing signal in the first state, and charging the capacitor in response to the timing signal in the second state.

[0051] In another embodiment, the control method 700 further includes: amplifying the difference between the reference voltage signal and the feedback voltage signal to generate an error amplification signal; generating a shutdown control signal based on the error amplification signal to control the shutdown of the power switch; and generating a dummy load control signal based on the error amplification signal, wherein when the error amplification signal is less than a first threshold voltage, the power consumed by the dummy load increases as the error amplification signal decreases.

[0052] In a further embodiment, generating a dummy load control signal based on an error amplification signal includes: generating a conversion current signal based on the error amplification signal, wherein the conversion current signal decreases as the error amplification signal decreases; generating a control current signal based on the conversion current signal, wherein when the conversion current signal is greater than a current threshold, the control current signal is a zero current signal, and when the conversion current signal is less than the current threshold, the control current signal increases as the conversion current signal decreases; and generating a dummy load control signal based on the control current signal.

[0053] Note that in the flowchart described above, the functions marked in the boxes may occur in a different order than shown in the diagram. For example, two boxes shown consecutively may actually be executed in essentially parallel order, or they may be executed in reverse order, depending on the specific functions involved.

[0054] In the specification and claims of this application, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply an order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in such an order or logical order, unless specifically specified in the language of the claims. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0055] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A control circuit for a switching converter, wherein the switching converter includes a power switching circuit with a power switch, which converts an input voltage signal into an output voltage signal by turning the power switch on and off, the control circuit comprising: The switching control circuit receives a feedback voltage signal that characterizes the output voltage signal, and generates a switching control signal based on the feedback voltage signal to control the operation of the power switching circuit. as well as A dummy load control circuit, coupled to a switch control circuit, generates a dummy load control signal based on the operation of the switch control circuit to adjust the power consumed by the dummy load coupled between the output of the switching converter and the reference ground. in When the switching frequency is less than the first frequency threshold, the power consumed by the dummy load is controlled by the dummy load control signal to increase as the switching frequency decreases.

2. The control circuit as described in claim 1, wherein: The dummy load is a controllable semiconductor device; and The dummy load control circuit is coupled to the control terminal of the controllable semiconductor device to provide a dummy load control signal and generate a control current signal related to the operation of the switching control circuit to adjust the dummy load control signal at the control terminal of the controllable semiconductor device.

3. The control circuit as described in claim 1, wherein: When the switching frequency is greater than the second frequency threshold, the dummy load control signal controls the power consumed by the dummy load to be zero; and When the switching frequency is between the first frequency threshold and the second frequency threshold, the dummy load control signal controls the power consumed by the dummy load to be less than the first power threshold.

4. The control circuit as described in claim 2, wherein the dummy load control circuit comprises: The timing unit receives a switch control signal to generate a timing signal. When the timing duration of the timing unit is less than a first time threshold, the timing signal is in a first state. When the timing duration of the timing unit is greater than the first time threshold, the timing signal is switched to a second state. as well as A capacitor is coupled between the control terminal of a controllable semiconductor device and a reference ground. The charge / discharge control unit discharges the capacitor in response to a timing signal in the first state and charges the capacitor in response to a timing signal in the second state.

5. The control circuit as described in claim 4, wherein the charge / discharge control unit comprises: A discharge control switch, in response to a timing signal in the first state, controls a discharge current source to discharge the capacitor, thereby providing a negative control current signal; as well as A charging control switch, in response to a timing signal in the second state, controls a charging current source to charge the capacitor to provide a positive control current signal, wherein the positive control current signal and the negative control current signal have equal absolute values.

6. A control circuit for a switching converter, wherein the switching converter includes a power switching circuit with a power switch, which converts an input voltage signal into an output voltage signal by turning the power switch on and off, the control circuit comprising: The error amplification module receives the feedback voltage signal that characterizes the output voltage signal and amplifies the difference between the reference voltage signal and the feedback voltage signal to generate an error amplification signal. The switching control circuit is coupled to the error amplifier module to receive the error amplification signal and generate a switching control signal based on the error amplification signal to control the operation of the power switching circuit. as well as The dummy load control circuit receives the error amplification signal generated by the error amplification module and generates a dummy load control signal based on the error amplification signal to adjust the power consumed by the dummy load coupled between the output of the switching converter and the reference ground. in When the error amplification signal is less than a voltage threshold, the power consumed by the dummy load is controlled by the dummy load control signal to increase as the error amplification signal decreases.

7. The control circuit of claim 6, wherein the dummy load control circuit comprises: The voltage-to-current conversion unit receives the error amplification signal and generates a conversion current signal, wherein the conversion current signal decreases as the error amplification signal decreases; A current clamping unit is coupled to a voltage-to-current conversion unit to receive a converted current signal and generate a control current signal based on the converted current signal. When the converted current signal is greater than a current threshold, the control current signal is a zero current signal. When the converted current signal is less than the current threshold, the control current signal increases as the converted current signal decreases. as well as The dummy load control signal generation unit is coupled to the current clamping unit to receive the control current signal and generate a dummy load control signal based on the control current signal.

8. The control circuit of claim 7, wherein the voltage-to-current conversion unit comprises: A transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal receives an error amplification signal, the first terminal generates a first current signal, and the second terminal is coupled to a reference ground. as well as The first current mirror has an input terminal and an output terminal, wherein the input terminal receives a first current signal and the output terminal generates a converted current signal.

9. The control circuit of claim 7, wherein the current clamping unit comprises: A current source provides a second current signal; as well as The second current mirror has an input terminal and an output terminal, wherein the input terminal receives a second current signal and a converted current signal, and the output terminal generates a control current signal.

10. A switching converter, wherein the switching converter comprises: A power switching circuit has a power switch that converts an input voltage signal into an output voltage signal by turning the power switch on and off. as well as The control circuit as described in any one of claims 1-9.

11. A control method for a switching converter, wherein the switching converter includes a power switching circuit with a power switch, and converts an input voltage signal into an output voltage signal by turning the power switch on and off, the control method comprising: Couple the dummy load between the output of the switching converter and the reference ground; A switching control signal is generated based on the feedback voltage signal characterizing the output voltage signal to control the operation of the power switching circuit; as well as A dummy load control signal is generated based on the switch control signal to adjust the power consumed by the dummy load; whereby... When the switching frequency is less than the first frequency threshold, the power consumed by the dummy load is controlled by the dummy load control signal to increase as the switching frequency decreases.

12. The control method of claim 11, wherein the method for generating a dummy load control signal based on a switch control signal comprises: A timing signal is generated based on the switch control signal, wherein the timing signal is in the first state when the timing duration is less than the first time threshold. When the timing duration exceeds the first time threshold, the timing signal is switched to the second state; A capacitor is coupled between the control terminal of the dummy load and the reference ground to provide a dummy load control signal; as well as The capacitor is discharged in response to the timing signal of the first state, and charged in response to the timing signal of the second state.

13. A control method for a switching converter, wherein the switching converter includes a power switching circuit with a power switch, and converts an input voltage signal into an output voltage signal by turning the power switch on and off, the control method comprising: Couple the dummy load between the output of the switching converter and the reference ground; The difference between the reference voltage signal and the feedback voltage signal characterizing the output voltage signal is amplified to generate an error amplification signal; The error amplification signal is used to generate a switching control signal to control the operation of the power switching circuit; and A dummy load control signal is generated based on the error amplification signal to adjust the power consumed by the dummy load; whereby... When the error amplification signal is less than a voltage threshold, the power consumed by the dummy load is controlled by the dummy load control signal to increase as the error amplification signal decreases.

14. The control method of claim 13, wherein the method for generating a dummy load control signal based on the error amplification signal comprises: A conversion current signal is generated based on the error amplification signal, wherein the conversion current signal decreases as the error amplification signal decreases; A control current signal is generated based on the converted current signal, wherein when the converted current signal is greater than a current threshold, the control current signal is a zero current signal; when the converted current signal is less than the current threshold, the control current signal increases as the converted current signal decreases; and A dummy load control signal is generated based on the control current signal.

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