A multi-channel synchronous data acquisition device and method with adjustable input voltage range

Abstract

The present invention relates to a multi-channel synchronous data acquisition device and method with an adjustable input voltage range. The device includes a clock selection unit, a voltage gear switching unit, and an AD sampling processing unit. The multi-channel synchronous processing unit and the voltage gear switching unit are both electrically connected to the AD sampling processing unit. The clock selection unit is used to output a multi-channel synchronous sampling clock signal. The voltage gear switching unit includes two or more gear control circuits connected in series. The voltage gear switching unit is used to control the corresponding gear control circuit to output a gain signal to achieve the output of a target gain signal through a relay. The AD sampling processing unit is used to sample the target gain signal input by the corresponding channel according to the multi-channel synchronous sampling clock signal. The voltage gear switching is achieved by the cooperation of the input voltage control circuit and the relay, thereby achieving an adjustable voltage range for data acquisition.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and in particular to a multi-channel synchronous data acquisition device and method with adjustable input voltage range. Background Art

[0002] Field signals play a vital role in fields such as radar, meteorology, earthquake prediction, aerospace, and communications. These signals are characterized by strong real-time performance, high data rates, large data volumes, complex processing, and high computational complexity. Therefore, high-speed data acquisition has long been a field of significant interest in engineering practice.

[0003] The rapid development of digital signals is driving increasing demands on signal acquisition, particularly in terms of parameters such as accuracy, speed, and sampling channel synchronization. For example, in distributed fiber-optic acoustic wave sensing monitoring systems, the synchronization, accuracy, and acquisition rate of data across each channel are particularly demanding. However, existing technologies for such monitoring systems suffer from poor multi-channel synchronization and a fixed voltage range for data acquisition, making them unable to meet the multi-channel acquisition requirements of such systems.

[0004] Therefore, it is necessary to provide a data acquisition device with multi-channel synchronous acquisition and adjustable input voltage range to solve the above technical problems. Summary of the Invention

[0005] To address the above technical issues, the present invention provides a multi-channel synchronous data acquisition device with an adjustable input voltage range. This device addresses the technical issues in existing monitoring systems, such as poor multi-channel synchronization and a fixed voltage range for data acquisition, which cannot meet the multi-channel acquisition requirements of monitoring systems.

[0006] The technical effects of the present invention are achieved as follows:

[0007] A multi-channel synchronous data acquisition device with adjustable input voltage range includes a clock selection unit, a voltage gear switching unit and an AD sampling processing unit, wherein the multi-channel synchronous processing unit and the voltage gear switching unit are both electrically connected to the AD sampling processing unit.

[0008] A clock selection unit, used for outputting multi-channel synchronous sampling clock signals;

[0009] A voltage gear switching unit, the voltage gear switching unit is used to adjust the gear gain of the input voltage signal, the voltage gear switching unit includes two or more gear control circuits connected in series, each of the multiple gear control circuits includes a corresponding relay, and the voltage gear switching unit is used to control the corresponding gear control circuit through the relay to output a gain signal to adjust the gear gain of the voltage gear switching unit to achieve the output of a target gain signal;

[0010] The AD sampling processing unit is used to sample the target gain signal inputted by the corresponding channel according to the synchronous sampling clock signal of the multiple channels.

[0011] Furthermore, the gear control circuit further includes a differential drive chip, and the differential drive chip is used to process the input voltage signal input thereto to obtain a corresponding gain differential signal and input it to the corresponding relay.

[0012] Furthermore, the relay is a single-pole double-throw relay, and the single-pole double-throw relay is configured such that when a switch within the single-pole double-throw relay contacts a first contact, the signal output terminal outputs the gain differential signal; and when the switch within the single-pole double-throw relay contacts a second contact, the signal output terminal outputs the corresponding input voltage signal of the differential driver chip. The gear control circuit and the single-pole double-throw relay cooperate, so that when the switch within the single-pole double-throw relay contacts the first contact, the signal output terminal outputs the gain differential signal output by the gear control circuit connected to the front end of the single-pole double-throw relay, thereby superimposing the voltage gain of the gear control circuit on the target gain signal; and when the switch within the single-pole double-throw relay contacts the second contact, the signal output terminal outputs the input voltage signal of the gear control circuit, so that the voltage gain of the gear control circuit is not used on the target gain signal. Thus, by completing the selection of the voltage gain of the gear control circuit at each level, the input voltage gear of the voltage gear switching unit is adjustable.

[0013] Furthermore, the clock selection unit includes a clock generator, an onboard clock source and an external clock source. The clock generator is used to use the external clock source as a reference clock source for the clock generator when the external clock source is input; and to use the onboard clock source as a reference clock source for the clock generator when the external clock source is not input.

[0014] Furthermore, the external clock source includes at least a first external clock source and a second external clock source, the first external clock source is electrically connected to the first reference clock input terminal of the clock generator through a first relay, and the second external clock source is electrically connected to the second reference clock input terminal of the clock generator through a second relay, and the clock selection unit is used to control one of the first relay and the second relay to be turned on through the FPGA to complete the switching of the external clock source.

[0015] Furthermore, the FPGA is used to complete synchronization calibration of the multi-channel synchronous sampling clock signals input to the AD sampling processing unit by inputting synchronization signals at a preset period through the hardware synchronization port of the AD sampling processing unit. Because the two or more synchronous sampling clock signals output by the clock generator have RMS integrated jitter, this can cause an increase in signal frequency errors between channels during long-term operation. Therefore, the FPGA is used to complete synchronization calibration of the multi-channel synchronous sampling clock signals input to the AD sampling processing unit by inputting synchronization signals at a preset period through the hardware synchronization port of the AD sampling processing unit. This achieves synchronization of multi-channel data acquisition through the two mechanisms of providing the two or more synchronous sampling clock signals to the AD sampling processing unit by the clock generator and hardware calibration synchronization of the AD sampling processing unit.

[0016] In addition, a multi-channel synchronous data acquisition method with an adjustable input voltage range is also provided. The method is implemented based on the above-mentioned multi-channel synchronous data acquisition device with an adjustable input voltage range. The voltage gear switching unit includes at least two gear control circuits connected in series, namely a first-stage gain control circuit and a second-stage gain control circuit. The gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit are both greater than 1 times the gain. The gear control circuit includes a differential drive chip, which is used to process the input voltage signal input thereto to obtain a corresponding gain differential signal and input it to the corresponding relay, including:

[0017] When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, controlling the relay corresponding to the first-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip, and simultaneously controlling the relay corresponding to the second-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip;

[0018] When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, controlling the relay corresponding to the first-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip, and simultaneously controlling the relay corresponding to the second-stage gain control circuit to output the input voltage signal of the corresponding differential driver chip;

[0019] When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, the relay corresponding to the first-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip, and at the same time, the relay corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip.

[0020] In addition, a multi-channel synchronous data acquisition method with an adjustable input voltage range is also provided. The method is implemented based on the above-mentioned multi-channel synchronous data acquisition device with an adjustable input voltage range. The voltage gear switching unit includes at least three gear control circuits connected in series, namely a first-stage gain control circuit, a second-stage gain control circuit, and a third-stage gain control circuit. The gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit are both greater than 1x gain, and the gear gain of the third-stage gain control circuit is 1x gain. The gear control circuit includes a differential drive chip, which is used to process the input voltage signal input thereto to obtain a corresponding gain differential signal and input it into the corresponding relay, including:

[0021] When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, controlling the relay corresponding to the first-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip, and simultaneously controlling the relay corresponding to the second-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip;

[0022] When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, controlling the relay corresponding to the first-stage gain control circuit to output the gain differential signal output by the corresponding differential driver chip, and simultaneously controlling the relay corresponding to the second-stage gain control circuit to output the input voltage signal of the corresponding differential driver chip;

[0023] When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, controlling the relay corresponding to the first-stage gain control circuit to output the corresponding input voltage signal of the differential drive chip, and simultaneously controlling the relay corresponding to the second-stage gain control circuit to output the corresponding gain differential signal output by the differential drive chip;

[0024] When the target gear gain of the target gain signal is 1x gain, the relay corresponding to the first-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip, and the relay corresponding to the second-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip, and the relay corresponding to the third-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip.

[0025] Furthermore, the multi-channel synchronous data acquisition method with adjustable input voltage range also includes:

[0026] When an external clock source is input into the clock generator, the external clock source is used as a reference clock source of the clock generator;

[0027] When no external clock source is input into the clock generator, the onboard clock source is used as a reference clock source of the clock generator.

[0028] Furthermore, the multi-channel synchronous data acquisition method with adjustable input voltage range also includes:

[0029] Based on the preset cycle control synchronization signal input to the hardware synchronization port of the AD sampling processing unit,

[0030] The synchronous sampling clock signals of the multiple channels inputted by the AD sampling processing unit are synchronously calibrated.

[0031] As described above, the present invention has the following beneficial effects:

[0032] 1) By cooperating with the gear control circuit and the single-pole double-throw relay, when the switch inside the single-pole double-throw relay contacts the first contact, its signal output end outputs a gain differential signal output by the gear control circuit connected to the front end of the single-pole double-throw relay, so that the voltage gain of this gear control circuit is superimposed on the target gain signal; when the switch inside the single-pole double-throw relay contacts the second contact, its signal output end outputs the input voltage signal of the gear control circuit, so that the voltage gain of this gear control circuit is not used on the target gain signal, thereby achieving adjustable input voltage gear of the voltage gear switching unit by completing the selection of the voltage gain of the gear control circuit at each level.

[0033] 2) FPGA is used to input a synchronization signal according to a preset period through the hardware synchronization port of the AD sampling processing unit to complete the synchronous calibration of the multi-channel synchronous sampling clock signals input by the AD sampling processing unit. By using the two mechanisms of providing two or more synchronous sampling clock signals to the AD sampling processing unit by the clock generator and the hardware calibration synchronization of the AD sampling processing unit, the synchronization of multi-channel data acquisition is achieved, which solves the problem that the two or more synchronous sampling clock signals output by the clock generator have RMS integrated jitter, which will cause the signal frequency error between channels to increase in long-term operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0035] Figure 1 This is a structural block diagram of a multi-channel synchronous data acquisition device with adjustable input voltage range provided in an embodiment of this specification;

[0036] Figure 2 A schematic diagram of a gear control circuit in a clock selection unit provided in an embodiment of this specification;

[0037] Figure 3 A schematic diagram of a relay in a clock selection unit provided in an embodiment of this specification;

[0038] Figure 4 A logic block diagram of the gear gain switching process of the voltage gear switching unit provided in the embodiment of this specification;

[0039] Figure 5 A schematic diagram of a clock selection unit provided in an embodiment of this specification;

[0040] Figure 6 A logic block diagram of outputting a synchronous sampling clock signal and performing synchronous calibration on the synchronous sampling clock signal provided in an embodiment of this specification;

[0041] Figure 7 This is a schematic diagram of the AD sampling processing unit provided in the embodiments of this specification.

[0042] Among them, the reference numerals in the figure correspond to:

[0043] Clock selection unit 1, clock generator 11, voltage gear switching unit 2, gear control circuit 21, relay 22, AD sampling processing unit 3. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] Example 1:

[0047] like Figure 1-7 As shown, the embodiment of this specification provides a multi-channel synchronous data acquisition device with an adjustable input voltage range, including a clock selection unit 1, a voltage gear processing unit 2 and an AD sampling processing unit 3, and the multi-channel synchronous processing unit and the voltage gear processing unit 2 are electrically connected to the AD sampling processing unit 3.

[0048] Clock selection unit 1, used for outputting multi-channel synchronous sampling clock signals;

[0049] The voltage gear processing unit 2 is used to adjust the gear gain of the input voltage signal. The voltage gear processing unit 2 includes two or more gear control circuits 21 connected in series. The multiple gear control circuits 21 each include a corresponding relay 22. The voltage gear processing unit 2 is used to control the corresponding gear control circuit 21 through the relay 22 to output a gain signal to adjust the gear gain of the voltage gear processing unit 2 to achieve the output of the target gain signal;

[0050] The AD sampling processing unit 3 is used to sample the target gain signal input from the corresponding channel according to the synchronous sampling clock signal of the multiple channels.

[0051] Preferably, the gear control circuit 21 further includes a differential driving chip, which is used to process the input voltage signal input thereto to obtain a corresponding gain differential signal and input it to the corresponding relay 22 .

[0052] Preferably, the relay 22 is a single-pole double-throw relay 22, and the single-pole double-throw relay 22 is configured so that when the switch inside the single-pole double-throw relay 22 contacts the first contact, the signal output end outputs a gain differential signal; when the switch inside the single-pole double-throw relay 22 contacts the second contact, the signal output end outputs the input voltage signal of the corresponding differential driver chip.

[0053] It should be noted that, through the cooperation between the gear control circuit 21 and the single-pole double-throw relay, when the switch inside the single-pole double-throw relay contacts the first contact, its signal output end outputs the gain differential signal output by the gear control circuit 21 connected to the front end of the single-pole double-throw relay, so that the voltage gain of this gear control circuit 21 is superimposed on the target gain signal; when the switch inside the single-pole double-throw relay contacts the second contact, its signal output end outputs the input voltage signal of the gear control circuit 21, so that the voltage gain of this gear control circuit 21 is not used on the target gain signal, thereby making it possible to adjust the input voltage gear of the voltage gear switching unit 2 by completing the selection of the voltage gain of the gear control circuit 21 at each level.

[0054] Specifically, this embodiment takes the voltage gear processing unit 2 as an example, which includes three gear control circuits 21 connected in series, and the gear gains GAIN of the three gear control circuits 21 are 2, 4 and 1 respectively, so as to enable the voltage gear processing unit 2 to switch among four gear gains of 1, 2, 4 and 8 through different combinations of the gear control circuits 21.

[0055] The three gear control circuits 21 connected in series are divided into a first-stage gain control circuit, a second-stage gain control circuit and a third-stage gain control circuit according to their positional relationship. The gear gains of the first-stage gain control circuit, the second-stage gain control circuit and the third-stage gain control circuit are 2, 4 and 1 respectively.

[0056] This embodiment takes the gear gain switching of the first-stage gain control circuit as an example to illustrate as follows:

[0057] like Figure 2 As shown, the first stage gain control circuit is used to Figure 3 The differential driver chip U5 in the J3 input realizes a 2-fold gain of the collected signal. Figure 3 In the middle, R44 / R45=2, R51 / R49=2, achieving a 2-fold gear gain.

[0058] J3 is the input port of the voltage gear processing unit 2, that is, the input port of the acquisition signal of the first-stage gain control circuit, which is used to input the acquisition signal AD_IN signal. The -OUT and +OUT output pins of the differential driver chip U5 output the gain differential signals AD_IN1_OUT1- and AD_IN1_OUT1+ signals with 2 times the gear gain.

[0059] like Figure 3 As shown, the back end of the differential driver chip U5 is connected to a single-pole double-throw relay RLY3. The single-pole double-throw relay RLY3 has a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, and an eighth pin. The first, second, third, and fourth pins are the four pins on the left side of the single-pole double-throw relay RLY3, arranged from top to bottom. The fifth, sixth, seventh, and eighth pins are the four pins on the right side of the single-pole double-throw relay RLY3, arranged from bottom to top.

[0060] A first contact, a second contact, and a switch are provided inside the single-pole double-throw relay RLY3. The first contact is connected to the second pin and the seventh pin of the single-pole double-throw relay RLY3. The second contact is connected to the fourth pin and the fifth pin of the single-pole double-throw relay RLY3. The switch is connected to the third pin and the sixth pin of the single-pole double-throw relay RLY3.

[0061] Among them, the first contact is connected to the second pin and the seventh pin of the single-pole double-throw relay RLY3 for inputting AD_IN and GND signals respectively; the second contact is connected to the fourth pin and the fifth pin of the single-pole double-throw relay RLY3 for inputting AD_IN1_OUT1- and AD_IN1_OUT1+ signals respectively; the third pin and the sixth pin of the single-pole double-throw relay RLY3 are the output ports of the single-pole double-throw relay RLY3, which are used as the output ports of the first-stage gain control circuit.

[0062] Single-pole, double-throw relay RLY3 has a control pin. The FPGA inputs a control signal, AD_IN1_GAIN1, to the control pin, causing the switch inside RLY3 to contact the corresponding contact. This allows the selection of whether to use the differential gain signals AD_IN1_OUT1- and AD_IN1_OUT1+, which have a 2x gain, output by differential driver chip U5. The FPGA is the processing center of the multi-channel synchronous data acquisition device with an adjustable input voltage range. It is used to determine whether the ADC sampling chip in AD sampling processing unit 3 is operational, select the gain, and calibrate clock synchronization.

[0063] That is, when the switch inside the single-pole double-throw relay RLY3 is controlled to contact the second contact, the single-pole double-throw relay RLY3 outputs the AD_IN1_OUT1- and AD_IN1_OUT1+ signals to the second-stage gain control circuit, achieving a 2x gain; when the switch inside the single-pole double-throw relay RLY3 is controlled to contact the first contact, the single-pole double-throw relay RLY3 outputs the AD_IN and GND signals to the second-stage gain control circuit, and the 2x gain of the first-stage gain control circuit is not selected for use on the target gain signal of the voltage gear processing unit 2, that is, the AD_IN signal input to J3 is directly output to the second-stage gain control circuit.

[0064] The second-stage gain control circuit uses the signals AD_IN1_OUT1- and AD_IN1_OUT1+, or the signals AD_IN and GND, output from single-pole, double-throw relay RLY3, as inputs to the positive input terminal +IN and the negative input terminal -IN of the corresponding differential driver chip. This serves as the input voltage for the second-stage gain control circuit. The shift gain switching process for the second-stage gain control circuit is the same as that for the first-stage gain control circuit described above.

[0065] Similarly, when the voltage gear processing unit 2 includes more than three gear control circuits 21, that is, a multi-stage gain control circuit, the gain control circuit of the previous stage completes the gear gain switching and outputs a corresponding signal to provide it to the gain control circuit of the next stage as its input voltage to complete its gear gain switching.

[0066] It should be noted that regardless of whether the voltage gear processing unit 2 includes a three-stage gain control circuit or a multi-stage gain control circuit with more than three stages, if the voltage gear processing unit 2 is required to output a 1x gain differential signal corresponding to the acquisition signal input by J3, then it is necessary to use a 1x gain gear control circuit 21 in the last-stage gain control circuit of the voltage gear processing unit 2, so that when all the previous-stage gain control circuits that control the last-stage gain control circuit do not use their gains, the acquisition signal input by J3 is passed through the last-stage gain control circuit with 1x gain to obtain a 1x gain differential signal corresponding to the acquisition signal, which is then input to the AD sampling processing unit 3.

[0067] Preferably, the clock selection unit 1 includes a clock generator 11, an onboard clock source and an external clock source. The clock generator 11 is configured to use the external clock source as a reference clock source for the clock generator 11 when an external clock source is input; and to use the onboard clock source as a reference clock source for the clock generator 11 when no external clock source is input.

[0068] Preferably, the external clock source includes at least a first external clock source and a second external clock source, the first external clock source is electrically connected to the first reference clock input terminal of the clock generator 11 through the first relay 22, and the second external clock source is electrically connected to the second reference clock input terminal of the clock generator 11 through the second relay 22, and the clock selection unit 1 is used to control one of the first relay 22 and the second relay 22 to be turned on through the FPGA to complete the switching of the external clock source.

[0069] Specifically, if Figure 5 As shown, J1, J2, and Y1 are the clock sources of clock selection unit 1. Among them, Y1 is the onboard clock source and has the lowest priority. J1 and J2 are the first and second external clock sources, respectively. When J1 and J2 are not available, the reference clock source is Y1. When J1 or J2 is available and connected to clock generator 11, the reference clock source is J1 or J2, which realizes the switchability of clock sources.

[0070] Among them, the switching of J1 and J2 clock sources is controlled by FPGA. Figure 5 The switching process of the clock sources J1 and J2 is not described in detail in this application.

[0071] In this embodiment, the AD sampling processing unit 3 includes one ADC sampling chip.

[0072] The reference clock source is determined by the clock selection unit 1 and provided to the clock generator. After passing through the internal phase-locked loop PLL of the clock generator 11, it is multiplied to generate two 500MHz clocks, which are provided to the ADC sampling chips as their clock signals (meeting the 250MSPS sampling requirements). Since the clock signals are generated by the same clock generator and the same PLL, the signal frequency is guaranteed.

[0073] Preferably, the FPGA is used to complete synchronization calibration of the multi-channel synchronous sampling clock signals input by the AD sampling processing unit 3 by inputting synchronization signals according to a preset period through the hardware synchronization port of the AD sampling processing unit 3. The preset period can be set by those skilled in the art. In this embodiment, the preset period is 1 second.

[0074] In this embodiment, the clock generator 11 generates two 500MHz clock signals, which are respectively provided to two ADC sampling chips. However, since the clock generator 11 signal itself has an RMS (root mean square) integrated jitter of up to 150fs, it will cause the signal frequency error between channels to accumulate continuously under long-term operation. In order to eliminate this error, the FPGA is used to simultaneously input a calibration signal to the SYNCINP and SYNCINM synchronization pins of the two ADC sampling chips every 1s, so that the clock signals obtained by the two ADC sampling chips are synchronously calibrated once, that is, the accumulated error is cleared, thereby ensuring the synchronization of the 500MHz clock signals obtained by the two ADC sampling chips.

[0075] In this embodiment, Figure 7 As shown, the original input signal passes through Figure 4 After being processed by the voltage gear switching unit 2, it is transmitted in the form of a gain differential signal. Figure 5 The two pairs of signal input pins INBP, INBM or INAP, INAM of the ADC sampling chip U37 chip are provided to the ADC sampling chip. The data obtained after processing by the ADC sampling chip communicates with the FPGA through LVDS signal (low voltage differential signal).

[0076] In some other embodiments, the AD sampling processing unit 3 may include two or more ADC sampling chips. Figure 7 As shown, when the clock generator 11 has four sampling channels, the FPGA can send commands to two ADC sampling chips at fixed times through the SYNCINP and SYNCINM synchronization pins, so that the two ADC sampling chips can sample synchronously.

[0077] FPGA is used to input a synchronization signal according to a preset period through the hardware synchronization port of the AD sampling processing unit 3 to complete the synchronization calibration of the multi-channel synchronous sampling clock signal input by the AD sampling processing unit 3, so that the synchronization of multi-channel data acquisition is achieved by using two mechanisms: the two-way or multi-way synchronous sampling clock signal provided by the clock generator 11 to the AD sampling processing unit 3 and the hardware calibration synchronization of the AD sampling processing unit 3. This solves the problem that the two-way or multi-way synchronous sampling clock signal output by the clock generator 11 has RMS integrated jitter, which will cause the signal frequency error between channels to increase under long-term operation.

[0078] The embodiments of this specification provide a multi-channel synchronous data acquisition method with an adjustable input voltage range. The method is implemented based on the multi-channel synchronous data acquisition device with an adjustable input voltage range in Example 1. The voltage gear processing unit 2 includes at least two gear control circuits 21 connected in series, namely a first-stage gain control circuit and a second-stage gain control circuit. The gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit are both greater than 1 times the gain, including:

[0079] When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential driver chip, and the relay 22 corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential driver chip;

[0080] When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay 22 corresponding to the second-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip;

[0081] When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and at the same time, the relay 22 corresponding to the second-stage gain control circuit is controlled to output the corresponding gain differential signal output by the differential drive chip.

[0082] The embodiments of this specification also provide another multi-channel synchronous data acquisition method with an adjustable input voltage range. The method is implemented based on the multi-channel synchronous data acquisition device with an adjustable input voltage range in Example 1. The voltage gear processing unit 2 includes at least three gear control circuits 21 connected in series, namely a first-stage gain control circuit, a second-stage gain control circuit, and a third-stage gain control circuit. The gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit are both greater than 1x gain, and the gear gain of the third-stage gain control circuit is 1x gain, including:

[0083] When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential driver chip, and the relay 22 corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential driver chip;

[0084] When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay 22 corresponding to the second-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip;

[0085] When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip, and the relay 22 corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip;

[0086] When the target gear gain of the target gain signal is 1x gain, the relay 22 corresponding to the first-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and at the same time, the relay 22 corresponding to the second-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and at the same time, the relay 22 corresponding to the third-stage gain control circuit is controlled to output the corresponding gain differential signal output by the differential drive chip.

[0087] In a specific embodiment, the two aforementioned multi-channel synchronous data acquisition methods with adjustable input voltage ranges both further include:

[0088] When an external clock source is input into the clock generator 11, the external clock source is used as a reference clock source of the clock generator 11;

[0089] When no external clock source is input to the clock generator 11 , the onboard clock source is used as a reference clock source of the clock generator 11 .

[0090] In a specific embodiment, the two aforementioned multi-channel synchronous data acquisition methods with adjustable input voltage ranges each further include:

[0091] Based on the preset cycle control synchronization signal input to the hardware synchronization port of the AD sampling processing unit 3,

[0092] The synchronous sampling clock signals of the multiple channels inputted by the AD sampling processing unit 3 are synchronously calibrated.

[0093] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

[0094] In the absence of conflict, the above embodiments and features in the embodiments can be combined with each other.

[0095] The above disclosure is only a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A multi-channel synchronous data acquisition device with adjustable input voltage range, characterized in that: The system comprises a clock selection unit (1), a voltage level processing unit (2) and an AD sampling processing unit (3), wherein the clock selection unit (1) and the voltage level processing unit (2) are both electrically connected to the AD sampling processing unit (3). A clock selection unit (1), configured to output a multi-channel synchronous sampling clock signal; A voltage gear processing unit (2), the voltage gear processing unit (2) is used to adjust the gear gain of an input voltage signal, the voltage gear processing unit (2) comprises two or more gear control circuits (21) connected in series, each of the plurality of gear control circuits (21) comprises a corresponding relay (22), the voltage gear processing unit (2) is used to control the corresponding gear control circuit (21) via the relay (22) to determine whether to output a gain signal to adjust the gear gain of the voltage gear processing unit (2) so as to output a target gain signal; An AD sampling processing unit (3) is used to sample the target gain signal inputted from the corresponding channel according to the synchronous sampling clock signal of the multi-channel; The gear control circuit (21) further includes a differential drive chip, which is used to process an input voltage signal inputted thereto to obtain a corresponding gain differential signal and input it into the corresponding relay (22); The relay (22) is a single-pole double-throw relay (22), and the single-pole double-throw relay (22) is configured such that when a switch inside the single-pole double-throw relay (22) contacts a first contact, the signal output end outputs the gain differential signal; and when the switch inside the single-pole double-throw relay (22) contacts a second contact, the signal output end outputs the corresponding input voltage signal of the differential drive chip.

2. The multi-channel synchronous data acquisition device with adjustable input voltage range according to claim 1, characterized in that: The clock selection unit (1) includes a clock generator (11), an onboard clock source, and an external clock source, wherein the clock generator (11) is configured to use the external clock source as a reference clock source of the clock generator (11) when the external clock source is inputted into the clock generator (11); When the external clock source is not input, the onboard clock source is used as the reference clock source of the clock generator (11).

3. The multi-channel synchronous data acquisition device with adjustable input voltage range according to claim 2, characterized in that: The external clock source comprises at least a first external clock source and a second external clock source, wherein the first external clock source is electrically connected to a first reference clock input terminal of the clock generator (11) via a first relay (22), and the second external clock source is electrically connected to a second reference clock input terminal of the clock generator (11) via a second relay (22), and the clock selection unit (1) is used to control one of the first relay (22) and the second relay (22) to be turned on via an FPGA to complete the switching of the external clock source.

4. The multi-channel synchronous data acquisition device with adjustable input voltage range according to claim 3, characterized in that: The FPGA is used to complete synchronization calibration of the multi-channel synchronous sampling clock signals input by the AD sampling processing unit (3) by inputting synchronization signals according to a preset period through the hardware synchronization port of the AD sampling processing unit (3).

5. A multi-channel synchronous data acquisition method with an adjustable input voltage range, the method being implemented based on the multi-channel synchronous data acquisition device with an adjustable input voltage range according to any one of claims 1 to 4, the voltage gear processing unit (2) comprising two gear control circuits (21) connected in series, namely a first-stage gain control circuit and a second-stage gain control circuit, the gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit both being greater than 1 times the gain, the gear control circuit (21) comprising a differential drive chip, the differential drive chip being used to process an input voltage signal inputted thereto to obtain a corresponding gain differential signal and input it to a corresponding relay (22), characterized in that: include: When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip; When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip; When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the corresponding gain differential signal output by the differential drive chip.

6. A multi-channel synchronous data acquisition method with an adjustable input voltage range, the method being implemented based on the multi-channel synchronous data acquisition device with an adjustable input voltage range according to any one of claims 1 to 4, the voltage gear processing unit (2) comprising three gear control circuits (21) connected in series, namely a first-stage gain control circuit, a second-stage gain control circuit and a third-stage gain control circuit, the gear gain of the first-stage gain control circuit and the gear gain of the second-stage gain control circuit both being greater than 1 times the gain, the gear gain of the third-stage gain control circuit being 1 times the gain, the gear control circuit (21) comprising a differential drive chip, the differential drive chip being used to process an input voltage signal input thereto to obtain a corresponding gain differential signal and input it to a corresponding relay (22), characterized in that: include: When the target gear gain of the target gain signal is the product of the gear gain corresponding to the first-stage gain control circuit and the gear gain corresponding to the second-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip; When the target gear gain of the target gain signal is the gear gain corresponding to the first-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the gain differential signal output by the corresponding differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the input voltage signal of the corresponding differential drive chip; When the target gear gain of the target gain signal is the gear gain corresponding to the second-stage gain control circuit, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the corresponding gain differential signal output by the differential drive chip; When the target gear gain of the target gain signal is 1 times the gain, the relay (22) corresponding to the first-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and the relay (22) corresponding to the second-stage gain control circuit is controlled to output the corresponding input voltage signal of the differential drive chip, and the relay (22) corresponding to the third-stage gain control circuit is controlled to output the corresponding gain differential signal output by the differential drive chip.

7. The multi-channel synchronous data acquisition method with adjustable input voltage range according to claim 5 or 6, wherein the clock selection unit (1) comprises a clock generator (11), an onboard clock source and an external clock source, and is characterized in that: Also includes: When an external clock source is input into the clock generator (11), the external clock source is used as a reference clock source of the clock generator (11); When no external clock source is input into the clock generator (11), the onboard clock source is used as a reference clock source of the clock generator (11).

8. The multi-channel synchronous data acquisition method with adjustable input voltage range according to claim 5 or 6, characterized in that: Also includes: Based on a preset period, the synchronization signal is input to the hardware synchronization port of the AD sampling processing unit (3), The synchronous sampling clock signals of the multiple channels inputted by the AD sampling processing unit (3) are synchronously calibrated.

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