Membrane-based microelectromechanical system (MEMS) devices constructed using back end of line (BEOL) metal layers of a solid state semiconductor process

Abstract

A MEMS device formed using BEOL materials with CMOS technology, wherein post-processing with vHF and a backing substrate is applied to form the MEMS device, and wherein the overall size of the MEMS device is between 50 μm and 150 μm. In other applications, the MEMS device can be implemented as an inertial sensor.

Description

Technical Field

[0001] This application relates generally to MEMS devices, and more specifically to techniques for manufacturing MEMS devices. Background Technology

[0002] An integrated circuit is a semiconductor device having a substrate of semiconductor material on which a series of layers are deposited using photolithography. These layers are doped and polarized to create electrical components (e.g., resistors, capacitors, or impedance devices) or electronic components (e.g., diodes or transistors). Subsequent deposition of other layers forms a structure of interconnected layers required for electrical connections.

[0003] Microelectromechanical systems (MEMS) are small electromechanical devices fabricated using layer deposition techniques based on photolithography. MEMS can have cavities or hollow spaces within them, which can be filled with liquids or gases. Traditional integrated circuits are completely solid devices, i.e., without any type of hollow portion. A hollow portion can be defined as a cavity larger than a hollow portion on an atomic or subatomic scale. Moving elements may exist within a MEMS. These moving elements can be connected at one end to the rest of the MEMS structure, or they can be completely loose (i.e., not physically attached to their surroundings) within a housing that is at least partially closed (to prevent loose parts from "escaping" from the MEMS). Chips can include MEMS devices and integrated circuits (ICs), where the ICs can control the MEMS.

[0004] The main problem with MEMS devices currently is the need for customized manufacturing processes. Solid-state electronic devices, on the other hand, do not present this issue, as they have converged on a manufacturing standard called Complementary Metal-Oxide-Semiconductor (CMOS), which has many variations, primarily categorized by their node size. This represents the smallest feature size that the process can address in the front-end process (FEOL).

[0005] In fact, most MEMS ICs currently on the market are contained within a package that has two dies. One of these dies comes from a CMOS wafer, while the other comes from a MEMS wafer manufactured using a custom process. The dies within the package are typically wire-bonded and encapsulated using a plastic package. For combined ICs requiring multiple MEMS devices, the package may contain more than two dies, one of which is a CMOS with control electronics, and multiple MEMS dies, each built using a different manufacturing process.

[0006] For every MEMS manufacturer and for every type of MEMS device, this proprietary manufacturing process presents several challenges: cost, size, time to market, performance, and mass production capabilities. Since 90% of the semiconductor industry consists of solid-state ICs—that is, no MEMS—and most of them are manufactured using CMOS processes, most semiconductor companies employ a so-called fabless model, outsourcing all production to large CMOS foundries whose business focuses solely on producing CMOS wafers.

[0007] This generates economies of scale typically 100 or higher globally compared to the largest MEMS foundries. This is why MEMS processes are more expensive than CMOS wafers. However, especially if we consider lower nodes, the cost of a MEMS wafer may be lower than that of a CMOS wafer due to the significantly increased complexity of the CMOS process compared to MEMS processes. But for the same level of complexity, CMOS will be far less expensive than any MEMS process. If MEMS could be manufactured using the same CMOS process, the overall cost of the IC would be significantly reduced. This is because we no longer need two dies within the package, but only one. Therefore, we eliminate the MEMS mold and simplify the packaging.

[0008] There is interest in reducing the size of ICs, especially for applications such as smartphones and even wearable devices, particularly earbuds, where space is very limited. Currently, the best packaging technology for minimizing the overall size of ICs is wafer-level chip-scale packaging (WLCSP). This essentially involves depositing an encapsulating layer on top of the wafer to protect it, forming bumps for the pads, and then dicing the wafer, with optional back-side grinding performed beforehand. Additional steps, such as RDLs (redistribution layers), can be added during this process, but they are not necessary or required in all implementations. However, WLCSP cannot be used if more than one mold is required for packaging. If MEMS can be built within the same CMOS mold, we will be able to apply WLCSP to package them, significantly reducing the overall package size and, if possible, enabling different types of MEMS devices to be implemented in the same CMOS process. Manufacturers can then fabricate combined chips packaged with WLCSP. This will result in a much larger shrinkage compared to the currently used multi-mold plastic packaging counterparts.

[0009] Developing new MEMS devices requires developing new manufacturing processes to build them. Because these processes must handle volumes typical of the consumer MEMS market—and are therefore very large—and high yields are desired to minimize costs, this is a complex project that typically takes several years and is costly. If the same existing, off-the-shelf CMOS process used for low-cost, high-volume production can be used to build the MEMS, then the time to market will be minimal, as only the device needs to be developed. There is no need to spend time (and cost) developing a custom manufacturing process.

[0010] Because CMOS and MEMS processes have different economies of scale, the equipment used in CMOS processes is state-of-the-art, while for MEMS processes, it is often conventional equipment to reduce the cost of setting up these MEMS processes. This means that the minimum feature size (also known as the critical size) of CMOS processes is generally smaller than that of MEMS processes. Therefore, if one can use CMOS manufacturing processes to build MEMS, they will be able to manufacture MEMS devices with smaller feature sizes. This will help improve device performance because softer springs / films and smaller gaps can be fabricated.

[0011] In addition, if MEMS can be fabricated using CMOS technology, parasitic capacitance is minimized when connecting the MEMS to the electronic interface (typically sensing / driving) circuitry within the CMOS die. This is typically achieved via wire bonding within a plastic package, which usually adds approximately 1 pF to 10 pF of capacitance. When the MEMS is integrated into the same CMOS process, the parasitic capacitance from the MEMS-electronic interface is typically reduced to 1 fF to 10 fF. This is a reduction of x100 to x1000. Since parasitic capacitance degrades the performance of a MEMS device (due to the capacitance that shields the MEMS), reducing parasitic capacitance improves the performance of the MEMS IC. Improved performance means increased sensor sensitivity, thereby reducing power consumption, or a combination of both.

[0012] Furthermore, as mentioned above, the mass production capacity of mainstream CMOS foundries is more than 100 times that of major MEMS foundries. Therefore, if we can utilize CMOS processes to build MEMS devices, we will benefit from this much larger production capacity. This will enable us to address new markets, such as IoT (Internet of Things), which would otherwise be impossible. Currently, MEMS suppliers struggle to serve the existing MEMS market due to their limited mass production capabilities. IoT promises to increase the current MEMS market size by 100 times or more. Currently, this can only be achieved by manufacturing MEMS devices using mainstream CMOS foundries.

[0013] Some companies use monolithic solutions to build MEMS together with CMOS. This leaves only a single die containing both CMOS and MEMS at the end of the manufacturing process. There are two ways to achieve this: one is to manufacture the MEMS and CMOS wafers separately and then combine them; the other is to build the MEMS wafer on the completed CMOS wafer instead of starting from a blank silicon wafer. In both cases, a customized MEMS manufacturing process is required. These monolithic solutions reduce the size of the IC because there is no need for wire bonding and WLCSP can be used. Furthermore, performance is also slightly improved due to the lower parasitic interconnect capacitance between the MEMS and CMOS, typically reduced to between 100 fF and 1 pF.

[0014] However, previous approaches still suffer from issues of cost, time-to-market, and mass production capabilities, as they still require fully custom MEMS processes. Furthermore, despite the reduced size and improved performance, the situation would be even better if we could build MEMS using CMOS processes. This is because, in terms of size, the profile is always larger, essentially meaning we would have two dies, one on top of the other. But with CMOS, it's a single mold that can be back-milled. In terms of performance, parasitic capacitance is reduced by x10 compared to traditional dual-die packaging solutions, but by x100 when building MEMS devices using CMOS processes.

[0015] Finally, these monolithic solutions only work when there is only one MEMS device or sensor. If we need a combined chip to combine different types of sensors, this will no longer be applicable. However, when building all these MEMS devices using CMOS processes, we have always had a single die solution that can be back-milled. Therefore, the cost and size advantages of building MEMS using CMOS processes increase significantly when we move towards combined chips.

[0016] The reduction in cost and size, especially as we move towards chip-on-chip integration, is partly due to the reduction of many no longer-needed bonding pads. If we can build MEMS devices using CMOS manufacturing processes for which numerous solutions have been proposed, we will reap known advantages. The initial solution was to modify the CMOS process, adding several steps to build the MEMS device. Depending on whether these steps are performed at the beginning, middle, or end of the CMOS process, the solution is referred to as preprocessing, internal processing, or post-processing.

[0017] Improvements to CMOS processes are necessary because MEMS devices require mechanical movement, necessitating empty spaces within the IC to perform this movement. These empty spaces cannot be created in CMOS. Another reason for improvement is the addition of layers made of different materials or with different mechanical properties not found in CMOS processes.

[0018] Given the enormous cost of implementing modern CMOS processes in mainstream foundries and the cost of maintaining their stability, improvements before and during the process were abandoned in order to maintain very high volume while also achieving very high yields. The only remaining option is CMOS post-processing to realize MEMS.

[0019] CMOS post-processing means that after the fabrication of the CMOS wafer is complete, it undergoes several additional manufacturing steps in which the MEMS is realized. However, unlike the monolithic approach explained earlier, this approach involves wafer bonding or building the MEMS on top of the CMOS wafer. In this case, we only need to create the empty space required to allow the mechanical movement of the MEMS. The MEMS is then constructed using the materials present within the CMOS wafer.

[0020] While one possible approach is to use polycrystalline silicon to realize MEMS, this requires deep etching, either starting from the top of the wafer, thus etching through all back-to-back (BEOL) processes first, or starting from the back side, requiring deep etching through the silicon substrate. This is a complex process and not cost-effective.

[0021] The only remaining solution is to use the existing materials in the BEOL of the CMOS to realize MEMS. Since the BEOL is the very top part of the CMOS mold, this will require minimal post-processing and therefore has the lowest cost.

[0022] To address this, various solutions have been proposed, such as combinations of plasma and / or wet etching with HF and other chemicals. These processes are difficult to mass-produce at high yields, especially when wet etching is involved.

[0023] Previously proposed simple post-processing methods include a maskless post-processing step using a single vapor HF (vHF) etching process. vHF etches away the silicon oxide present between the metal layers of the BEOL, leaving all the metal. This was proposed by Baolab. Due to its simplicity, it is the lowest-cost CMOS post-processing method. Furthermore, it can be implemented in the same CMOS foundry or packaging or assembly workshop.

[0024] In this approach, metal layers (typically Al or AlCu and W) are used to construct the MEMS device, but other metal layers (such as Cu) can also be used. With proper design, oxides can be trapped within the metal casing. Other materials can be used, but they must be present within the CMOS BEOL. Most previous methods used special packaging (such as stacked packages), such as LGAs, to protect the MEMS. This increases cost and size, thus minimizing or eliminating the size and cost advantages that would otherwise be achieved using CMOS processes to construct the MEMS.

[0025] Baolab proposes using a top metal layer to protect the MEMS while employing small apertures to allow vHF to enter the MEMS cavity. A second set of post-processing steps, including aluminum sputtering and patterning, will then be applied to properly seal the MEMS device. This typically increases the cost of the CMOS process by 10%. This simplifies packaging requirements and eliminates the need for stacked layers or other special packaging. Instead, any standard packaging technology, such as QFN or others, can be used. This reduces the cost and size of the final IC.

[0026] In addition to the top metal layer, the bottom metal layer completes the metal cavity housing the MEMS device. This is done to limit vHF etching to the bottom, since most CMOS processes do have doped silicon oxide below M1, which is the bottommost metal layer. Doped silicon oxide reacts very violently to vHF, rapidly increasing the etching rate and leaving very nasty residues that are difficult to remove. This makes the design portable to most CMOS processes, whereas otherwise it would only be suitable for special processes where there is no doped silicon oxide below the bottommost metal layer of BEOL.

[0027] Similar to other solutions using materials from BEOL to realize MEMS devices, Baolab's solution uses metal walls to surround the MEMS device, defining the MEMS cavity within the ASIC die. In this way, the electronics are placed around it. These metal walls are stacked from metal layers (typically made of aluminum) and vias (typically made of tungsten). However, if we are using smaller CMOS nodes with processes below 0.18μm, the material may differ, primarily copper. In principle, these are not straight, vertical walls because DRC rules require the metal layers to extend beyond the edges of the vias. However, some exceptions can be made if we intend to increase the lateral area exposed on the walls, such as in the case of planar capacitive sensors. This would be the DRV that the foundry must accept.

[0028] Using Baolab's solution, vertical metal walls would theoretically connect the top and bottom metal planes, thus electrically short-circuiting all MEMS cavities. This is typically not something we'd be interested in, or at least not something that would occur arbitrarily in all cavities. To address this, Baolab used vertically staggered anchoring structures. These structures force the vHF to move up and down the silicon oxide layer until it's exhausted, leaving some unetched silicon oxide. In this way, we achieve mechanically consistent walls without electrically short-circuiting the top and bottom metal plates.

[0029] One reason this is particularly effective is that the silicon oxide layer, typically deposited between the metal layers of a BEOL in CMOS processes, exists on two distinct sublayers, each with a different oxide density. Consequently, the vHF etch rate of one of these layers is slower than the other. In this way, etching silicon oxide vertically with vHF is more difficult (i.e., takes longer) than horizontally because the etching propagates faster along one of the silicon oxide sublayers. Using these anchoring structures, we force vHF to etch through all the slower-etching-rate sublayers, preventing it from propagating rapidly through the faster-etching-rate sublayers. These staggered anchors can also be used to add pillars or struts at different locations on the MEMS to provide greater uniformity to the top metal plane. This is especially important given that aluminum sputtering is typically used to support the subsequent seal, preventing the top metal plane from bending, which could otherwise damage or render the MEMS device unusable.

[0030] The main problem with these anchored walls is that, despite providing mechanical strength and electrically disconnecting the top and bottom metal planes, the capacitance between them is very large. This is because of the large surfaces placed close to each other within the staggered anchoring structure, one connected to the top plate and the other to the bottom plate, and even worse, largely filled with silica.

[0031] Another issue related to the previous one is the critical trade-off between parasitic capacitance between the top and bottom metal plates and production yield and reliability. To minimize this parasitic capacitance, we could minimize the length of the anchoring structure, reduce the number and / or height of the fingers, and / or potentially increase the etching time. In this way, if we want to minimize parasitic capacitance, we would have a small anchoring structure with minimal residual silicon oxide after vHF etching. However, this would be a very fragile structure, susceptible to mechanical failure from shocks, vibrations, or simply sealing or encapsulating the device. This would also lead to low yields. Even slight over-etching would completely remove the silicon oxide inside the anchoring structure, causing collapse of the top and bottom components, rendering the device completely unusable. In production, we need to avoid this requirement for critical vHF etching, as it always results in low yields. The reason is that the etching rate and the amount of silicon oxide etched within the MEMS cavity depend not only on the vHF machine and the applied formulation but also on the CMOS process. While we can have tight control over the vHF machine and its formulation, we cannot control the CMOS process, whose tolerances are typically around 30%.

[0032] Besides the potential need for all metal layers to realize a MEMS device, thus requiring specialized packaging processes, specific CMOS processes for undoped silicon oxide beneath the bottom metal plate, and significant parasitic capacitance, the two main challenges of using materials in a CMOS BEOL to realize MEMS solutions are yield and reliability. These issues become even more critical when using the Baolab approach with top and bottom metal planes. However, if we don't use this approach, the process becomes more complex and expensive, thus losing its cost advantage, as well as its advantages in mass production, time to market, and even performance.

[0033] A major problem encountered when using BEOL metal in CMOS processes to implement MEMS devices is the vertical stress gradient. This is minimized in custom MEMS fabrication processes. However, in CMOS, because these metal lines (where no mechanical structure is intended but only electrical connections) are surrounded by silicon oxide in a solid-state IC, residual stress is less of a concern and often results in larger values. In addition to large residual stress, we typically find large vertical stress gradients. This causes the metal to bend or curl, usually upwards, but depending on the layer, it can also be downwards, especially on the top layer. This bending is a significant problem when we use top and bottom metal planes. Because the available vertical clearance space above and below the device is minimal, the device can easily come into contact with these top and bottom metal planes. When a MEMS device comes into contact with a top or bottom metal plane, it becomes unusable. This results in very poor yield and reliability.

[0034] One possible solution to slightly alleviate this problem is to increase the vertical gap distance and reduce the number of metal layers used for the MEMS device itself. However, this would reduce performance in the out-of-plane direction because the gap would be larger, and therefore the relative capacitance change of a given sensor would be smaller for the same displacement. Similarly, in the case of inertial sensors, we would be forced to use a smaller sensing mass, and not be able to use all available metal layers, thus further reducing performance. Furthermore, reducing the number of metal layers used to construct the movable parts of the device (as in the case of the sensing mass in inertial sensors) would further increase its curvature, as described below, thus requiring minimization of the curvature height of the MEMS device. This is defined as the maximum vertical displacement in the out-of-plane direction of any metal layer along the entire MEMS device or any specific element thereof.

[0035] One known solution to this problem is to stack two or more metal layers. In this way, we can increase the radius of curvature of the resulting metal structure, thereby reducing the overall height of curvature. However, while this is a good solution for designing certain components of MEMS devices, such as the sensing mass of an inertial sensor, which we want to make as large as possible to improve sensor sensitivity, for other components like springs, this results in very high stiffness, which significantly reduces sensitivity. In fact, stiffness is inversely proportional to the cube of length and thickness, so increasing the thickness quickly leads to very stiff springs. This means that the sensor sensitivity is very low, while the actuator's drive voltage is high. Furthermore, the stacking of many layers is limited by the number of metal layers in the process, and this rapidly increases its cost if modifications or the use of CMOS processes with a large number of metal layers in BEOL are required.

[0036] In summary, it is necessary to find the right design to realize MEMS devices by reusing the BEOL material present in standard CMOS processes, removing some of the silicon oxide inside the MEMS cavity using vHF etching, and then packaging it with WLCSP. These devices have very high yield, reliability and performance.

[0037] Another problem with using a vHF etch post-processing step after CMOS is that the SiN passivation deposited and patterned on top of the CMOS wafer is partially etched away by the vHF etch. This means that in practice, unless a very short vHF etch step is performed, most or all of the SiN passivation will be etched away. This will leave a very difficult-to-remove residue in the wafer, and this residue will expose all wafers with ASIC regions that should not have their silicon oxide etched away.

[0038] The known solution to prevent this is to increase the silicon content of the passivation layer, typically measured by the layer's refractive index or RI. While technically not complex, this requires process tweaking, which is very challenging for large mainstream foundries to implement. Ultimately, this requirement means we will no longer be able to use fully standard CMOS processes, thus losing some of the advantages of low cost, short time-to-market, and high-volume production capabilities. Summary of the Invention

[0039] In various implementations, this application addresses the deficiencies associated with the manufacture of MEMS devices.

[0040] In various aspects, the systems, devices, and methods are generated by or use vHF etching to etch away a portion of the silicon oxide in the BEOL of a CMOS process, thereby releasing the material present in the BEOL constituting the MEMS device. The method of the present invention uses a bottom metal plane and a top metal plane, the top metal plane having an array of small holes to allow vHF to enter the MEMS cavity. A key inventive concept is to limit the overall MEMS size in the layout to between 50 μm and 150 μm, preferably less than 100 μm. For a given radius of curvature of a MEMS device or element, the total curvature height depends on the horizontal dimension. Therefore, if the device is small enough, the curvature height will be limited despite a large vertical stress gradient.

[0041] The second inventive concept is the design of the spring. For such small devices to perform well, small, soft springs are needed while maintaining a low curvature height. These seem like contradictory requirements. Short springs mean they will be very stiff, thus reducing the sensitivity (performance) of the MEMS sensor. To have soft springs, we need to minimize their thickness, which means minimizing metal stacking or not using short springs at all. But this increases the vertical stress gradient, thus rapidly increasing the overall curvature height.

[0042] A preferred inventive solution to the spring design problem is to use a set of at least three springs instead of one, which are evenly distributed around the device and rotate about the central axis of the device, so that the MEMS device will not tilt due to symmetry after being released by vHF etching.

[0043] In the case of inertial sensors, MEMS devices may include a central sensing mass made of multiple stacked metals, such that the central sensing mass is very flat compared to the springs surrounding it. For sufficient sensitivity, the sensing mass can also be larger than the springs. If one or more springs of the sensing mass are kept bent, then if the sensing mass is tilted, it will ultimately have a large curvature height, even though the sensing mass itself is relatively flat. However, if the springs are evenly distributed around it and there are at least three springs, then the sensing mass will experience a smaller vertical displacement due to the curvature of the springs, and it will be flat, thus not affecting the total vertical height through its larger size.

[0044] In some implementations, the central mass will have a circular shape, and the spring surrounding it will have a helical shape, and the spring will be made of only one metal layer or a stack of only two metal layers. In the case of using a stack of two metal layers, the two metal layers will be connected by a via layer in the middle. In a preferred embodiment, the via layer will have the same linear or helical shape as the upper and lower metal layers, but in principle it will be slightly narrowed laterally to satisfy the DRC rule at least in one horizontal direction at each point. Throughout the application, when we say we use a stack of a particular set of metal layers, it should be understood that we will use via layers between the metal layers to keep them connected. Using circular and rounded shapes for the sensing mass, springs, and generally all or as many components of a MEMS device avoids high mechanical stresses that would otherwise accumulate at the right angles of the device geometry. These rounded shapes help balance the spring stresses, and when we use at least three springs evenly distributed around the central mass, this results in a horizontal tilt that is necessary for the central mass.

[0045] One aspect includes a MEMS device formed using BEOL materials from a CMOS process, wherein post-processing with vHF and a backing is applied to form the MEMS device, and the overall size of the MEMS device is between 50 μm and 150 μm. The overall size of the MEMS device can be less than 100 μm. In some embodiments, the overall size of the MEMS device is less than or equal to 50 μm. The MEMS device may include a set of at least three springs uniformly distributed around the MEMS device and rotating about the central axis of the MEMS device or its movable part. The device shape may be rounded, and the springs may have a helical shape. The springs may be made of a single metal layer or a stack of at least two metal layers. The MEMS device may include an inertial sensor.

[0046] MEMS devices may include a detection mass element. The detection mass element may be formed or fabricated from a stack of four metal layers and a spring, wherein the spring is either connected to the top metal layer of the stack forming the detection mass element, or to two top metal layers of the stack. The spring may be connected to an outer ring such that, after vHF etching, a portion of it remains buried in silicon oxide on its outer edge.

[0047] In some embodiments, the MEMS device has a top metal plane and a bottom metal plane smaller than the top metal plane. The outer ring width of the bottom metal plane can be less than or equal to 10% to 50% of the width of the outer ring of the top metal plane. The outer ring width of the bottom metal plane can be approximately 30% of the width of the outer ring of the top metal plane. The MEMS device may include at least one pad, wherein the at least one pad includes a top metal layer arranged to extend laterally by 15 μm to 25 μm in all directions beyond the vertically aligned passivation opening. The at least one pad may extend laterally by 20 μm in all directions beyond the vertically aligned passivation opening. The MEMS device may be formed within a MEMS cavity that does not include a metal-filled structure. In some embodiments, the MEMS device is arranged to have more capacitance, for example, to enable the use of more conventional sensing circuitry to measure MEMS capacitance. The MEMS device may consist of an array of MEMS devices electrically connected in parallel. Each of these MEMS devices has its own passivation opening and will be completely disconnected except for the lines / tracks forming the electrical connections.

[0048] On the other hand, the MEMS device includes a set of at least three springs, which are evenly distributed around the MEMS device and rotate about the central axis of the MEMS device. The device shape can be rounded, and the springs can be helical. The springs can be made of a single metal layer or a stack of at least two metal layers. The MEMS device may include an inertial sensor. The MEMS device may include a sensing mass, wherein the sensing mass is made of a stack of four metal layers and springs, and wherein the springs are connected either to the top metal layer of the stack forming the sensing mass or to two top metal layers of the stack.

[0049] On the other hand, the MEMS device includes a spring, wherein the ratio of the maximum displacement to the spring length is at least 1%. The MEMS device may include a sensing mass, wherein the sensing mass is made of a spring and a stack of four metal layers, and wherein the spring is connected either to the top metal layer forming the stack of the sensing mass, or to two top metal layers of the stack. The spring may be connected to an outer ring such that, after vHF etching, a portion of it remains buried in silicon oxide on its outer edge. The MEMS device may include a top metal plane and a bottom metal plane, wherein the width of the outer ring of the bottom metal plane is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane.

[0050] On the other hand, there is a method for fabricating MEMS devices using BEOL material in CMOS processes. This method includes: applying vHF and a backing material in a post-processing step to form the MEMS device, wherein the total size of the MEMS device is between 50 μm and 150 μm. The total size of the MEMS device can be less than 100 μm. The method may also include forming a set of at least three springs that are uniformly distributed around the MEMS device and rotate around the central axis of the MEMS device.

[0051] This method may include forming a rounded device shape and forming a spring with a helical shape. This method may include forming a spring having a single metal layer or a stack of at least two metal layers. This method may form a MEMS device including an inertial sensor.

[0052] The method may include forming a detection mass element, wherein the detection mass element is made of a stack of springs and four metal layers, and wherein the springs are connected either to the top metal layer of the stacked detection mass element or to two top metal layers of the stack. The method may include connecting the springs to an outer ring such that, after vHF etching, a portion of the spring remains buried in silicon oxide on its outer edge.

[0053] The method may include forming a MEMS device having a top metal plane and a bottom metal plane, the bottom metal plane being smaller than the top metal plane. The method may include forming an outer ring width of the bottom metal plane, the outer ring width of the bottom metal plane being less than or equal to 10% to 50% of the width of the outer ring of the top metal plane. The method may include forming the outer ring width of the bottom metal plane to be approximately 30% of the width of the outer ring of the top metal plane. The method may include forming a MEMS device within a MEMS cavity that does not include metal-filled structures.

[0054] In another aspect, a method for manufacturing a MEMS device includes forming a set of at least three springs, the springs being uniformly distributed around the MEMS device or a movable part thereof, and rotating about a central axis of the MEMS device or a movable part thereof. The method may include forming a rounded MEMS device shape and forming springs with a helical shape. The method may include forming springs having a single metal layer or a stack of at least two metal layers. The method may include forming a MEMS device including an inertial sensor. The method may include forming a detection mass, wherein the detection mass is made of a stack of springs and four metal layers, and wherein the springs are connected either to the top metal layer of the stacked detection mass or to two top metal layers of the stack.

[0055] In another aspect, a method for manufacturing a MEMS device includes forming a spring, wherein the ratio of the maximum displacement to the spring length is at least 1%. The method may include forming a sensing mass having a spring and four metal layers stacked together, wherein the spring is connected either to a top metal layer of the stacked sensing mass or to two top metal layers of the stack. The method may include attaching the spring to an outer ring such that, after vHF etching, a portion of it remains buried in silicon oxide on its outer edge. The method may include forming an outer ring width of the bottom metal plane that is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane.

[0056] On the other hand, smartphones, wearable devices, earphones, or Internet of Things (IoT) devices include MEMS devices according to the foregoing aspects.

[0057] All inventive concepts described in this section and throughout this application, while applicable in principle to CMOS, may also be applied to BEOLs of any other solid-state semiconductor process, such as BiCMOS, GaAs, SiGe, GaN, SOI, etc.

[0058] Any two or more features described in this specification (including this summary section) may be combined to form an implementation not specifically described in this specification.

[0059] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will become apparent from the specification, the drawings, and the claims. Attached Figure Description

[0060] Figure 1 A detection mass component of a MEMS device is shown, which has three springs connected to its periphery and evenly spaced around its periphery;

[0061] Figure 2This is an exploded view of the metal and via layers of a MEMS device, where SiO2, passivation, and substrate are not shown.

[0062] Figure 3 yes Figure 2 An enlarged view of the M4 layer of a MEMS device;

[0063] Figure 4 yes Figure 2 An enlarged view of the M5 layer of a MEMS device;

[0064] Figure 5 yes Figure 2 An enlarged view of the V4 layer of the MEMS device;

[0065] Figure 6 yes Figure 2 A three-dimensional view of a MEMS device;

[0066] Figure 7 It shows Figure 2 A side view of the metal layer of a MEMS device;

[0067] Figure 8 yes Figure 2 , Figure 6 and Figure 7 A cross-sectional schematic diagram of a MEMS device; and

[0068] Figure 9 This is an exploded view of the metal and via layers of a MEMS device, including the side electrodes.

[0069] The same reference numerals in different figures denote the same elements. Detailed Implementation

[0070] This application addresses, in various respects, defects related to the fabrication and / or structure of MEMS devices.

[0071] In various aspects, the systems, devices, and methods are generated by or use vHF etching to etch away a portion of the silicon oxide in the BEOL of a CMOS process, thereby releasing the material present in the BEOL that will constitute the MEMS device. The method of the present invention uses a bottom metal plane and a top metal plane with an array of pinholes to allow vHF to enter the MEMS cavity. A key inventive concept is to limit the overall MEMS size in the layout to between 50 μm and 150 μm, preferably less than 100 μm. For a given radius of curvature of a MEMS device or element, the total curvature height depends on the horizontal dimension. Therefore, if the device is small enough, the curvature height will be limited despite a large vertical stress gradient.

[0072] The second inventive concept is the design of the spring. For such small devices to perform well, a small, soft spring is needed while maintaining a low curvature height. These seem like contradictory requirements. A short spring means it will be very stiff, thus reducing the sensitivity (performance) of the MEMS sensor. To have a soft spring, we need to minimize its thickness, which means minimizing metal stacking or not using a short spring at all. But this increases the vertical stress gradient, thus rapidly increasing the overall curvature height.

[0073] The preferred inventive solution to the spring design problem is to use a set of at least three springs instead of one, evenly distributed around the device and rotating about the central axis of the device, so that the MEMS device will not tilt after being released by vHF etching through symmetry.

[0074] In the case of inertial sensors, MEMS devices include a central sensing mass composed of multiple stacked metals, which is therefore very flat compared to the springs surrounding it. For sufficient sensitivity, the sensing mass can also be larger than the springs. If one or more springs around the sensing mass are kept bent, then if the sensing mass is tilted, the springs will ultimately have a large curvature height, even though the sensing mass itself is relatively flat. However, if the springs are evenly distributed around it and there are at least three springs, then the sensing mass will experience a smaller vertical displacement due to the curvature of the springs, and the sensing mass will be flat, thus not affecting the total vertical height through its larger size.

[0075] Figure 1 A central mass and / or sensing mass 100 of a MEMS device is shown, having three springs 102, 104, and 106 fabricated and / or attached to the periphery of the sensing mass and uniformly distributed around it. The sensing mass 100 also includes an array of etched holes 108. In some embodiments, the central mass 100 will have a circular shape, and the springs 102, 104, and 106 surrounding the central mass will have a helical shape and be made of only one metal layer, or a stack of only two metal layers, or a stack of more than two layers. The use of circular and rounded shapes for the sensing mass 100, the springs 102, 104, and 106, and generally for all or as many components of a MEMS device as possible, avoids high mechanical stresses that would otherwise accumulate at the right angles of the device geometry. These circular shapes help balance the stress on springs 102, 104, and 106. When we use at least three springs 102, 104, and 106 evenly distributed around the central mass 100, this results in a horizontal inclination, which is what we need for the central mass.

[0076] While the number of springs can be increased, allowing us to use four or more springs, and this would further help to achieve the horizontal tilt of the center detection mass 100, some implementations only have three springs because otherwise the overall stiffness of the MEMS device would increase proportionally with the number of springs, thereby reducing its sensitivity.

[0077] In this application, we will use the term "inertial sensor" to refer to various devices that sense acceleration. This can include at least accelerometers, motion detectors, and bone conduction sensors. They operate on the same physical principles, but differ in the frequency of their detection. Similarly, their bandwidth and whether they need to sense direct current (DC), as well as their resolution and / or sensitivity requirements, also vary.

[0078] Another implementation can use pairs of straight springs located on opposite sides of the sensing mass 100, such that each pair of springs is aligned on the same straight line. This solution is feasible because the residual stress in the metal lines is found to be tensile in most CMOS processes, with the exception of the topmost metal layer. Therefore, the curvature height is minimized. However, this solution results in relatively high stiffness, which is also highly dependent on the device temperature. Therefore, this is a solution applicable to some MEMS devices, especially when high mechanical resonant frequencies are required, and when the temperature dependence of spring stiffness is no longer significant.

[0079] If the MEMS device attached to the center portion of the spring or the sensing mass (e.g., in the case of an inertial sensor) is thicker than the spring and therefore made of a stack of larger metal layers, then a preferred embodiment of the spring is made using the upper metal layer if we connect the sensing mass or the center portion of the MEMS to the top metal plane. This minimizes the parasitic capacitance of the spring and the supporting outer ring toward the lower metal plate.

[0080] Figure 2 This is an exploded view of the metal and via layers of the MEMS device 200, where SiO2, passivation, and substrate are not shown. Figure 2 An out-of-plane inertial sensor is described. This out-of-plane inertial sensor is fabricated using a 6-metal BEOL CMOS process. The metal layers are numbered M1 (bottom) to M6 (top). There are a total of 5 via layers, numbered V1 (between M1 and M2) to V5 (between M5 and M6), but V1 is not used in this particular design. The sense mass has a circular structure with three helical springs evenly placed around it, and the diameter of the sense mass plus the springs is 50 μm. The sense mass is made by stacking metal layers M2 to M5, while the springs are stacked on metal layers M4 and M5. The sense mass has concentric rings that stop at etched holes that vertically pass through it, and the sense mass is made of via layers V2 to V4.

[0081] The top metal plane has the same diameter, plus a 20μm wide outer ring around that diameter, which corresponds to a circle with a diameter of 90μm. In the X and Y directions, there is an array of 0.8μm holes spaced approximately 5μm apart between the centers of every two holes. The spring has a 20μm wide surrounding ring, constructed on the same M4 and M5 layers. An array of concentric through-holes connects these rings to the top metal plane on these rings. That is, they are implemented at the V4 and V5 layers.

[0082] There is a circular bottom metal plane made of M1, with a diameter of 50 μm, plus a 6 μm wide outer ring, which is smaller than the outer ring of the top layer used for the top metal plane and the spring support. The inner and outer rings together constitute a circle with a diameter of 62 μm. The difference between the inner and outer rings is that after vHF etching, the outer ring is partially etched, and its edges remain buried (and affected) by silicon oxide. The top passivation opens in a 50 μm circular shape and is located above the MEMS device.

[0083] MEMS device 200 includes an M6 layer 202, a V5 layer 204, an M5 layer 206, a V4 layer 208, an M4 layer 210, a V3 layer 212, an M3 layer 214, a V2 layer 216, an M2 layer 218, and an M1 layer 220. M6 layer 202 includes a top plate 222 having etched holes arranged in an array and a connection to an ASIC. V5 layer 204 includes an array of concentric through-hole rings 224 extending on an outer metal surface. M5 layer 206 includes a top cover 226 of a detection mass element having an array of etched holes. Layer 206 also includes a portion of a helical spring 228 and an outer metal ring 230. V4 layer 208 includes an array 232 of concentric through-hole rings extending on an outer metal surface, a portion of a helical spring 228 extending in V4 layer 208, and an array 236 of concentric through-hole rings extending on the detection mass element and stopping at the etched hole locations, while surrounding the hole locations with square rings. M4 layer 210 includes a detection mass plane 238 with an etched hole array, a portion of a helical spring 228, and a portion of an outer metal ring 230. V3 layer 212 includes an array of concentric through-hole rings 244 that extend on the detection mass and stop at the etched hole locations, while surrounding the hole locations with square rings. M3 layer 214 includes a detection mass metal plane 246 with an etched hole array. V2 layer 216 includes an array of concentric through-hole rings 248 that extend on the detection mass, stop at the etched hole locations, and surround the etched hole locations with square rings. M2 layer 218 includes a detection mass metal bottom cover 250 containing an etched hole array. M1 layer 220 includes a bottom metal plane 252 that includes a connection portion for the ASIC.

[0084] A preferred embodiment of the accelerometer using a six-layer metal process is as follows, wherein layer M1 220 is the bottom layer and layer M6 202 is the top layer. Layer M1 220 will be implemented as the bottom plane, and layer M6 202 will be implemented as the top metal plane, which will be shorted to the sensing mass and the spring. The sensing mass will be implemented using a stack of layers M2 218 to M5 206. And the spring 228 will be implemented using only layer M5 206 or a stack of layers M4 210 and M5 206.

[0085] If we set the total diameter of the detection mass plus the spring, there is an optimal value for the maximum angle of rotation or length of the spring. A longer spring (larger total angle) means a softer spring, but a smaller detection mass. A shorter spring allows for a larger detection mass, but the spring will be stiffer. Therefore, there is always an optimal value, depending on the specific design and manufacturing characteristics. However, generally speaking, it is difficult to manufacture reliable devices and good yields using springs with angles exceeding 360°. That is, preferably, each individual spring will not rotate one revolution around the circular detection mass.

[0086] Another parameter affecting design yield, performance, and reliability is the spacing around the spring. That is, in the absence of any other components such as springs, sensing mass elements, anchors, or devices (except for the edges of the spring, as they are fused to the outer ring or anchor / wall and sensing mass element or other MEMS components at their beginning and end), there must be a horizontal spacing or gap at each point of the spring. This obviously needs to be at least equal to the minimum spacing set by the Process Design Rule Check (DRC). However, in practice, we set it to a higher value, between x2 and x10 of this minimum spacing set by the process's DRC. A preferred value is x5. For example, in the case of a 180nm process with a minimum gap DRC of 300nm between metals, we preferably set the horizontal spacing of the springs to 1.5μm. The trade-off here is that for very large spacings, we will reduce sensitivity and / or performance because we will reduce the sensing mass area more and therefore the mass of the same spring length (thus achieving a given softness / stiffness of the spring). However, reducing the horizontal spacing between springs results in poorer yield and reliability.

[0087] Compared to displacement (vertical position, so out of plane; horizontal displacement, so in-plane), another crucial aspect of the spring (especially important when the spring is flexible) is making it short enough, such as when we use a set of three or more helical springs evenly distributed around a central sensing mass. Because we have a small sensing mass and need very flexible springs to achieve sufficient sensitivity, this will, in principle, be prone to static friction problems, which will lead to very poor reliability of these MEMS devices.

[0088] Figure 3 yes Figure 2 An enlarged view 300 of the M4 layer 210 of the MEMS device. The M4 layer 210 includes a 50 μm circular metal plane 302 inside the sensing mass, a helical spring 306, a 20 μm wide outer ring 304 that is partially buried in silicon oxide after vHF etching to support the spring and thus support the sensing mass, and an array 308 of etched holes through the sensing mass.

[0089] Figure 4 yes Figure 2 An enlarged view 400 of the M5 layer 206 of the MEMS device. The M5 layer 400 includes a top cover 402 of a sensing mass element with an array of etched holes, a helical spring 404, and an outer metal ring 406.

[0090] Figure 5 yes Figure 2 An enlarged view 500 of the V4 layer 208 of the MEMS device. The V4 layer 500 includes an array 502 of concentric via rings extending on the detection mass element, which stops at each etched hole 504 location and surrounds each hole 504 in a square ring.

[0091] Layer 500 also includes an array 508 of concentric through-hole rings extending on the outer metal.

[0092] Figure 6 This is a non-decomposed 3D view 600 of a metal layer (therefore the remaining silicon oxide, passivation, and substrate are not shown), such as M6 layer 202 including... Figure 2 The etched holes of the MEMS device. Layer 202 includes an array of etched holes 602, an outer ring 604, and a connection portion 606 to the ASIC (upper electrode and sensing mass device). Layer M1 220 includes a connection portion 608 to the lower electrode of the ASIC.

[0093] Figure 7 It shows Figure 2A side view 700 of the metal layers M1-M6 and via layers V2-V5 (since V1 is empty) of the MEMS device includes a connection 702 with the ASIC (upper electrode and detection mass), a top metal plane 704, an outer ring 706, a detection mass 708, a bottom metal plane 710, and a connection 712 with the lower electrode of the ASIC.

[0094] Figure 8 yes Figure 2 , Figure 6 and Figure 7 Figure 800 shows a cross-sectional schematic diagram of a MEMS device. Figure 800 shows a passivation section 802, a passivation opening 804, a spring 806, an etched hole array 808, an outer metal ring 810, an M6 layer 812, a V5 layer 814, an M5 layer 816, a V4 layer 818, an M4 layer 820, a SiO2 deposition 822, an M1 layer 824, a V3 layer 826, an M3 layer 828, a V2 layer 830, an M2 layer 832, a bottom metal plane 834, a detection mass 836, an array 838 of concentric through-hole rings inside the detection mass 836, and an array 840 of concentric through-hole rings along the outer metal ring 810.

[0095] MEMS devices are designed to operate in linear regions. This is because the device has a relatively large size, and although it has a certain thickness, the large spring makes it flexible enough to allow for maximum displacement, covering all the very small gaps above, below, in front, or on the sides. In this way, the MEMS spring follows Hooke's Law, having constant stiffness, i.e., producing a mechanical restoring force proportional to the displacement.

[0096] In some cases, assuming the displacement is large compared to the spring length, the mechanical restoring force initially becomes proportional to the displacement. However, after a given initial displacement, this restoring force is no longer linear and increases much more rapidly. In this way, although the spring is flexible for small displacements around the equilibrium point (where the sensor operates with very good sensitivity), the restoring force will be much larger at that point when the detected mass undergoes a large displacement, such as if subjected to impact or strong vibration, contacting surrounding walls, top plates, or bottom plates. Thus, due to the increased restoring force at the contact point, the MEMS device returns to its equilibrium position and overcomes static friction.

[0097] Looking at this phenomenon in more detail, all springs are nonlinear. However, while other MEMS devices experience only small displacements, the device described in this paper can experience large displacements, causing it to enter a nonlinear region of mechanical restoring force versus displacement before contacting surrounding walls, top plates, or bottom plates.

[0098] We can calculate the length of a spring in two ways. One is the straight-line distance from one end to the other. The second method is the entire distance along all the lengths of the spring (along its curvature and curves). We will take the longest of these measurements as the “length” of the spring. In the embodiments described herein, the shortest ratio between the minimum displacement that causes the spring to contact the surrounding walls, top plate, or bottom plate and the length of any spring is at least 1%, while in some designs this ratio can be 5% or even 10%. This principle also applies to lower ratios, but robustness may be insufficient. However, 0.5% or even 0.1% may provide sufficient results, depending on the specific process and overall implementation. This short ratio is a factor in the MEMS device described herein that has not been found in other MEMS designs, allowing for the implementation of soft springs and short gaps to achieve high-performance devices that can be packaged using all packaging technologies, including WLCSP, while maintaining high throughput and reliability.

[0099] Another inventive concept involves the design of vertical walls, or more precisely, the definition of MEMS regions, or the limitation of lateral etching of silicon oxide, as well as the mechanical anchoring or support of the MEMS. As previously mentioned, other designs utilize vertical metal walls or anchors.

[0100] In the first scenario, using vertical metal walls, we cannot seal the device from the top and / or bottom using top and / or bottom metal layers. This means we would need a special CMOS process with undoped silicon beneath the lowest metal layer of the BEOL, and / or a special, more expensive packaging technique, such as a stacked substrate, to properly protect the MEMS cavity from the top, and typically also require more expensive post-processing etching steps. This could be completely or partially avoided if the MEMS device were allowed to electrically short-circuit the top and bottom metal planes to the surrounding walls, which is generally not possible.

[0101] The second option is to use anchors, which, while electrically disconnecting the top and bottom metal layers, create a large parasitic capacitance between them, thus degrading device performance. Furthermore, any attempt to improve performance or reduce this parasitic capacitance by reducing the anchor structure or increasing the vHF etching time will decrease device yield and reliability.

[0102] The devices of this invention have neither a vertical metal wall connecting the top and bottom metal planes nor capacitive anchors. Instead, these devices employ two different solutions. One solution is to extend the component of the MEMS device located between the top and bottom metal planes or electrodes, such as a spring, but also other electrodes, such that it is ultimately buried in silicon oxide, sufficiently spaced horizontally so that vHF cannot reach it. In practice, we have seen that a long distance is not necessary. For a 180nm CMOS node, a 20μm band of metal around the MEMS device is sufficient. Thus, metal is placed around the released MEMS device, which holds the MEMS device in place because the outer edge of the MEMS device has unetched silicon oxide around and / or nearby. Preferably, the surrounding metal has a circular shape at its outer edge, but other shapes are also possible.

[0103] In the above solution, we have at least three electrically disconnected components: the top metal plane, the bottom metal plane, and the component of the MEMS device between them. More components can be electrically disconnected. An alternative implementation can be applied where, instead of having three or more electrically disconnected components, there are only two. In this case, a portion of the MEMS device can be attached to one of the top and bottom metal planes via a vertical metal wall, but not to the other. In some implementations, the MEMS device is attached to the top metal plane. This is because the top metal layer is typically less flat and more curved than the bottom metal layer. This is because the bottom metal layer is not separated from the underlying silicon oxide. To increase the mechanical consistency of these outer rings, we can use a set of through-holes to connect them. To make the outer ring more robust, we can use a concentric array of through-hole rings instead of a regular square array of through-holes, as used in a sensing mass component. However, in this case, no holes will penetrate the outer ring, as occurs in the sensing mass component, so the ring will not be broken, and the ring can be continuous.

[0104] Another implementation aspect that can be applied to the last two options is that, since we neither use vertical metal walls to short-circuit the top and bottom metal planes nor capacitive anchors to connect them, we can reduce the size of the bottom metal plane compared to the larger size of the top metal plane. This is because the lateral over-etching of the top metal will be greater than that of the bottom metal layer, since vHF needs to etch downwards to reach this point first in order to etch the bottom metal layer. Lateral over-etching is the distance between the outermost edge of the passivation opening window above the MEMS device that we need to release and the outermost position of the etched silicon oxide after the vHF post-processing step. In other words, since we do not use vertical metal walls that short-circuit from top to bottom, nor capacitive anchors, but instead surround the MEMS device with a metal region extending into the surrounding silicon oxide, a portion of this metal region will have its surrounding silicon oxide etched away during the vHF step, beyond which it will no longer be etched.

[0105] Using this method, we reduce the parasitic capacitance between the top and bottom metal planes, which is also the parasitic capacitance between the top or bottom metal plane and the movable parts of the MEMS device when using the second method disclosed above, i.e., when we short-circuit the component between the top and bottom metal planes using one of these vertical planes or connections. This reduction in parasitic capacitance leads to an improvement in device sensitivity or performance.

[0106] The reduction in the width of the outer ring at the bottom metal plate compared to the top metal plate will depend on the CMOS process and overall design. However, in some embodiments, this reduction will be between 10% and 50%, with a preferred value of 30%. In some embodiments, the width of the outer ring at the top metal plate is 20 μm, meaning that the outer ring width at the bottom metal plate can have a preferred size of 6 μm. If the diameter of the center disk (detector mass plus spring) is 50 μm, the total size of the top plate can have a diameter of 90 μm, and the total diameter of the bottom plate can be 62 μm.

[0107] If we anchor the component between the top and bottom metal planes, allowing the metal region to extend around the component and eventually be buried in unetched silicon oxide, we can also make its dimensions smaller than the top metal plane but larger than the bottom metal plane. In this case, the over-etching of the metal region will be somewhere between the top and bottom metal planes. In some implementations, the width of the outer ring of the intermediate plate will be between 30% and 70% of the width of the ring on the top metal plane. In one implementation, this value will be 50%. However, this ultimately depends on the specific CMOS process and overall design. If the top metal plane has a circular shape, it can include an inner disk adjacent to the outer ring surrounding it. The inner disk can have an array of holes therein to allow vHF into the MEMS cavity, while the outer ring is solid (with the possible exception explained below for creating trenches to electrically isolate most of the outer ring).

[0108] The extension of the internal disk is, in principle, the extension of the MEMS that we want to release via vHF. However, another inventive concept is to reduce the extension of the internal disk, thereby eliminating the need for release holes around the outside of the MEMS that needs to be released. Since vHF can transmit over relatively long distances, all MEMS will be released, and we can minimize over-etching on the outer rings in all metal layers, thus enabling a reduction in the size of these outer rings. This will reduce the parasitic capacitance between the top and bottom metal plates, thereby improving the performance of the MEMS. With this reduced extension used for the release holes, the passivation opening can also be reduced, as we only need to open it above the area with the hole array.

[0109] The reduction in the internal disk that we can achieve will depend on the CMOS process, but in some implementations, the reduction on each side will be between 2 μm and 20 μm, with a preferred value of 6 μm. That is, the disk diameter will be reduced by 4 μm to 40 μm, preferably by 12 μm. This reduction in the internal disk can be achieved by reducing the outer ring to the same value on all metal layers having the outer ring. For illustration, although the internal disk and outer ring are discussed, the actual layout of the top metal layer will be a single disk. Then the etched hole array will be located in the center, covering the area defined by the size of the internal disk. Therefore, the solid area around which there are no etched holes can be referred to as the outer ring. Also for illustration, when we say that we are reducing the internal disk, this does not affect the size of the sensing mass, spring, or other components of the MEMS device that need to be released. The internal disk here only defines the area above the MEMS device or the component that needs to be released, which has the array of etched holes.

[0110] The above description also applies when there are multiple electrically disconnecting components between the top and bottom metal layers. In this case, each has its own metal extension buried in silicon oxide, and they are electrically disconnected from each other, although there will always be some electrical parasitic capacitance.

[0111] While a preferred approach is to use an external metal region to support the MEMS component between the top and bottom metal planes, enclosing all released MEMS internally for better mechanical consistency, this is not strictly necessary. This is particularly useful in the cases disclosed above, where there are two or more electrically disconnected MEMS components between the top and bottom metal layers. One example is an in-plane inertial sensor with multiple lateral electrodes for sensing acceleration in different directions.

[0112] Another variation of reducing the parasitic capacitance between the top metal plane (and the middle portion of the MEMS device, for example, if electrically shorted via a vertical metal connection) and the bottom metal plane is to add a very short trench around the entire top metal plane at a distance from the MEMS that needs to be released. In some implementations, the trench is located at half the over-etch distance. In one configuration, this is approximately 10 μm, since the total length of such a metal region around the MEMS is approximately 20 μm. But the distance can be shorter, as low as 5 μm or even less, and even less than zero. Preferably, the trench will be located at a distance between 5 μm and 15 μm. And the extension of the top metal plate can be approximately 20 μm. However, depending on the specific CMOS process characteristics, the overall MEMS design, and the desired vHF characteristics and formulation, the trench can be between 5 μm and 30 μm.

[0113] The trench width should be minimized, where process allows. This width can be 0.8 μm, but in some implementations, it will be between 0.5 μm and 2 μm, depending on the process, particularly the thickness of the top metal layer. A metal ring can be installed beyond the trench to maintain passivation. Through the trench, the outer ring is divided into two parts, one inside the other, which are electrically and mechanically disconnected. Although there will be some parasitic capacitance between the two parts, which eventually connects to the silicon oxide, the two parts will not move relative to each other.

[0114] Therefore, one might question why the outer portion of this separate outer ring needs to be retained. The reason is that over-etching occurs during the vHF post-processing steps, removing the silicon oxide between the passivation layer and the top metal layer, making the passivation layer very fragile. For this reason, it is preferable to retain the outermost metal ring to prevent the passivation layer from breaking and to provide it with support. However, depending on process characteristics and the overall design, it is possible to remove only the outer portion of the outer ring (instead of constructing trenches for the outer ring), simply reducing its diameter. This will further reduce parasitic capacitance.

[0115] A preferred embodiment features a short vertical metal wall surrounding the MEMS device and connected to a top metal plane. This vertical metal wall may or may not be connected to a moving part of the MEMS located between the top and bottom metal planes, such as a spring anchor. The purpose of this short wall (i.e., not descending to the bottom metal plane) is to prevent the vHF from etching horizontally towards its outer edge below the top metal plane, forcing the vHF to first descend to the vertical wall and then rise back, thus enabling etching towards the outer edge below the top metal plane. According to the embodiment, the short vertical metal wall may also provide mechanical consistency and / or electrical connection to other parts of the MEMS device, such as the spring anchor.

[0116] Another approach to achieving a mechanical connection without electrically short-circuiting the two parts of a MEMS without using capacitive anchors is to use a MIM layer in the MEMS fabrication process. This layer is typically not removed by vHF etching, or at least etched relatively slowly, although this depends on the specific CMOS process. This provides a more compact solution than capacitive anchors. However, the capacitance tends to be larger, and mechanical robustness may be insufficient. Nevertheless, it may still be effective in some implementations depending on the MEMS device, process, and overall design. For some implementations, using horizontal capacitive anchors instead of vertical capacitive anchors is also effective. In some configurations, hybrid designs can be achieved using the same design principles, such as any type or combination of capacitive anchors, to achieve feedthrough connections through the MEMS metal walls or planes.

[0117] The array of holes at the top metal plane 222 will be as small as possible. This array may be smaller than allowed by the process's DRC, but large enough to ensure it can be opened across all top metal thicknesses. This minimum size will depend on the specific CMOS process, particularly the top metal thickness. In some implementations, the width dimension is 0.8 μm. Below this value, it is generally difficult to fully open, resulting in lower yields. As described below, larger values ​​may not fill properly when we apply the sealing layer. Therefore, there is a trade-off: the holes cannot be too small to be opened during the patterning of the top metal layer in the CMOS process, nor too large to be properly sealed during packaging. Thus, in some implementations, the hole size will be between 0.5 μm and 1.5 μm, with a preferred value of 0.8 μm. However, the size of the etched holes may vary depending on the CMOS process, the top metal thickness, and the sealing material, thickness, and process used. In some implementations, given the very small size of the holes, they will be drawn as square holes, as virtually any other shape would have no effect when we are forcing the process, and the holes will be partially rounded during device fabrication.

[0118] The spacing between holes on the top metal plane (e.g., top plate 222) may be similar to the vertical length of the vertical distance from the top metal layer M1 to the bottom metal layer M6. In some configurations, the horizontal spacing between etched holes on the top metal layer 222 is at least twice the vertical distance between M1 and M6. In some embodiments, this distance can be larger, considering that the etching rate of vHF is slower in the vertical direction than in the horizontal direction, due to the different densities and etching rates of the multiple oxide sublayers. Since the goal is to ensure proper etching of all volumes within the MEMS cavity, the holes can be placed close enough, but at the same time, as much as possible, to prevent the formation of a weak top metal plane with so many holes and a small amount of remaining metal that it may not be able to withstand the seal on its top when the device is packaged, as explained below.

[0119] Through experimentation, we found that a sufficient value is one where the spacing between etched holes is between 50% and 200% of the height of the metal stack. This height is calculated from the lowest point of the bottom metal layer M1 to the highest point of the top metal layer (e.g., M6). A preferred value is to space the holes at a distance equal to this height (e.g., 100%). Hole spacing refers to the measured distance from the center of one hole to the center of another in both the horizontal (X) and vertical (Y) directions.

[0120] To allow vHF to drop to a minimum level of silicon oxide so that all silicon oxide that needs to be removed is properly etched in all cavities, a uniform array of holes is implemented throughout all MEMS devices within the cavity. This may result in a lateral offset relative to holes on the top metal plane; however, the preferred embodiment simply places them in the same location. If these holes pass through structures with silicon oxide interiors, such as sensing mass components, these holes can be surrounded by via walls to prevent vHF from entering through these holes and etching away the silicon oxide that we wish to keep unetched. Given the small size of these holes, they can preferably be square, and these via barriers can be implemented as square rings.

[0121] The fourth inventive concept utilizes a sealing layer, also known as repassivation, present in the WLCSP process. This layer is typically made of polyimide (PI), but can also be benzocyclobutene (BCB) or other materials to seal the MEMS cavity. This avoids the need for specific aluminum sputtering and alignment processes, reducing the complexity and cost of post-processing, which is further simplified to only vHF etching and backing. Furthermore, the use of PI or BCB is considered to provide better sealing, better coverage of the aperture array on the top metal layer. In contrast, aluminum sputtering requires very thick deposition, and even then, some apertures may not be properly sealed due to the conformal nature of the deposition. This does not occur with PI, which seals all apertures very well. In cases involving a different type of packaging than WLCSP, the process can still apply PI or BCB or other coatings and patterning (even with aluminum sputtering, although not ideal, it can be done with sufficient thickness and an appropriate set of parameters), and then proceed with any packaging process.

[0122] Another key inventive concept involves eliminating the use of metal-filled structures within the MEMS cavity. To compensate for residual metal stress, CMOS designs require a constant metal density across all regions of the ASIC. To achieve this, once the ASIC design is complete, an automated process called "metal filling" is performed, filling all empty areas with random small metal shapes to achieve the desired target metal density.

[0123] This metal filling cannot be performed within the MEMS cavity. Otherwise, after the application of vHF, all these tiny metal-filled structures would be released and would adhere to the MEMS device through static friction, preventing it from functioning properly, or simply not allowing it to function at all.

[0124] All interpretations given in this application can be applied to different CMOS nodes, different metal stacks, and even different solid-state semiconductor processes. Furthermore, when we describe top and bottom metal layers, these are typically the topmost and bottommost metal layers in the process layer stack. However, this can also apply to other metal layers. In the case of building an inertial sensor using a six-metal-layer process, we typically need all available metal layers to maximize the thickness and mass of the sensor's sensing mass. However, if the process has more available metal layers, or if we are building a different type of MEMS device, or even for an inertial sensor, if we can manage to obtain the required specifications, we may not need to use all available metal layers in the metal stack. In this case, we would preferably use the top metal layer, leaving the bottom metal layer for the ASIC to use for electrical connection. In this case, there will be no dedicated area for implementing the MEMS; instead, the MEMS will be implemented on top of the ASIC.

[0125] In all cases, the active area (FEOL) beneath the MEMS can be used to implement the ASIC. However, without available metal layers for interconnection, it will be difficult to implement the effective portion of the ASIC beneath the MEMS, as they are all used to implement the MEMS. However, depending on the process and the specific ASIC design, it may be useful to implement large transistors or other circuits requiring minimal wiring, and / or polysilicon lines (if available) can be used for that wiring. When not all metal layers in the process stack are used to implement the MEMS, then all interpretations of this application should be understood as follows: The “top” and “bottom” metal layers are not the very top and bottom of the metal stack, but rather the very top and bottom of the metal layers used to implement the MEMS device. Although preferred embodiments include the use of circular and rounded shapes, the disclosed invention can be applied to other types of shapes.

[0126] Another key inventive concept involves sensing electronics that connect to the MEMS, when the sensing electronics are capacitive MEMS sensors, such as, but not limited to, accelerometers, bone conduction sensors, motion detectors, ultrasonic sensors, or any other capacitive sensors. In some embodiments, the MEMS capacitive sensors described herein include uniquely small capacitances. This is due to the unique characteristics of their small size and minimal parasitic capacitance, resulting from several concepts explained above. Furthermore, due to their proximity to the ASIC (attached to the edge of the MEMS) and the elimination of the need to wire the MEMS to another die where the ASIC resides, or even to the top of the wafer (in wafer-on-die schemes or in cases where the MEMS is built on top of an ASIC CMOS wafer, the ASIC is placed on top of the wafer).

[0127] In some implementations, the capacitance of this MEMS sensor is approximately between 10 fF and 100 fF, or approximately 50 fF. This is about 100 times smaller than commercially available MEMS devices used in consumer electronics. This allows for entirely different sensing schemes that would be infeasible with other MEMS devices due to the excessive power consumption.

[0128] In some configurations, sensing of MEMS capacitance is accomplished by constructing a ring oscillator, where at least one capacitor in the loop is the MEMS device described herein. This ring oscillator feeds a counter, which is read and reset at each sampling period. The counter's output is already digital, and it outputs the capacitance value. This approach offers several technical advantages. First, it simplifies analog design, being entirely digital except for the ring oscillator. This means that many analog modules that would otherwise be necessary can be avoided, such as transconductance amplifiers, programmable gain amplifiers, A / D converters, analog filters, choppers, and capacitor mismatch compensation. This simplification offers numerous technical advantages: smaller ASIC area, resulting in lower manufacturing costs; reduced design time, leading to faster time-to-market; lower development costs; easier portability to other CMOS nodes and processes; and lower power consumption.

[0129] The lower power consumption stems from avoiding a large number of high-power analog modules. However, as a replacement for these modules, the process would involve continuously charging and discharging the MEMS sensor capacitor at very high frequencies, ranging from 10MHz to 100MHz, depending on the MEMS design, CMOS process, and target sensor specifications. For ordinary capacitors in the order of a few pF, this would consume too much power. However, for the MEMS sensor of this invention, with a capacitance approximately 100 times lower or less, this does not mean more but actually less power consumption, making the sensor of this invention very energy-efficient, in addition to the other advantages mentioned above for this sensing scheme.

[0130] A ring oscillator can vary its frequency due to many factors, such as power supply voltage and its noise, temperature, and process variations. To compensate for this, a second ring oscillator can be implemented using another MEMS device very closely spaced from the first, so that it will experience almost the same process, voltage, and temperature variations. The second MEMS device (or if the ring oscillator loop includes more than one MEMS device) will be slightly different, with a stiffer spring. Preferably, this will be fabricated using a wider and / or thicker (i.e., using more metal stacks) spring. In this way, the capacitance reading of the counter connected to this second sensor will shift slightly due to the magnitude of the sensor measurement (e.g., acceleration in the case of an accelerometer), but will vary in the same way as the first sensor due to all other factors, such as power supply voltage, process, and temperature variations.

[0131] In one implementation, two ring oscillators each start a separate counter until the second counter reaches a predetermined value. In this case, we read the first counter, which provides us with the sensed amplitude value, and then we reset both counters and start counting again. This predetermined value is programmable, so we can define different sampling frequencies. When the sampling frequency is low, the ring oscillators and / or counters are disabled between samples, minimizing power consumption. In some implementations, a third digital counter with a very slow digital clock is included to activate the device each time a new sample needs to be acquired.

[0132] In some implementations, to increase detection mass without increasing the size of the detection mass element, metal walls are built and / or formed around the entire periphery of the MEMS device. In this way, silicon oxide is trapped within the detection mass element and is not removed by vHF etching. Furthermore, the detection mass element has a large number of vias, which are made of tungsten, a material with a higher density than silicon oxide and aluminum, which are the materials for the metal layers. To further increase the effective density and total mass of the detection mass element, a larger and closer array of vias than allowed by the process's DRCs can be implemented. In the case of circular detection mass elements, concentric via rings can also be used, with the spacing equal to the thickness of the ring, preferably such that this spacing and the width of the ring are equal to the via size and via spacing defined by the CMOS process DRCs. Although vias in CMOS processes are typically required to be square with a fixed size, in practice we can extend these vias in one dimension, but at least we need to maintain the specified via size in another dimension. Otherwise, the wafer will not be manufactured correctly. Since we need to drill holes in the detection mass element, these circular rings may need to be interrupted around the holes. For quality inspection components and rings, or through their internal filling structures, other shapes can be achieved.

[0133] Another key inventive concept involves improvements to the pads. This is due to passivation openings not only above the MEMS device but also above each pad (i.e., at a position vertically aligned with the pad). This is why passivation openings exist in CMOS processes. This means that when vHF is applied in post-processing, the oxide below the passivation (i.e., between the passivation and the top metal layer) will be etched away. If the top metal layer at the pad is not large enough, the silicon etch will extend beyond that top metal layer and etch below the passivation, leaving no metal underneath. If this happens, a large amount of silicon oxide around the pad will be etched away, and there will be no oxide below the top passivation. As a result, the passivation will break, and a large amount of silicon oxide will be etched away, thus ruining a part of the ASIC electronics. An implementation of this technical problem is to extend at least the top metal layer compared to conventional pad designs (and even better, if we extend more or all other metal layers). This extension will depend on the details of the specific process and the vHF etch applied. In some implementations, the metal will have a lateral extension of 15 μm to 25 μm in all directions outside the passivation opening. In one implementation, the extension will be 20 μm. A rounded shape is not necessary; therefore, in various implementations, the pads will retain a square design for the passivation opening, as will the metal defining the passivation opening. However, other shapes may also be implemented.

[0134] Most of the inventive concepts disclosed herein can be applied to a wide variety of devices, including but not limited to inertial sensors, gyroscopes, pressure sensors, ultrasonic sensors, and transducers such as CMUTs, loudspeakers, magnetometers and compasses, microphones, RF switches, adjustable capacitors, RF inductors, temperature sensors, and so on. To avoid requiring CMOS foundries to increase the silicon content for passivation, we can use special formulations and / or equipment developed, for example, by Memsstar (Scotland). After the vHF etching step, we bake the wafer to sublimate any remaining fluorine.

[0135] Due to the smaller size, lower cost, and higher performance of the MEMS devices disclosed herein, coupled with their high-volume production capabilities and shorter time-to-market, the concepts of this invention enable the construction of smaller and higher-performance smartphones, wearables, and earphones, offering more functionality, longer lifespan, and autonomy thanks to more space for larger batteries. These sensors are also enabling many Internet of Things (IoT) applications, which require ultra-low-cost, small-size, high-volume sensors with extremely low power consumption (high performance). Another application example is RFIDs with embedded sensors.

[0136] Figure 9This is an exploded view of the metal layer and via layer of the MEMS device 900, including the side electrodes. Figure 9 It shows Figure 2 A variation of the implementation for sensing in-plane acceleration includes lateral electrodes without springs around the bottom portion of the detection mass. That is, the detection mass consists of four metal layers (from M2 to M5). The spring is made of metal layers M4 and M5, with an outer metal ring supporting the spring. Therefore, the detection mass does not use the metal around layers M2 and M3. In this way, we can use layers M2 and M3 to construct the lateral electrodes of the detection mass. The shape of these lateral electrodes is substantially similar to the outer ring of the aforementioned metal layers (M4 and M5), but not a complete ring, but two semi-rings. Each of these semi-rings is made of two available metal layers (M2 and M3) stacked together, meaning there are numerous through-holes inside to connect them. These through-holes are formed as an array of concentric semi-rings.

[0137] The outer diameter of these lateral electrodes is shorter than the outer ring of the upper metal layer. In this design, the outer diameter of the lateral electrodes is also shorter than the bottom metal plane, but an improvement is to make the diameter of the bottom metal plane smaller than the outer diameter of these lateral electrodes.

[0138] Because we retain the bottom metal plane, we can still sense out-of-plane acceleration. Therefore, MEMS devices have multiple electrodes, allowing the same device to sense one, two, or even three axes together. This functionality can be implemented by dividing these lateral electrodes into quarter-rings instead of half-rings. Furthermore, differential capacitance can be implemented for the X and Y axes (i.e., in-plane acceleration). While this design is suitable for inertial sensors, the same design principles (electrodes, spring supports, etc.) can be used to implement other types of capacitive sensors and actuators.

[0139] MEMS device 900 includes M6 layer 902, V5 layer 904, M5 layer 906, V4 layer 908, M4 layer 910, V3 layer 912, M3 layer 914, V2 layer 916, M2 layer 918, and M1 layer 920. M6 layer 902 includes a top plate 922 having etched holes arranged in an array and connections to the ASIC. V5 layer 904 includes an array of concentric through-hole rings 924 extending on an outer metal surface. M5 layer 906 includes a detection mass element top cover 926 with an array of etched holes. Layer 906 also includes a portion of a helical spring 928 and an outer metal ring 930. Layer V4 908 includes an array 932 of concentric via rings extending on the outer metal, a portion of a helical spring 928 extending in layer V4 908, and an array 936 of concentric via rings extending on the detection mass, the array of concentric via rings stopping at etched hole locations and surrounding them with square rings. Layer M4 910 includes a detection mass plane 938, a portion of the helical spring 928, and a portion of the outer metal ring 930. Layer V3 912 includes an array of concentric via rings 944 extending on the detection mass and stopping at etched hole locations, while surrounding the hole locations with square rings. Layer M3 914 includes a detection mass metal plane 946 with an etched hole array and a lateral electrode 954 connected to the ASIC. Layer V2 916 includes an array of concentric via rings 948 extending on the detection mass, stopping at etched hole locations, and surrounding the etched hole locations with square rings. V2 layer 916 also includes an array 956 of concentric via semi-rings extending on the lateral electrodes. M2 layer 918 includes a metal bottom cover 950 of the detection quality component with an array of etched holes. M2 layer 918 also includes lateral electrodes 958. M1 layer 920 includes a bottom metal plane 952, which includes a connection to the ASIC.

[0140] Elements or steps of the different embodiments described may be combined to form other embodiments not previously specifically described. Elements or steps may be omitted from the previously described system or process without adversely affecting its operation or the overall operation of the system. Furthermore, various individual elements or steps may be combined into one or more individual elements or steps to perform the functions described in this specification.

[0141] Other embodiments not specifically described in this specification are also within the scope of the following claims.

Claims

1. A MEMS device formed using materials of the back-end-of-line of a CMOS process, wherein: post-processing of vHF and back-lining is applied to form the MEMS device, and the total size of the MEMS device is between 50 pm and 150 pm; the MEMS device further comprises a set of at least three springs, the springs being evenly distributed around the MEMS device and rotating around a central axis of the MEMS device; wherein the shape of the device is rounded and the springs are helical in shape.

2. The MEMS device of claim 1, wherein, the total size of the MEMS device is less than 100 pm.

3. The MEMS device of any of claims 1-2, wherein, the springs are made of one of: a stack of at least two metal layers and a single metal layer.

4. The MEMS device of any of claims 1-2, wherein, the MEMS device is an inertial sensor.

5. The MEMS device of any of claims 1-2, comprising a proof mass, wherein, the proof mass is made of the springs and a stack of four metal layers, the springs being one of: made with and connected to a top metal layer of the stack forming the proof mass, and connected to two top metal layers of the stack.

6. The MEMS device of any of claims 1-2, wherein, the springs are connected to an outer ring such that a portion of the springs remains buried in silicon oxide of an outer edge of the outer ring after the vHF etching.

7. The MEMS device of any of claims 1-2, wherein, the MEMS device has a top metal plane and a bottom metal plane, the bottom metal plane being smaller than the top metal plane.

8. The MEMS device of claim 7, wherein, the outer ring width of the bottom metal plane is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane.

9. The MEMS device of any one of claims 1-2, comprising a pad, wherein the pad comprises a top metal layer arranged to laterally extend 15 pm to 25 pm in all directions to exceed a vertically aligned passivation opening.

10. The MEMS device of any of claims 1-2, wherein, the MEMS device is formed within a MEMS cavity that does not include a metal fill structure.

11. A MEMS device comprising a set of at least three springs, the springs being evenly distributed around the MEMS device and rotating around a central axis of the MEMS device, wherein, the shape of the device is rounded and the springs have a helical shape.

12. The MEMS device of claim 11, wherein, the springs are made of one of: a stack of at least two metal layers and a single metal layer.

13. The MEMS device of any of claims 11-12, wherein, the MEMS device is an inertial sensor.

14. The MEMS device of any of claims 11-12, comprising a proof mass, wherein, the proof mass is made of the springs and a stack of four metal layers, the springs being one of: connected to a top metal layer of the stack forming the proof mass, and connected to two top metal layers of the stack.

15. The MEMS device of claim 11, wherein, the ratio of maximum displacement to spring length is at least 1%.

16. The MEMS device of claim 15, wherein, the proof mass is made of the springs and a stack of four metal layers, the springs being one of: connected to a top metal layer of the stack forming the proof mass, and connected to two top metal layers of the stack.

17. The MEMS device of any one of claims 15 and 16, wherein: the springs are connected to an outer ring such that a portion of the springs remains buried in silicon oxide on an outer edge of the outer ring after the vHF etching, and the outer ring width of the bottom metal plane is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane.

18. A method of fabricating a MEMS device using materials of a back end of the line of a CMOS process, the method comprising: post-processing of vHF and back-lining is applied to form the MEMS device, a set of at least three springs is formed, the springs being evenly distributed around the MEMS device and rotating around a central axis of the MEMS device, Forming a rounded device shape and forming a spring having a spiral shape wherein the total size of the MEMS device is between 50 pm and 150 pm.

19. The method of claim 18, wherein, The total size of the MEMS device is less than 100 pm.

20. The method of any of claims 18-19, comprising forming the spring with one of a stack of at least two metal layers and a single metal layer.

21. The method of any of claims 18-19, wherein, The MEMS device is an inertial sensor.

22. The method of any of claims 18-19, comprising forming a detection mass, wherein, The proof mass is made of the spring and a stack of four metal layers, and the spring is one of connected to a top metal layer of the proof mass forming the stack, and connected to two top metal layers of the stack.

23. The method of any of claims 18-19, comprising connecting the spring to an outer ring such that a portion of the spring remains buried in silicon oxide on an outer edge of the outer ring after vHF etching.

24. The method of any of claims 18-19, comprising forming a MEMS device having a top metal plane and a bottom metal plane, the bottom metal plane being smaller than the top metal plane.

25. The method of claim 24, comprising forming the bottom metal plane with an outer ring width that is less than or equal to 10% to 50% of an outer ring width of the top metal plane.

26. The method of any of claims 18-19, comprising forming a pad, wherein the pad comprises a top metal layer arranged to laterally extend 15 pm to 25 pm in all directions to beyond a vertically aligned passivation opening.

27. The method of any of claims 18-19, comprising forming the MEMS device within a MEMS cavity, wherein the MEMS cavity does not include a metal fill structure.

28. A method of manufacturing a MEMS device, the method comprising forming a set of at least three springs, the springs being evenly distributed around the MEMS device and rotating around a central axis of the MEMS device, and forming a rounded MEMS device shape and forming a spring having a spiral shape.

29. The method of claim 28, comprising forming the spring with one of a stack of at least two metal layers and a single metal layer.

30. The method of any of claims 28-29, wherein, The MEMS device is an inertial sensor.

31. The method of any of claims 28-29, comprising forming a detection mass, wherein, The proof mass is made of a stack of four metal layers and the spring, the spring being one of connected to a top metal layer of the proof mass forming the stack, and connected to two top metal layers of the stack.

32. The method of claim 28, comprising forming a spring, wherein, A ratio of maximum displacement to spring length is at least 1%.

33. The method of claim 32, comprising forming a proof mass comprising a stack of four metal layers and the spring, wherein, The spring is one of connected to a top metal layer of the proof mass forming the stack, and connected to two top metal layers of the stack.

34. The method of any one of claims 32 and 33, comprising: connecting the spring to an outer ring such that a portion of the spring remains buried in silicon oxide on an outer edge of the outer ring after vHF etching, and The outer ring width of the bottom metal plane is formed to be less than or equal to 10-50% of the outer ring width of the top metal plane.

35. A smartphone, wearable device, earbud, or Internet of Things (loT) device comprising the MEMS device of any of claims 1-17.

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