Asynchronous data transmission processing method, system on chip and computer readable storage medium

Abstract

The application provides an asynchronous data transmission processing method, a system chip and a computer readable storage medium. The method comprises the following steps: judging whether a first request signal received from a receiving module changes from a low level signal to a high level signal, and switching a level of a second request signal sent by the receiving module if yes; judging whether a first completion signal received from the receiving module changes from a low level signal to a high level signal, and switching a level of a second completion signal sent by the sending module if yes; judging whether a first request signal sent by a sending module changes from a high level signal to a low level signal, and switching a level of a second request signal sent by the receiving module if yes; and judging whether a first completion signal received from the receiving module changes from a high level signal to a low level signal, and switching a level of a second completion signal sent by the sending module if yes. The method can avoid the problem that a module clock frequency difference is too large to be sampled and improve data transmission efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of asynchronous data transmission, in particular to an asynchronous data transmission processing method, a system on chip and a computer readable storage medium. BACKGROUND

[0002] In a system on chip, information interaction modules across clock domains are often included. In order to ensure the stability of data transmission, asynchronous processing is required for the information interaction modules.

[0003] In a clock domain, signal transmission between a sending module and a receiving module needs to be synchronized. Referring to Figure 1 , a system on chip includes a sending module 10, a receiving module 11 and a synchronization module 12. The sending module 10 sends a first request signal to the synchronization module 12, and the synchronization module 12 sends a second request signal to the receiving module 11 after synchronization. The sending module 10 sends data to the receiving module 11. The receiving module 11 sends a first completion signal to the synchronization module 12, and the synchronization module 12 sends a second completion signal to the sending module 10 after synchronization.

[0004] The sending module, the receiving module and the synchronization module all determine whether there is a request for data by detecting the rising edge of a signal. Referring to Figure 2 , the sending module switches the first request signal from low to high, the synchronization module switches the second request signal from low to high after synchronization, and the receiving module starts to receive data after receiving the second request signal switched from low to high. After the data is received, the receiving module switches the first completion signal from low to high, and the synchronization module switches the second completion signal from low to high after synchronization, indicating that the current data transmission is completed. The sending module switches the high level of the first request signal to low after receiving the second completion signal switched from low to high, and prepares for the next data transmission.

[0005] Referring to Figure 3 , when the clock frequency of the receiving module is lower than that of the sending module, the sending module switches the first request signal from high to low after receiving the second completion signal switched from low to high, and immediately performs the next data transmission, quickly switching the first request signal from low to high. In the dashed box 15, due to the low clock frequency of the receiving module, the receiving module fails to receive the second request signal switched from low to high in time, and cannot complete the second transmission.

[0006] To avoid this problem, the sending module needs to wait for a period of time after the first request signal is switched from high level to low level, so that the receiving module detects that the first request signal is switched from low level to high level, and then switches the first request signal from low level to high level. However, this way will increase the time of data transmission, and the efficiency of data transmission is reduced.

[0007] Referring to Figure 4 When the clock frequency of the receiving module is greater than that of the sending module, the receiving module switches the first completion signal from low level to high level, and then switches the first completion signal from high level to low level. In the dashed box 16, because the clock frequency of the sending module is smaller, the synchronization module does not synchronize in time, and the flow of data transmission is not completed, so that the next data transmission cannot be performed.

[0008] To avoid this problem, the receiving module needs to wait for a period of time after the first completion signal is switched from high level to low level, so that the sending module detects that the first request signal is switched from high level to low level, and then switches the first request signal from low level to high level. However, this way will increase the time of data transmission, and the efficiency of data transmission is reduced. SUMMARY

[0009] The first object of the present application is to provide an asynchronous data transmission processing method for normal sampling and improving the efficiency of data transmission when the clock difference between the sending module and the receiving module is large.

[0010] The second object of the present application is to provide a system-level chip applying the above asynchronous data transmission processing method.

[0011] The third object of the present application is to provide a computer storage medium for implementing the above asynchronous data transmission processing method.

[0012] To achieve the above first object, the present application provides an asynchronous data transmission processing method, which comprises: receiving a first request signal of a sending module, judging whether the first request signal is switched from low level signal to high level signal, if yes, switching the level of a second request signal sent to the receiving module; judging whether a first completion signal received from the receiving module is switched from low level signal to high level signal, if yes, switching the level of a second completion signal sent to the sending module; judging whether the first request signal sent by the sending module is switched from high level signal to low level signal, if yes, switching the level of the second request signal sent to the receiving module; judging whether the first completion signal received from the receiving module is switched from high level signal to low level signal, if yes, switching the level of the second completion signal sent to the sending module.

[0013] As can be seen from the above scheme, the asynchronous data transmission processing method can indicate that there is a data processing request when the signal changes from low level to high level, and can also indicate that there is a data processing request when the signal changes from high level to low level. When the level switching is detected, there is a new data request. The method can avoid the problem that the sending module and the receiving module cannot be normally sampled when the clock frequencies are greatly different, and can save the time period required for the sending module or the receiving module to recover when the level is switched, thereby improving the asynchronous transmission efficiency.

[0014] In a further scheme, if the first request signal changes from a low level signal to a high level signal, the level of the second request signal sent to the receiving module is switched from low level to high level; and if the first completion signal changes from a low level signal to a high level signal, the second completion signal sent to the sending module is switched from low level to high level.

[0015] As can be seen, in a data transmission period, if the first request signal changes from a low level signal to a high level signal, the second request signal also changes from a low level signal to a high level signal; and if the first completion signal changes from a low level signal to a high level signal, the second completion signal also changes from a low level signal to a high level signal.

[0016] In a further scheme, if the first request signal changes from a high level signal to a low level signal, the level of the second request signal sent to the receiving module is switched from high level to low level; and if the first completion signal changes from a high level signal to a low level signal, the second completion signal sent to the sending module is switched from high level to low level.

[0017] As can be seen, in a data transmission period, if the first request signal changes from a high level signal to a low level signal, the second request signal also changes from a high level signal to a low level signal; and if the first completion signal changes from a high level signal to a low level signal, the second completion signal also changes from a high level signal to a low level signal.

[0018] In a further scheme, after the level of the second request signal received by the receiving module is switched, the receiving module starts to receive data.

[0019] As can be seen, the sending module sends the first request signal to inform the receiving module that data is ready, and after the receiving module receives the second request signal, the receiving module receives the data request information from the sending module, and then starts to transmit data.

[0020] In a further scheme, after the receiving module finishes receiving data, the level of the first completion signal is switched.

[0021] Therefore, after the receiving module finishes receiving data, the level of the first completion signal needs to be switched to inform the sending module that the data has been received.

[0022] In a further solution, after the sending module receives the level switching of the second completion signal, the level of the first request signal is switched.

[0023] Therefore, after the sending module receives the information that the receiving module has finished receiving, the level of the first request signal is switched to inform the receiving module that the next data is ready for receiving.

[0024] To achieve the second purpose, the application provides a system-level chip, which comprises a sending module, a receiving module and a synchronization module, the sending module sends a first request signal to the synchronization module, the synchronization module sends a second request signal to the receiving module, the receiving module sends a first completion signal to the synchronization module, and the synchronization module sends a second completion signal to the sending module; the synchronization module has a processor and a memory, the memory stores a computer program, and the processor executes the computer program to perform the asynchronous data transmission processing method.

[0025] To achieve the third purpose, the application provides a computer program which, when executed by a processor, implements the asynchronous data transmission processing method. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a system block diagram of an embodiment of the system-level chip.

[0027] Figure 2 is a timing waveform diagram of the asynchronous data transmission processing method in the prior art.

[0028] Figure 3 is a timing waveform diagram in which the signals in the asynchronous data transmission processing method in the prior art cannot be normally sampled.

[0029] Figure 4 is a timing waveform diagram in which the signals in the asynchronous data transmission processing method in the prior art cannot be normally sampled.

[0030] Figure 5 is a flowchart of an embodiment of the asynchronous data transmission processing method of the application.

[0031] Figure 6 is a timing waveform diagram of an embodiment of the asynchronous data transmission processing method of the application.

[0032] Figure 7 is a timing waveform diagram of the sending module and the receiving module in an embodiment of the asynchronous data transmission processing method of the application when the clock domain frequencies are equal.

[0033] Figure 8is the timing waveform diagram when the clock domain frequency of the sending module is greater than the clock domain frequency of the receiving module in the embodiment of the asynchronous data transmission processing method of the present application.

[0034] Figure 9 is the timing waveform diagram when the clock domain frequency of the sending module is less than the clock domain frequency of the receiving module in the embodiment of the asynchronous data transmission processing method of the present application.

[0035] Figure 10 is the timing waveform diagram of multiple data transmissions in the embodiment of the asynchronous data transmission processing method of the present application.

[0036] The present application is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0037] Embodiment of the asynchronous data transmission processing method:

[0038] In order to solve the problem of being unable to sample and low transmission efficiency caused by too large clock difference, the asynchronous data transmission processing method provided in the embodiment is that when the signal appears level switching, there is a new data request. Referring to Figure 5 , Figure 5 is the flow chart of the embodiment of the asynchronous data transmission processing method. Referring to Figure 6 , Figure 6 is the timing waveform diagram of the embodiment of the asynchronous data transmission processing method. First, step S1 is performed, and the first request signal of the sending module is received. The first request signal of the sending module is received by the synchronous module, and after synchronous processing, the second request signal is sent to the receiving module.

[0039] After receiving the first request signal of the sending module, step S2 is performed to determine whether the first request signal changes from low level signal to high level signal. As shown in the dashed box 21 of Figure 6 , the first request signal changes from low level signal to high level signal, indicating that the sending module is ready for data and requests the receiving module to receive.

[0040] If the first request signal changes from low level signal to high level signal, step S3 is performed to switch the level of the second request signal sent by the receiving module. Preferably, as shown in the dashed box 22 of Figure 6 , at this time, the second request signal changes from low level to high level. After receiving the level switching signal of the second request, the receiving module starts to receive the data sent by the sending module.

[0041] If the first request signal does not change from low level signal to high level signal, step S2 is continued to determine whether the first request signal changes from low level signal to high level signal.

[0042] After the level of the second request signal sent by the receiving module is switched, step S4 is performed to determine whether the first completion signal received from the receiving module changes from a low level signal to a high level signal. After the level of the second request signal is switched, the receiving module starts to receive data. When the data receiving is completed, the receiving module changes the first completion signal from the low level signal to the high level signal, as shown in the dashed box 23, to indicate that the receiving module has completed the data receiving and informs the sending module that the data sending is completed and the next data transmission can be prepared. Figure 6

[0043] If the first completion signal received by the receiving module changes from the low level signal to the high level signal, step S5 is performed to switch the level of the second completion signal sent to the sending module. The second completion signal is switched from the low level to the high level, as shown in the dashed box 24. When the level of the second completion signal is received by the sending module, the sending module starts to prepare new data for the next data transmission. Figure 6

[0044] If the first completion signal received by the receiving module does not change from the low level signal to the high level signal, step S4 is continuously performed to determine whether the first completion signal received from the receiving module changes from the low level signal to the high level signal.

[0045] After step S5 is completed, the level of the first request signal sent by the sending module is switched. Then step S6 is performed to determine whether the first request signal received from the sending module changes from the high level signal to the low level signal. The first request signal changes from the high level to the low level, as shown in the dashed box 25, to indicate that the sending module has prepared the data and requests the receiving module to receive. Figure 6

[0046] If yes, step S7 is performed to switch the level of the second request signal sent to the receiving module. The level of the second request signal is switched from the high level to the low level, as shown in the dashed box 26. After the level of the second request signal is received by the receiving module, the receiving module starts to receive data. Figure 6

[0047] If the first request signal received by the sending module does not change from the high level signal to the low level signal, step S6 is continuously performed to determine whether the first request signal received from the sending module changes from the high level signal to the low level signal.

[0048] After the data receiving of the receiving module is completed, step S8 is performed to determine whether the first completion signal received from the receiving module changes from the high level signal to the low level signal. The first completion signal changes from the high level to the low level, as shown in the dashed box 27.

[0049] Figure 6 ​​​​​the dashed box 27, the receiving module changes the level of the first completion signal from high to low, indicating that the receiving module has completed receiving data, informing the sending module that the data transmission is completed and the next data transmission can be prepared. If yes, step S9 is executed to switch the level of the second completion signal sent to the sending module. As shown in the dashed box 28, the level of the second completion signal is switched from high to low. When the sending module receives the level switching of the second completion signal, the sending module starts to prepare new data for the next data transmission. Figure 6

[0050] If the first completion signal received from the receiving module is not changed from low to high, step S8 is continuously executed to determine whether the first completion signal received from the receiving module is changed from low to high.

[0051] The method of the embodiment can avoid the problem that the sending module and the receiving module cannot normally sample when the clock frequencies of the sending module and the receiving module are greatly different, and can save the time period required for the sending module or the receiving module to recover when switching the level, thereby improving the asynchronous transmission efficiency.

[0052] Referring to Figure 7 , Figure 7 is a timing waveform diagram when the clock domain frequency of the sending module is equal to the clock domain frequency of the receiving module in the asynchronous data transmission processing method embodiment. At this time, the clock domain frequency of the sending module is equal to the clock domain frequency of the receiving module. The first request signal, the second request signal, the first completion signal and the second request signal can be normally sampled.

[0053] Referring to Figure 8 , Figure 8 is a timing waveform diagram when the clock domain frequency of the sending module is greater than the clock domain frequency of the receiving module in the asynchronous data transmission processing method embodiment. The dashed box 31 represents the timing waveform diagram of signal transmission when the method described in the background art is used, and the dashed box 32 represents the timing waveform diagram of signal transmission when the asynchronous data transmission processing method is used. The original second request signal in the dashed box 31 cannot switch the low level to the high level in the second transmission, and the transmission data process is interrupted. However, the method in the embodiment can be normally sampled.

[0054] Referring to Figure 9 , Figure 9 ​is a timing waveform diagram when the frequency of the clock domain of the sending module is lower than the frequency of the clock domain of the receiving module in the embodiment of the asynchronous data transmission processing method. The dashed box 41 represents the timing waveform diagram of signal transmission when the method described in the background technology is adopted, and the dashed box 42 represents the timing waveform diagram of signal transmission when the asynchronous data transmission processing method is adopted. The original second completion signal in the dashed box 41 cannot be switched from low level to high level at the second transmission, and the transmission data process is interrupted. However, the method in the embodiment can be normally sampled.

[0055] Referring to Figure 10 , Figure 10 is a timing waveform diagram of multiple data transmissions in the embodiment of the asynchronous data transmission processing method. The dashed box 51 represents the timing waveform diagram of signal transmission when the method described in the background technology is adopted, and the dashed box 52 represents the timing waveform diagram of signal transmission when the asynchronous data transmission processing is adopted. Data 1 represents the timing waveform diagram of data transmission when the conventional method is adopted, and data 2 represents the timing waveform diagram of signal transmission when the asynchronous data transmission processing is adopted. The transmission efficiency of data 1 is lower than that of data 2. When the same time is used, data 1 completes 6684 transmissions, and data 2 completes 7715 transmissions, and the data transmission efficiency is increased by 15.4%.

[0056] System on Chip Embodiment:

[0057] The system on chip in the embodiment includes a sending module, a receiving module, and a synchronization module. The synchronization module has a processor and a memory. The memory stores a computer program, and the processor executes the computer program to perform the asynchronous data transmission processing method described above.

[0058] Computer-readable storage medium embodiment:

[0059] The asynchronous data transmission processing method described in the above embodiments can be stored in a computer-readable storage medium in the form of a computer program. When the program is executed by a processor, the steps of the asynchronous data transmission processing method embodiment described above can be completed. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0060] The above merely describes the preferred embodiments of the present application, but the design concept of the present application is not limited thereto, and more other equivalent embodiments can be included without departing from the concept of the present application, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present application.

Claims

1. An asynchronous data transmission processing method, comprising: receiving a first request signal from a sending module, determining whether the first request signal changes from a low level signal to a high level signal, and if so, switching the level of a second request signal sent to a receiving module; determining whether a first completion signal received from the receiving module changes from a low level signal to a high level signal, and if so, switching the level of a second completion signal sent to the sending module; if the first completion signal changes from a low level signal to a high level signal, switching the level of the second completion signal sent to the sending module from a low level to a high level; characterized in that: determining whether the first request signal sent by the sending module changes from a high level signal to a low level signal, and if so, switching the level of the second request signal sent to the receiving module; determining whether the first completion signal received from the receiving module changes from a high level signal to a low level signal, and if so, switching the level of the second completion signal sent to the sending module; if the first completion signal changes from a high level signal to a low level signal, switching the level of the second completion signal sent to the sending module from a high level to a low level; after the receiving module finishes receiving data, switching the level of the first completion signal.

2. The asynchronous data transmission processing method according to claim 1, characterized in that: if the first request signal changes from a low level signal to a high level signal, switching the level of the second request signal sent to the receiving module from a low level to a high level.

3. The asynchronous data transmission processing method according to claim 1, characterized in that: if the first request signal changes from a high level signal to a low level signal, switching the level of the second request signal sent to the receiving module from a high level to a low level.

4. The asynchronous data transmission processing method according to any one of claims 1 to 3, characterized in that: after the level of the second request signal received by the receiving module is switched, the receiving module starts receiving data.

5. The asynchronous data transmission processing method according to any one of claims 1 to 3, characterized in that: after the level of the second completion signal received by the sending module is switched, the sending module switches the level of the first request signal.

6. A system on chip, comprising a sending module, a receiving module and a synchronization module, the sending module sends a first request signal to the synchronization module, the synchronization module sends a second request signal to the receiving module, the receiving module sends a first completion signal to the synchronization module, and the synchronization module sends a second completion signal to the sending module; characterized in that: the synchronization module has a processor and a memory, the memory stores a computer program, and the processor executes the computer program to perform the asynchronous data transmission processing method according to any one of claims 1 to 5.

7. A computer readable storage medium, having a computer program stored thereon, characterized in that: The computer program, when executed by a processor, implements the asynchronous data transmission processing method according to any one of claims 1 to 5.

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