Data processing method, device, equipment, readable storage medium and program product
By storing and executing target data blocks in a pre-defined dedicated memory, the problem of low cache hit rate in dynamic binary translation is solved, thus improving execution efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2022-08-16
- Publication Date
- 2026-06-23
AI Technical Summary
In dynamic binary translation, the cache hit rate of the target code block is low, leading to increased execution overhead.
By obtaining the starting address of the data block to be translated, the starting address of the target data block is determined, and the target data block is stored and executed in a preset dedicated memory. If the target data block is not stored in the preset dedicated memory, the data block to be translated is translated into the target data block and stored in the preset dedicated memory.
This improved the cache hit rate of target data blocks in dynamic binary translation, thereby increasing execution efficiency.
Smart Images
Figure CN115408010B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a data processing method, apparatus, device, readable storage medium, and program product. Background Technology
[0002] Binary translation is a technique for translating binary programs, enabling the execution of binary programs running on one processor on another. Binary translation can be divided into dynamic binary translation and static binary translation. Dynamic binary translation involves translating and running the program simultaneously; the translation process from the source program to the target program occurs concurrently with the target program's execution. Static binary translation involves completing most of the translation before the target program runs, allowing direct loading and execution of the already translated binary code. Processors typically have a cache, where instructions and data can be accessed at high speed. In dynamic binary translation, although the target code blocks are stored in the cache, the cache hit rate is low, resulting in additional execution overhead. Summary of the Invention
[0003] This application addresses the shortcomings of existing methods by proposing a data processing method, apparatus, device, computer-readable storage medium, and computer program product to solve the problem of how to improve the cache hit rate of target code blocks.
[0004] Firstly, this application provides a data processing method, including:
[0005] Obtain the starting address of the data block to be translated;
[0006] Based on the starting address of the data block to be translated, the starting address of the target data block is determined. The target data block is the data block obtained by translating the data block to be translated.
[0007] If, based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated will be translated into the target data block.
[0008] The target data block is stored in a preset dedicated memory, and the target data block is executed in the preset dedicated memory.
[0009] In one embodiment, if it is determined that the target data block has been stored in a preset dedicated memory based on the starting address of the target data block, the target data block is executed in the preset dedicated memory.
[0010] In one embodiment, determining the starting address of the target data block based on the starting address of the data block to be translated includes:
[0011] Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
[0012] In one embodiment, if it is determined, based on the starting address of the target data block, that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block, including:
[0013] If the starting address of the target data block is different from the addresses of all program address spaces in the preset relation table, it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block; the preset relation table includes the addresses of program address spaces in the preset dedicated memory.
[0014] In one embodiment, storing the target data block in a preset dedicated memory includes:
[0015] Determine the address of the target data block in the program address space;
[0016] Based on the address of the target data block in the program address space, the target data block is stored in a preset dedicated memory using a preset replacement algorithm.
[0017] In one embodiment, executing the target data block in a preset dedicated memory includes:
[0018] Restore the context of the target program corresponding to the target data block;
[0019] Based on the context, the target data block is executed in a pre-defined dedicated memory; the target program includes the target data block.
[0020] Secondly, this application provides a data processing apparatus, comprising:
[0021] A dedicated memory is pre-set to store the target data block;
[0022] The data processing unit includes a first processing module, a second processing module, a third processing module, and a fourth processing module.
[0023] The first processing module is used to obtain the starting address of the data block to be translated;
[0024] The second processing module is used to determine the starting address of the target data block based on the starting address of the data block to be translated. The target data block is the data block obtained by translating the data block to be translated.
[0025] The third processing module is used to translate the data block to be translated into the target data block if it is determined that the target data block is not stored in the preset dedicated memory based on the starting address of the target data block.
[0026] The fourth processing module is used to store the target data block in a preset dedicated memory and execute the target data block in the preset dedicated memory.
[0027] In one embodiment, the third processing module is further configured to:
[0028] Based on the starting address of the target data block, if it is determined that the target data block has been stored in the preset dedicated memory, then the target data block is executed in the preset dedicated memory.
[0029] In one embodiment, the second processing module is specifically used for:
[0030] Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
[0031] In one embodiment, the third processing module is specifically used for:
[0032] If the starting address of the target data block is different from the addresses of all program address spaces in the preset relation table, it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block; the preset relation table includes the addresses of program address spaces in the preset dedicated memory.
[0033] In one embodiment, the fourth processing module is specifically used for:
[0034] Determine the address of the target data block in the program address space;
[0035] Based on the address of the target data block in the program address space, the target data block is stored in a preset dedicated memory using a preset replacement algorithm.
[0036] In one embodiment, the fourth processing module is specifically used for:
[0037] Restore the context of the target program corresponding to the target data block;
[0038] Based on the context, the target data block is executed in a pre-defined dedicated memory; the target program includes the target data block.
[0039] Thirdly, this application provides an electronic device, including: a processor, a memory, and a bus;
[0040] A bus is used to connect the processor and memory;
[0041] Memory, used to store operation instructions;
[0042] A processor is used to execute the data processing method of the first aspect of this application by invoking operation instructions.
[0043] Fourthly, this application provides a computer-readable storage medium storing a computer program, which is used to perform the data processing method of the first aspect of this application.
[0044] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data processing method in the first aspect of this application.
[0045] The technical solution provided in this application has at least the following beneficial effects:
[0046] Obtain the starting address of the data block to be translated; based on the starting address of the data block to be translated, determine the starting address of the target data block, which is the data block obtained by translating the data block to be translated; if based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block; store the target data block in the preset dedicated memory, and execute the target data block in the preset dedicated memory; in this way, dynamic binary translation is performed based on the preset dedicated memory, which improves the cache hit rate of the target data block (e.g., the target code block) in dynamic binary translation. Attached Figure Description
[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.
[0048] Figure 1 This is a schematic diagram of the function body, the start boundary address of the function, and the end boundary address of the function.
[0049] Figure 2 This is a schematic diagram of dynamic binary translation;
[0050] Figure 3 This is a schematic diagram of the architecture of the data processing system provided in the embodiments of this application;
[0051] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application;
[0052] Figure 5 A flowchart illustrating another data processing method provided in an embodiment of this application;
[0053] Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;
[0054] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0055] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0056] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” indicates implementation as “A,” or implementation as “B,” or implementation as “A and B.”
[0057] It is understood that in the specific embodiments of this application, data related to data processing is involved. When the above embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.
[0058] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0059] This application embodiment provides a data processing method for a data processing system, which relates to fields such as binary translation.
[0060] To better understand and explain the solutions of the embodiments of this application, some technical terms involved in the embodiments of this application will be briefly explained below.
[0061] Function body, function start boundary address, and function end boundary address: For example, a disassembled RISC-V64 ELF binary file, which disassembles .text resources, contains a main function within the .text code segment; such as... Figure 1As shown, the function body of the main function runs from line 8 to line 22. Line 8 and line 22 are the start boundary and end boundary of the main function, respectively. That is, the start boundary address of the main function is 0, and the end boundary address of the main function is 38.
[0062] Dynamic binary translation: such as Figure 2 As shown, the application binary file is fed into the binary translation engine, which continuously converts the program's machine code and writes the resulting code blocks into the translated code cache. The application binary file is the source program, which can include multiple source code blocks. The binary translation engine is the translator, and the resulting code blocks are the target code blocks.
[0063] Program memory layout: Program memory layout is the structural information of a program in memory determined by the operating system and its loader; the program is loaded into memory according to this structural information.
[0064] Control Flow Graph (CFG): A control flow graph is a representation of the program's control flow. CFG is a representation in computer science that uses the mathematical method of graphs to indicate all the paths that a computer program takes during execution.
[0065] The solutions provided in this application relate to data processing technology. The technical solutions of this application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.
[0066] To better understand the solution provided in the embodiments of this application, the solution will be described below in conjunction with a specific application scenario.
[0067] In one embodiment, Figure 3 The diagram shows an architecture of a data processing system applicable to embodiments of this application. It is understood that the data processing methods provided in these embodiments can be applied to, but are not limited to, applications such as... Figure 3 In the application scenarios shown.
[0068] In this example, as Figure 3As shown, the data processing system in this example resides within the processor. The architecture of this system can include, but is not limited to, a processor core (CPU Core), cache, main memory, application-specific memory (ASM), and a bus. The CPU Core, cache, main memory, and ASM communicate via the bus. The CPU Core can access main memory through the cache instead of directly. The ASM can be scratch-pad memory, and it can be SRAM. The SRAM serving as the ASM can be part of the physical processor integrated circuit. The ASM has similar access speed to the cache, but it is a heterogeneous cache. Typical access times for storage technologies are shown in Table 1.
[0069] Table 1: Typical access times for storage technologies
[0070] Storage technology Typical visit time Cache ~3ns Main Memory (DRAM) ~100ns Scratch-Pad Memory ~3ns
[0071] Specifically, the CPU access speed to the cache is approximately 3ns (nanosecond), the CPU access speed to the main memory is approximately 100ns, and the CPU access speed to the on-chip SRAM (i.e., Scratch-Pad Memory) designed for embedded environments is approximately 3ns.
[0072] Modern computers are multi-level storage systems. From a memory speed perspective, even minor improvements to the computer system, such as adding ASM (Automatic Memory Memory) to reduce cache misses, can significantly increase program execution speed. ASM can be Scratch-Pad Memory, which refers to on-chip data memory. Scratch-Pad Memory maps to an address space that does not intersect with Main Memory but is connected to the same address and data buses. The main difference between Scratch-Pad Memory and Cache is that Scratch-Pad Memory simply guarantees single-cycle access time; conversely, cache access is subject to more constraints from system design rules, such as access time being affected by mandatory access rules, cache capacity, and access conflicts / misses.
[0073] ASM maps to contiguous regions in the processor's physical address space, requiring some form of address translation for program code to use it transparently. In practice, ASM address translation can be performed by software or assisted by hardware, such as translating addresses in the ASM's physical address space into addresses in the ASM's program address space.
[0074] It is understood that the above is only one example, and this embodiment is not limited here.
[0075] See Figure 4 , Figure 4 This illustration shows a flowchart of a data processing method provided in an embodiment of this application. This method can be executed by any electronic device, such as a server or terminal. As an optional implementation, the method can be executed by a server or terminal. For ease of description, in the following description of some optional embodiments, a server or terminal will be used as an example to illustrate the execution of this method. Figure 4 As shown, the data processing method provided in this application includes the following steps:
[0076] S401, obtain the starting address of the data block to be translated.
[0077] Specifically, the data block to be translated can be an instruction block to be translated; the data block to be translated can be a code block in the source program, that is, the data block to be translated can be a source code block; the source program can be the binary program to be translated; among them, the code block is, for example... Figure 1 The `main` function shown in the diagram has its function body running from line 8 to line 22. Line 8 marks the start boundary of the code block, and line 22 marks the end boundary. Specifically, the start boundary address is 0, and the end boundary address is 38. The starting address of the data block to be translated can be the start boundary address of the data block to be translated, for example... Figure 1 The 8th line shown indicates that the starting address of the data block to be translated is 0.
[0078] S402, Based on the starting address of the data block to be translated, determine the starting address of the target data block, where the target data block is the data block obtained by translating the data block to be translated.
[0079] Specifically, the target data block can be a code block in the target program, that is, the target data block can be a target code block; the target program can be a translated binary program, that is, the target program is a binary program obtained by translating the source program. The starting address of the target data block can be the starting boundary address of the target data block.
[0080] S403, if it is determined that the target data block is not stored in the preset dedicated memory based on the starting address of the target data block, then the data block to be translated is translated into the target data block.
[0081] Specifically, the pre-defined dedicated memory (ASM) can be a temporary storage memory. For example, the ASM may already store 10 code blocks and the addresses of their program address spaces. The ASM corresponds to a relation table in the translator, which includes the addresses of the program address spaces of the 10 code blocks and the file addresses of the source code blocks corresponding to each of the 10 code blocks. The starting address of the target data block can be the address of its program address space. If the address of the target data block's program address space is the same as the address of a code block in the relation table, then the target data block is determined to be in the ASM, i.e., the pre-defined dedicated memory has already stored the target data block. If the address of the target data block's program address space is different from the addresses of all code blocks in the relation table, then the target data block is determined not to be in the ASM, i.e., the pre-defined dedicated memory does not store the target data block.
[0082] S404, store the target data block in a preset dedicated memory, and execute the target data block in the preset dedicated memory.
[0083] Specifically, in dynamic binary translation, if it is determined that the target data block is not stored in the preset dedicated memory, the data block to be translated is translated into the target data block and the target data block is stored in the preset dedicated memory, so that the target data block can be executed in the preset dedicated memory in real time.
[0084] In this embodiment, the starting address of the data block to be translated is obtained; based on the starting address of the data block to be translated, the starting address of the target data block is determined, and the target data block is the data block obtained by translating the data block to be translated; if based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block; the target data block is stored in the preset dedicated memory, and the target data block is executed in the preset dedicated memory; thus, dynamic binary translation is performed based on the preset dedicated memory, which improves the cache hit rate of the target data block (e.g., the target code block) in dynamic binary translation.
[0085] In one embodiment, if it is determined that the target data block has been stored in a preset dedicated memory based on the starting address of the target data block, the target data block is executed in the preset dedicated memory.
[0086] Specifically, for example, ASM already stores 10 code blocks and the addresses of their program address spaces; ASM corresponds to a relation table in the translator, which includes the addresses of the program address spaces of these 10 code blocks and the file addresses of the source code blocks corresponding to these 10 code blocks; the starting address of the target data block can be the address of its program address space; if the address of the target data block's program address space is the same as the address of a code block's program address space in the relation table, then it is determined that the target data block is in ASM, that is, it is determined that the target data block has been stored in the preset dedicated memory, so that the target data block can be executed in the preset dedicated memory in real time.
[0087] In one embodiment, determining the starting address of the target data block based on the starting address of the data block to be translated includes:
[0088] Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
[0089] Specifically, based on the starting address of the data block to be translated and the program memory layout of the target program, the layout is optimized by means of a control flow graph to determine the position of the target data block in the program memory layout, that is, the starting address of the target data block.
[0090] Specifically, the translation program determines the starting address of the target data block based on the starting address of the data block to be translated, using the CFG (Content Transfer Group). The translation program can be a binary translation processor; it can reside on a server or a terminal, and may be located on the server's processor or the terminal's processor.
[0091] In one embodiment, if it is determined, based on the starting address of the target data block, that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block, including:
[0092] If the starting address of the target data block is different from the addresses of all program address spaces in the preset relation table, it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block; the preset relation table includes the addresses of program address spaces in the preset dedicated memory.
[0093] Specifically, for example, the ASM already stores 10 code blocks and the addresses of their program address spaces; the ASM corresponds to a relation table in the translator, which includes the addresses of the program address spaces of the 10 code blocks and the file addresses of the source code blocks corresponding to each of the 10 code blocks; the starting address of the target data block can be the address of its program address space; if the address of the target data block's program address space is different from the addresses of all code blocks in the relation table, then it is determined that the target data block is not in the ASM, that is, it is determined that the target data block is not stored in the preset dedicated memory; and the translator translates the data block to be translated into the target data block.
[0094] In one embodiment, storing the target data block in a preset dedicated memory includes:
[0095] Determine the address of the target data block in the program address space;
[0096] Based on the address of the target data block in the program address space, the target data block is stored in a preset dedicated memory using a preset replacement algorithm.
[0097] Specifically, the replacement algorithm can be a code block-level FIFO (First Input First Output) replacement, LRU (Least Recently Used) replacement, etc., or a Flush-style full update, etc.; the replacement algorithm is easy to control flexibly.
[0098] The translation process determines the address of the target data block's program address space. Based on this address, a replacement algorithm replaces the code blocks stored in dedicated memory with the target data blocks. For example, multiple code blocks stored in dedicated memory are replaced with multiple target data blocks. Then, based on the address of each target data block's program address space, the multiple target data blocks are concatenated to obtain the translated binary program, i.e., the target program.
[0099] In one embodiment, executing the target data block in a preset dedicated memory includes:
[0100] Restore the context of the target program corresponding to the target data block;
[0101] Based on the context, the target data block is executed in a pre-defined dedicated memory; the target program includes the target data block.
[0102] Specifically, the translation program restores the context of the target program corresponding to the target data block. The context of the target program can be the context of the target data block in the target program, and the context of the target data block can be the state description of the execution of the target data block.
[0103] In one embodiment, during dynamic binary translation, the ASM (Automatic Memory Management System) can be explicitly controlled by software. The reason for this is that, due to the limited capacity of the ASM, it may not be able to hold all the target code blocks in the target program. By managing the ASM through the translator, the target code blocks that need to be executed can be stored in the ASM, while those that do not need to be executed can be stored in other locations, such as main memory, thereby improving the cache hit rate of target code blocks during dynamic binary translation.
[0104] For example, a portion of the target code blocks in the target program are stored in ASM, for example, ASM has a capacity of 256KB; another portion of the target code blocks in the target program are stored in main memory; when the target program is executed, for example, the target program size is 256MB, if a target code block that is about to be executed is matched in ASM, then it is determined that the target code block has hit ASM.
[0105] Applying the embodiments of this application has at least the following beneficial effects:
[0106] Dynamic binary translation is performed using dedicated memory (ASM), which improves the cache hit rate of target data blocks (such as target code blocks) during dynamic binary translation.
[0107] To better understand the methods provided in the embodiments of this application, the solutions of the embodiments of this application will be further explained below with reference to specific application scenarios.
[0108] In a specific application scenario, such as a dynamic binary translation scenario, see [link to relevant documentation]. Figure 5 This illustrates the processing flow of a data processing method, such as... Figure 5 As shown, the data processing method provided in this application includes the following steps:
[0109] S501 locates the starting address of the source code block and the starting address of the target code block.
[0110] Specifically, the starting address of the source code block is obtained through a translation program; a program control flow graph (CFG) is created through the translation program; and the starting address of the target code block is determined through the CFG based on the starting address of the source code block.
[0111] S502, determine whether the target code block has been stored in ASM; if it is determined that the target code block has not been stored in ASM, proceed to step S503; if it is determined that the target code block has been stored in ASM, proceed to step S505.
[0112] Specifically, for example, ASM already stores 10 code blocks and the addresses of their program address spaces; ASM corresponds to a relation table in the translator, which includes the addresses of the program address spaces of these 10 code blocks and the file addresses of the source code blocks corresponding to these 10 code blocks; the starting address of the target code block can be the address of its program address space; if the address of the target code block's program address space is the same as the address of a code block in the relation table, then the target code block is determined to be in ASM, that is, it is determined that the target code block has been stored in ASM; if the address of the target code block's program address space is different from the addresses of all code blocks in the relation table, then the target code block is determined not to be in ASM.
[0113] S503 translates source code blocks into object code blocks.
[0114] Specifically, a translation program translates source code blocks into target code blocks.
[0115] S504, link the target code block and refresh ASM.
[0116] Specifically, the translation process determines the address of the target code block's program address space. Based on the address of the target code block's program address space, a replacement algorithm replaces (refreshes) the code blocks stored in ASM with the target code blocks. For example, multiple code blocks stored in ASM are replaced (refreshed) with multiple target code blocks. Based on the address of the program address space of each target code block, the multiple target code blocks are concatenated (linked) to obtain the translated binary program, i.e., the target program.
[0117] S505, restore the context of the target program corresponding to the target code block.
[0118] Specifically, when the target program is paused, its context is saved; after the context is restored, the target program resumes execution from the previously paused position. For example, if the target code block is not stored in ASM, the execution of the target program can be paused, the source code block can be translated into the target code block by a translator, the target code block can be written into ASM, and then the context of the target program can be restored to execute the target code block.
[0119] S506, Execute the target code block.
[0120] Specifically, the target code block is executed in ASM.
[0121] S507, save the context of the target program corresponding to the target code block; proceed to step S501 for processing.
[0122] Specifically, after executing the target code block, the context of the target program corresponding to the target code block is saved, and the process proceeds to step S501 to locate the starting address of the new source code block and the starting address of the new target code block.
[0123] Applying the embodiments of this application has at least the following beneficial effects:
[0124] Based on ASM, dynamic binary translation is performed, which improves the cache hit rate of target code blocks in dynamic binary translation.
[0125] The application embodiment also provides a data processing apparatus, the structural schematic diagram of which is shown below. Figure 6 As shown, the data processing device 60 includes a preset dedicated memory 601 and a data processing unit 602.
[0126] A dedicated memory of 601 is preset to store the target data block;
[0127] The data processing unit 602 includes a first processing module 6021, a second processing module 6022, a third processing module 6023, and a fourth processing module 6024;
[0128] The first processing module 6021 is used to obtain the starting address of the data block to be translated;
[0129] The second processing module 6022 is used to determine the starting address of the target data block based on the starting address of the data block to be translated, wherein the target data block is the data block obtained by translating the data block to be translated.
[0130] The third processing module 6023 is used to translate the data block to be translated into the target data block if it is determined that the target data block is not stored in the preset dedicated memory based on the starting address of the target data block.
[0131] The fourth processing module 6024 is used to store the target data block in a preset dedicated memory and execute the target data block in the preset dedicated memory.
[0132] In one embodiment, the third processing module 6023 is further configured to:
[0133] Based on the starting address of the target data block, if it is determined that the target data block has been stored in the preset dedicated memory, then the target data block is executed in the preset dedicated memory.
[0134] In one embodiment, the second processing module 6022 is specifically used for:
[0135] Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
[0136] In one embodiment, the third processing module 6023 is specifically used for:
[0137] If the starting address of the target data block is different from the addresses of all program address spaces in the preset relation table, it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block; the preset relation table includes the addresses of program address spaces in the preset dedicated memory.
[0138] In one embodiment, the fourth processing module 6024 is specifically used for:
[0139] Determine the address of the target data block in the program address space;
[0140] Based on the address of the target data block in the program address space, the target data block is stored in a preset dedicated memory using a preset replacement algorithm.
[0141] In one embodiment, the fourth processing module 6024 is specifically used for:
[0142] Restore the context of the target program corresponding to the target data block;
[0143] Based on the context, the target data block is executed in a pre-defined dedicated memory; the target program includes the target data block.
[0144] Applying the embodiments of this application has at least the following beneficial effects:
[0145] Obtain the starting address of the data block to be translated; based on the starting address of the data block to be translated, determine the starting address of the target data block, which is the data block obtained by translating the data block to be translated; if based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block; store the target data block in the preset dedicated memory, and execute the target data block in the preset dedicated memory; in this way, dynamic binary translation is performed based on the preset dedicated memory, which improves the cache hit rate of the target data block (e.g., the target code block) in dynamic binary translation.
[0146] This application also provides an electronic device, the structural schematic diagram of which is shown below. Figure 7 As shown, Figure 7The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.
[0147] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.
[0148] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0149] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.
[0150] The memory 4003 stores computer programs that execute embodiments of this application, and its execution is controlled by the processor 4001. The processor 4001 executes the computer programs stored in the memory 4003 to implement the steps shown in the foregoing method embodiments.
[0151] Electronic devices include, but are not limited to, servers and terminals.
[0152] Applying the embodiments of this application has at least the following beneficial effects:
[0153] Obtain the starting address of the data block to be translated; based on the starting address of the data block to be translated, determine the starting address of the target data block, which is the data block obtained by translating the data block to be translated; if based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block; store the target data block in the preset dedicated memory, and execute the target data block in the preset dedicated memory; in this way, dynamic binary translation is performed based on the preset dedicated memory, which improves the cache hit rate of the target data block (e.g., the target code block) in dynamic binary translation.
[0154] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.
[0155] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.
[0156] Based on the same principles as the methods provided in the embodiments of this application, the embodiments of this application also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in any of the optional embodiments of this application described above.
[0157] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.
[0158] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.
Claims
1. A data processing apparatus, characterized in that, include: A pre-defined dedicated memory is used to store the target data block. The pre-defined dedicated memory includes a temporary storage memory, which is part of the physical processor integrated circuit. The data processing unit includes a first processing module, a second processing module, a third processing module, and a fourth processing module. The first processing module is used to obtain the starting address of the data block to be translated; The second processing module is used to determine the starting address of the target data block based on the starting address of the data block to be translated, wherein the target data block is the data block obtained by translating the data block to be translated; The third processing module is used to translate the data block to be translated into the target data block if it is determined, based on the starting address of the target data block, that the target data block is not stored in the preset dedicated memory. The fourth processing module is used to store the target data block in the preset dedicated memory and execute the target data block in the preset dedicated memory.
2. The apparatus according to claim 1, characterized in that, The third processing module is also used for: Based on the starting address of the target data block, if it is determined that the target data block has been stored in the preset dedicated memory, then the target data block is executed in the preset dedicated memory.
3. The apparatus according to claim 1, characterized in that, The second processing module is specifically used for: Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
4. The apparatus according to any one of claims 1-3, characterized in that, The third processing module is specifically used for: If the starting address of the target data block is different from the addresses of all program address spaces in the preset relationship table, then it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block. The preset relationship table includes the addresses of the program address space in the preset dedicated memory.
5. The apparatus according to any one of claims 1-3, characterized in that, The fourth processing module is specifically used for: Determine the address of the target data block in the program address space; Based on the address of the target data block in the program address space, the target data block is stored in the preset dedicated memory using a preset replacement algorithm.
6. The apparatus according to any one of claims 1-3, characterized in that, The fourth processing module is specifically used for: Restore the context of the target program corresponding to the target data block; Based on the context, the target data block is executed in the preset dedicated memory; the target program includes the target data block.
7. A data processing method, characterized in that, include: Obtain the starting address of the data block to be translated; Based on the starting address of the data block to be translated, the starting address of the target data block is determined, wherein the target data block is the data block obtained by translating the data block to be translated; If, based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then the data block to be translated is translated into the target data block. The preset dedicated memory includes a temporary storage memory, which is part of the physical processor integrated circuit. The target data block is stored in the preset dedicated memory, and the target data block is executed in the preset dedicated memory.
8. The method according to claim 7, characterized in that, Also includes: Based on the starting address of the target data block, if it is determined that the target data block has been stored in the preset dedicated memory, then the target data block is executed in the preset dedicated memory.
9. The method according to claim 7, characterized in that, Determining the starting address of the target data block based on the starting address of the data block to be translated includes: Based on the starting address of the data block to be translated, the starting address of the target data block is determined by means of a control flow graph.
10. The method according to any one of claims 7-9, characterized in that, If, based on the starting address of the target data block, it is determined that the target data block is not stored in the preset dedicated memory, then translating the data block to be translated into the target data block includes: If the starting address of the target data block is different from the addresses of all program address spaces in the preset relationship table, it is determined that the target data block is not stored in the preset dedicated memory, and the data block to be translated is translated into the target data block; the preset relationship table includes the addresses of the program address spaces in the preset dedicated memory.
11. The method according to any one of claims 7-9, characterized in that, The step of storing the target data block in the preset dedicated memory includes: Determine the address of the target data block in the program address space; Based on the address of the target data block in the program address space, the target data block is stored in the preset dedicated memory using a preset replacement algorithm.
12. The method according to any one of claims 7-9, characterized in that, Executing the target data block in the preset dedicated memory includes: Restore the context of the target program corresponding to the target data block; Based on the context, the target data block is executed in the preset dedicated memory; the target program includes the target data block.
13. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 7-12.
14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7-12.
15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7-12.