Memory system and operating method thereof, storage medium, memory controller

Abstract

Embodiments of the present disclosure provide a memory system and an operating method thereof, a storage medium and a memory controller, wherein the memory system comprises at least one nonvolatile memory device and a memory controller coupled with the at least one nonvolatile memory device; wherein the memory device stores a multi-level mapping table for implementing mapping of a logical address to a physical address; the memory controller comprises a cache storing part of the multi-level mapping table; and the memory controller is configured to perform a random read operation on data stored in the memory device; wherein, in response to a random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache for storing different levels of mapping tables is adjusted.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system, its operation method, storage medium, and memory controller. Background Technology

[0002] Memory devices are storage devices used to preserve information in modern information technology. Among them, flash memory, as a typical non-volatile semiconductor memory, has advantages such as high storage density, controllable production costs, suitable erasure speed, and retention characteristics, and is gradually becoming the mainstream product in the storage market.

[0003] Memory systems such as solid-state drives (SSDs) used in personal computers and servers, and universal flash storage (UFS) used in mobile phones and various embedded systems, typically use flash memory as their permanent storage medium. Therefore, how to further improve the data read and write performance of memory systems has become a pressing issue for the industry. Summary of the Invention

[0004] This disclosure provides a memory system, its operation method, a storage medium, and a memory controller.

[0005] In a first aspect, embodiments of this disclosure provide a memory system comprising: at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device; wherein the memory device stores a multi-level mapping table for implementing a mapping from logical addresses to physical addresses; the memory controller includes a cache storing a portion of the multi-level mapping table; the memory controller is configured to perform a random read operation on data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache used to store different levels of mapping tables is adjusted.

[0006] In some embodiments, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table.

[0007] In some embodiments, the memory controller is configured to: in response to the random read range being greater than or equal to a preset value, increase the proportion of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table.

[0008] In some embodiments, the memory controller is configured to: obtain a target mapping table cache hit rate in response to the random read range being greater than or equal to a preset value; detect the current mapping table cache hit rate; and increase the proportion of the capacity in the cache used to store the second-level mapping table to the total capacity used to store the second-level mapping table and the third-level mapping table in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

[0009] In some embodiments, the memory controller is configured to: determine the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; and, based on the difference, determine the amount by which the capacity of the cache used to store the second-level mapping table is increased in this adjustment; wherein the increase is positively correlated with the difference.

[0010] In some embodiments, the memory controller is configured to: stop adjusting the capacity of the cache used to store different levels of mapping tables in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, and the proportion of the current capacity of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaching a preset proportion.

[0011] In some embodiments, the memory controller is configured to determine the target mapping table cache hit rate based on the random read range.

[0012] In some embodiments, the memory controller is configured to: in response to the random read range being less than the preset value, maintain the capacity in the cache for storing the second-level mapping table and the capacity for storing the third-level mapping table unchanged.

[0013] In some embodiments, the memory controller is configured to determine the preset value based on the current capacity of the cache used to store the second-level mapping table, and in conjunction with the mapping rules between the various levels of mapping tables.

[0014] In some embodiments, the memory controller is configured to increase the total capacity of the cache used to store the second-level mapping table and the third-level mapping table in response to the random read range being greater than or equal to a preset value.

[0015] In some embodiments, the multi-level mapping table includes a first-level mapping table and a second-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, and the second-level mapping table stores the physical address of the data. The cache stores a portion of the first-level mapping table and a portion of the second-level mapping table. The memory controller is configured to: in response to the random read range being greater than or equal to a preset value, increase the proportion of the cache capacity used to store the first-level mapping table in the total capacity used to store the first-level mapping table and the second-level mapping table.

[0016] In some embodiments, the memory system includes a DRAM-less memory system, and the cache includes static random access memory.

[0017] In some embodiments, the memory system includes general-purpose flash memory, and the memory device includes NAND flash memory.

[0018] Secondly, embodiments of this disclosure provide an operation method for a memory system, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device; wherein, the memory device stores a multi-level mapping table, the multi-level mapping table being used to implement a mapping from logical addresses to physical addresses; the memory controller includes a cache, the cache storing a portion of the multi-level mapping table; the operation method comprising: performing a random read operation on data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache used to store different levels of mapping tables is adjusted.

[0019] In some embodiments, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table. The step of adjusting the capacity of the cache used to store different levels of mapping tables in response to the random read range corresponding to the random read operation satisfying a preset condition includes: in response to the random read range being greater than or equal to a preset value, increasing the proportion of the capacity of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table.

[0020] In some embodiments, the step of increasing the proportion of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table in response to the random read range being greater than or equal to a preset value specifically includes: obtaining the target mapping table cache hit rate in response to the random read range being greater than or equal to the preset value; detecting the current mapping table cache hit rate; and increasing the proportion of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

[0021] In some embodiments, the method further includes: determining the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; and determining, based on the difference, the increase in the capacity of the cache used to store the second-level mapping table in this adjustment; wherein the increase is positively correlated with the difference.

[0022] In some embodiments, the method further includes: stopping the adjustment of the capacity of the cache used to store different levels of mapping tables when the current mapping table cache hit rate is less than the target mapping table cache hit rate, and the proportion of the current capacity of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaches a preset proportion.

[0023] Thirdly, embodiments of this disclosure provide a storage medium storing executable instructions, which, when executed by a processor, implement the steps of any of the methods described in the above embodiments.

[0024] Fourthly, embodiments of this disclosure provide a memory controller, including: a cache and a control unit, wherein the cache is configured to: store a multi-level mapping table of a portion of a non-volatile memory device; the multi-level mapping table is configured to implement a mapping from logical addresses to physical addresses; the control unit is configured to: perform random read operations on data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache used to store different levels of mapping tables is adjusted.

[0025] In some embodiments, the memory controller further includes: a flash translation layer connected to the control unit and the cache; the flash translation layer is configured to translate the logical address into a corresponding physical address according to the mapping information in the multi-level mapping table stored in the cache.

[0026] In some embodiments, the control unit is further configured to: receive instructions from the host to perform read, write, and erase operations on the memory device; the cache is further configured to temporarily store data transferred between the host and the memory device; the memory controller further includes: an encoder / decoder for encoding and decoding the data transferred between the host and the memory device.

[0027] This disclosure also provides another memory system, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device; wherein the memory device stores a multi-level mapping table for implementing a mapping from logical addresses to physical addresses; the memory controller includes a cache storing a portion of the multi-level mapping table; the memory controller is configured to perform a random read operation on data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the values ​​of different levels of the mapping table loaded from the memory device into the cache at one time are adjusted.

[0028] In the memory system provided in this embodiment, the memory device stores a multi-level mapping table. The cache of the memory controller is used to load a portion of the multi-level mapping table. When the random read range meets preset conditions, the memory controller adjusts the capacity of the cache used to store different levels of mapping tables. Thus, on the one hand, during large-scale random read operations, the memory controller can increase the capacity of the cache used to store at least one level of mapping table to improve the mapping table cache hit rate, thereby reducing the number of times the mapping table is updated from the memory device to the cache, reducing the time overhead of looking up the corresponding mapping table, and improving the performance of the memory system for large-scale random reads. On the other hand, dynamically adjusting the capacity of the cache used to store different levels of mapping tables can improve cache utilization, have less impact on other task scheduling, and reduce problems such as cache resource contention. Attached Figure Description

[0029] Figure 1 A schematic diagram of an exemplary system having a memory device provided in an embodiment of this disclosure;

[0030] Figure 2a A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0031] Figure 2b A schematic diagram of an SSD provided in an embodiment of this disclosure;

[0032] Figure 3 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0033] Figure 4 A schematic diagram of a multi-level mapping table provided in an embodiment of this disclosure;

[0034] Figure 5 A schematic diagram of various levels of mapping tables loaded in a cache, provided as an embodiment of this disclosure;

[0035] Figure 6 A schematic diagram of another memory system provided in an embodiment of this disclosure;

[0036] Figure 7 A flowchart illustrating the steps of adjusting the capacity of each level of the mapping table in the cache by a memory controller, as provided in this embodiment of the disclosure;

[0037] Figure 8 This is a schematic diagram of a negative feedback dynamic adjustment mechanism for the hit rate of a mapping table cache, provided in an embodiment of this disclosure. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0045] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0046] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0047] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0048] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with a host (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0049] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a general-purpose flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0050] In some embodiments, such as Figure 3 As shown, the memory system 300 uses a non-volatile memory device 310 (such as NAND flash memory) to store user data and the corresponding logical-to-physical mapping table (L2P mapping table). During data reading, a portion of the L2P mapping table is loaded into the cache 321 of the memory controller 320. The memory controller 320 uses the logical address provided by the host 400 and searches for the physical address in the memory device 310 using the portion of the L2P mapping table loaded in the cache 321. Then, it uses the found physical address to read the corresponding data from the memory device 310. For example, the cache 321 in the memory controller 320 may include, but is not limited to, static random access memory (SRAM) and dynamic random access memory (DRAM).

[0051] Several methods can be used to store and maintain L2P mapping tables. One method is single-level direct L2P mapping, which can contain mapping information for data throughout the entire memory device. Therefore, single-level direct page mapping schemes require a large amount of storage space (on the order of 1-2 MB L2P mapping table for 1 GB of data), which is challenging for high-capacity memory devices. Another method for storing and maintaining L2P mapping tables is a multi-level mapping scheme; here, a three-level mapping scheme is used as an example. Figure 4 As shown, the first-level mapping table stores the physical addresses of the second-level mapping table, and each entry in the first-level mapping table points to a second-level mapping table. The second-level mapping table stores the physical addresses of the third-level mapping table, and each entry in the second-level mapping table points to a third-level mapping table. The third-level mapping table stores the physical addresses of the data (such as physical block numbers, physical page numbers, etc.), and each entry in the third-level mapping table points to a physical block or page in the memory device. For example, for a memory device with a data storage capacity of 128GB, the size of its corresponding third-level mapping table is 128MB, the size of its corresponding second-level mapping table is 128KB, and the size of its corresponding first-level mapping table is 128 bytes.

[0052] The Flash Translation Layer (FTL) 322, located within the memory controller 320, is used to translate logical addresses into physical addresses. Due to the limited capacity of the cache 321 in the memory controller 320, in a multi-level mapping scheme, it is impossible to load all multi-level mapping tables into the cache 321. Therefore, the first-level mapping table can be entirely loaded into the cache 321, meaning it resides permanently in the cache 321. The second-level and third-level mapping tables can be partially loaded into the cache 321. Understandably, if the Flash Translation Layer 322 cannot obtain the necessary mapping information from the current cache 321, it needs to update the second-level and / or third-level mapping tables stored in the cache 321. This means reloading a portion of the second-level and / or third-level mapping tables from the memory device 310 into the cache 321 until the required mapping information is found. It is worth noting that for sequential reads, the mapping information is continuous, so the sequential read performance of the multi-level mapping scheme is good. However, for random reads, the mapping information is scattered. This may require multiple additional read operations on the memory device 310 to update the second-level and / or third-level mapping tables in the cache 321 to find the mapping information needed for random reads. Therefore, the random read performance of the multi-level mapping scheme is relatively poor. Here, the read latency of the cache 321 can be on the order of a few microseconds, while the read latency of the memory device 310 can be on the order of a larger order of magnitude, such as tens of microseconds.

[0053] In some embodiments, the memory system 300 may be a DRAM-less memory system, i.e., it does not contain DRAM. For example, the memory system 300 may be a UFS, and the cache 321 in the memory system 300 may be SRAM. A fixed capacity in the SRAM may be allocated to store a multi-level mapping table using a static allocation method, while the remaining SRAM capacity may be used as cache space for other task scheduling of the firmware (FW). Here, the firmware may be stored in the storage medium of the memory device 310 and may be executed by the control unit 323 (such as a processor) in the memory controller 320.

[0054] Taking a memory device with a storage capacity of 128GB as an example, such as Figure 5As shown, the total capacity of the SRAM in the memory controller can be 2MB. The SRAM can store 128 bytes of the first-level mapping table (i.e., the entire first-level mapping table in the memory device), 8KB of the second-level mapping table, and 256KB of the third-level mapping table. This ensures that random read operations within an 8GB range will not update the second-level mapping table stored in the SRAM. To ensure that random read operations within a 1GB range do not update the third-level mapping table stored in the SRAM, i.e., to achieve a 100% cache hit rate, the capacity of the SRAM used to store the third-level mapping table can be expanded from 256KB to 1024KB. However, with SRAM capacities of 8KB for the second-level mapping table and 1024KB for the third-level mapping table, large-scale random read operations will result in additional table lookups, severely degrading the performance of large-scale random reads. Taking 1000 random reads within a 128G range (i.e., full disk random read) as an example, as shown in Table 1, the ratio of random read commands, the number of reads by loading the second-level mapping table, and the number of reads by loading the third-level mapping table is almost 1:1:1. 1000 random read commands will result in a total of 2931 reads, and these extra 1931 reads will seriously affect the performance of the memory system.

[0055] Understandably, the memory controller has limited cache space. For large-scale random reads, increasing the cache space of the third-level mapping table would reduce the efficiency of the firmware when performing other tasks. If the cache space of the second-level and third-level mapping tables is not increased, the number of additional loading operations of the mapping table will increase, resulting in increased random read time overhead and poor random read performance.

[0056] Table 1

[0057]

[0058] refer to Figure 3 This disclosure provides a memory system 300, comprising: at least one non-volatile memory device 310 and a memory controller 320 coupled to the at least one non-volatile memory device 310; wherein the memory device 310 stores a multi-level mapping table for implementing a mapping from logical addresses to physical addresses; the memory controller 320 includes a cache 321 storing a portion of the multi-level mapping table; the memory controller 320 is configured to perform random read operations on data stored in the memory device 310; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache 321 used to store different levels of mapping tables is adjusted.

[0059] In this embodiment, the memory controller 320 can be connected to at least one memory device 310. The memory controller 320 communicates with a host 400 via a host interface 301. The host 400 can send commands and / or data through the host interface 301 to request the memory controller 320 to perform read, program, and erase operations on the memory device 310. The memory controller 320 can be configured to retrieve data from one or more memory devices 310 and send the data to the host 400 via a data bus. The memory device 310 may include one or more NAND flash memory cell arrays, and the storage medium of the memory device 310 may store executable instructions, such as firmware in the above embodiments. The memory controller 320 may include one or more caches 321, which may be caches (such as SRAM). The caches 321 can be used to store any suitable information, including L2P mapping tables, software code, commands, firmware, etc., to facilitate the memory controller 320 in quickly executing various commands and operations. In some embodiments, such as Figure 6 As shown, memory device 310 can be flash memory, and cache 321 can be SRAM. Memory controller 320 includes a processor connected to host 400 via a host interface and to memory device 310 via a flash memory interface. The processor is also connected to cache 321 and can obtain L2P mapping information from cache 321.

[0060] The memory device 310 stores a multi-level L2P mapping table, which reflects the mapping from logical addresses to physical addresses corresponding to the data stored in the memory device 310. During data reading, a portion of the multi-level mapping table is loaded from the memory device 310 into the cache 321. The memory controller 320 uses the logical address provided by the host 400 and searches for the physical address in the memory device 310 using the portion of the L2P mapping table loaded in the cache 321, and then uses the found physical address to read the corresponding data from the memory device 310.

[0061] For example, the memory controller 320 is configured to perform random read operations on data stored in the memory device 310 in response to a read command from the host 400. The memory controller 320 uses firmware stored in the memory device 310 to detect the random read range. If the random read range meets preset conditions (such as the random read range being greater than a certain value), the memory controller 320 adjusts the capacity of the cache 321 used to store the mapping tables at various levels.

[0062] Taking a three-level mapping scheme as an example, one can either increase the capacity of the second-level mapping table and decrease the capacity of the third-level mapping table (adjusting the ratio of the capacities of the second-level and third-level mapping tables) while keeping the total capacity of the second-level and third-level mapping tables unchanged; or one can increase the capacity of both the second-level and third-level mapping tables simultaneously, or increase the capacity of only one of the second-level and third-level mapping tables (increasing the total capacity of the second-level and third-level mapping tables). If the random access range does not meet the preset conditions, the memory controller 320 does not adjust the capacity of the cache 321 used to store the mapping tables at each level.

[0063] The memory controller 320 sends a mapping table load instruction to receive an adjusted multi-level mapping table of corresponding capacity from the memory device 310 and load it into the cache 321. This load instruction may contain capacity information for each level of the adjusted mapping table. The larger the capacity of the cache 321 used to store each level of the mapping table, the more mapping information can be retrieved from the memory device 310 in a single load. Subsequently, the memory controller 320 can search for the corresponding physical address of the memory device 310 based on the logical address provided by the host 400 and through the partially loaded multi-level mapping table in the cache 321, and then use the searched physical address to read the corresponding data from the memory device 310.

[0064] It should be noted that the embodiments disclosed herein may also include mapping schemes with three or more levels, such as four or more levels, without limitation. It is understood that when the memory system includes a mapping scheme with four or more levels, the specific adjustment objects need to be adjusted according to the actual situation. For example, when the memory system includes four levels, the capacities of the second-level, third-level, and fourth-level mapping tables can be adjusted, and the capacities of the third-level and fourth-level mapping tables can also be adjusted. The specific adjustment scheme can be adjusted according to the mapping strategy.

[0065] In some embodiments, when the random read range is less than a certain value, the memory controller 320 may also reduce the capacity of the cache 321 used to store different levels of mapping tables (e.g., reduce the capacity of the second-level mapping table and / or the third-level mapping table) to allocate additional cache capacity for performing other firmware tasks, thereby improving cache utilization. It is understood that in scenarios such as sequential read operations or small-range random read operations, the memory controller 320 may also choose not to adjust the capacity of the cache 321 used to store each level of mapping tables.

[0066] Thus, on the one hand, when performing large-scale random read operations, the memory controller 320 can increase the capacity of the cache 321 used to store at least one level of the mapping table (such as increasing the capacity of the second level mapping table) to improve the mapping table cache hit rate, thereby reducing the number of times the mapping table is updated from the memory device 310 to the cache 321, reducing the time overhead of looking up the corresponding mapping table, and improving the performance of the large-scale random read of the memory system 300. On the other hand, dynamically adjusting the capacity of the cache 321 used to store different levels of mapping tables can improve the utilization of the cache 321, with less impact on the scheduling of other tasks, and reduce problems such as cache resource contention.

[0067] In some embodiments, the memory system 300 includes a DRAM-less memory system, and the cache 321 includes static random access memory.

[0068] In this embodiment of the disclosure, the memory system 300 may not include DRAM, i.e., a DRAM-less memory system. For example, the cache 321 in the memory controller 320 may use SRAM instead of DRAM. SRAM has higher access speed and lower power consumption than DRAM, which is beneficial to improving the performance of the memory system 300.

[0069] In some embodiments, the memory system 300 includes general-purpose flash memory, and the memory device 310 includes NAND flash memory.

[0070] In this embodiment, the memory system 300 may be a UFS (Unique Memory System), and the memory device 310 may be a NAND flash memory. UFS features small size, high performance, and low power consumption, making it suitable for use in embedded and mobile devices. Compared to NOR flash memory, NAND flash memory has higher storage density, higher erasure cycles, and lower cost per bit. In some embodiments, the memory system 300 may also be an SSD, SD card, CF card, etc.

[0071] In some embodiments, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, ..., an Nth-level mapping table, where N is an integer greater than or equal to three. The previous-level mapping table stores the physical address of the next-level mapping table, and the last-level mapping table stores the physical address of the data. The cache stores at least all of the first M-level mapping tables (M greater than or equal to 1 and less than N) and a portion of the mapping tables for each of the subsequent NM-level mapping tables. In some specific embodiments, such as... Figure 4As shown, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table.

[0072] In this embodiment of the disclosure, since the capacity occupied by the first-level mapping table is small (e.g., the size of the first-level mapping table corresponding to a memory device with a storage capacity of 128G is only 128Byte), all the first-level mapping tables in the memory device can be loaded into the cache, while the second-level and third-level mapping tables in the memory device are partially loaded into the cache to reduce problems such as competition for cache resources.

[0073] For ease of understanding, the following multi-level mapping tables will be described using the three-level mapping table mentioned above as an example. In some embodiments, the memory controller 320 is configured to: in response to the random read range being greater than or equal to a preset value, increase the proportion of the capacity in the cache 321 used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table.

[0074] In this embodiment, the memory controller 320 can use firmware stored in the memory device 310 to detect the random read range, and when the random read range is greater than a preset value, increase the proportion of the capacity in the cache 321 used to store the second-level mapping table in the total capacity used to store the second-level and third-level mapping tables. That is, the memory controller 320 may not increase the total capacity in the cache 321 used to store the second-level and third-level mapping tables, but instead increase the capacity of the second-level mapping table and decrease the capacity of the third-level mapping table while keeping the total capacity of the second-level and third-level mapping tables in the cache 321 unchanged.

[0075] For example, as shown in Table 2, taking 1000 random reads within a 128G range (the storage capacity of the memory device is 128G, i.e., full disk random read) as an example, compared to the embodiment corresponding to Table 1, the memory controller reduces the capacity of the third-level mapping table in the cache from 1024K to 904K, and allocates the 120K reduction in the capacity of the third-level mapping table in the cache to the second-level mapping table. That is, the capacity of the second-level mapping table in the cache increases from the original 8K to 128K. In this way, it can be ensured that random reads within the 128G range do not update the second-level mapping table loaded in the cache, that is, the number of reads that additionally load the second-level mapping table is 0, while the increase in the number of reads that additionally load the third-level mapping table is small. Ultimately, the total number of reads is reduced from 2931 to 1994, which significantly improves the performance of random reads in the memory system.

[0076] Table 2

[0077]

[0078] In some embodiments, the memory controller 320 is configured to: obtain a target mapping table cache hit rate in response to the random read range being greater than or equal to a preset value; detect the current mapping table cache hit rate; and increase the proportion of the capacity in the cache 321 used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

[0079] In some embodiments, the memory controller 320 is configured to determine the target mapping table cache hit rate based on the random read range.

[0080] In some embodiments, the memory controller 320 is configured to: in response to the random read range being less than the preset value, maintain the capacity of the cache 321 for storing the second-level mapping table and the capacity for storing the third-level mapping table unchanged.

[0081] In this embodiment of the disclosure, reference is made to Figure 7The memory controller 320 can detect the random access range using firmware stored in the memory device 310. When the random access range is greater than or equal to a preset value, the memory controller 320 can calculate the target mapping table cache hit rate based on the random access range and the firmware. The memory controller 320 can detect the current mapping table cache hit rate. If the current mapping table cache hit rate is less than the target mapping table cache hit rate, the memory controller 320 adjusts the capacity in cache 321 used for storing the second-level mapping table and the capacity used for storing the third-level mapping table. If the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate, the memory controller 320 stops adjusting the capacity in cache 321 used for storing different levels of mapping tables. Furthermore, if the random access range is less than the preset value, the memory controller 320 can keep the capacity in cache 321 used for storing the second-level and third-level mapping tables unchanged.

[0082] In this way, the memory controller 320 can adjust the capacity of the cache 321 used to store the second-level mapping table and the capacity used to store the third-level mapping table multiple times until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate. By dynamically adjusting the capacity of different levels of mapping tables in the cache 321 multiple times, the target mapping table cache hit rate can be precisely achieved without exceeding it by too much. This ensures that limited cache resources are fully utilized, improving the performance of the memory system for large-scale random access while reducing contention for cache resources.

[0083] In some embodiments, the memory controller 320 is configured to increase the total capacity of the cache 321 for storing the second-level mapping table and the third-level mapping table in response to the random read range being greater than or equal to a preset value.

[0084] In this embodiment of the disclosure, when the random read range is greater than or equal to a preset value, the memory controller 320 adjusts the capacity of the cache 321 for storing the second-level mapping table and the capacity for storing the third-level mapping table, including but not limited to the following methods: one is that the memory controller 320 increases the capacity of the second-level mapping table and decreases the capacity of the third-level mapping table while keeping the total capacity of the second-level and third-level mapping tables in the cache 321 unchanged; another is that the memory controller 320 increases the capacity of at least one of the second-level and third-level mapping tables in the cache 321, so as to increase the total capacity of the second-level and third-level mapping tables. Increasing the total capacity of the cache 321 for storing the second-level and third-level mapping tables can also be achieved by increasing the capacity of one of the second-level and third-level mapping tables and decreasing the capacity of the other.

[0085] Understandably, increasing the total capacity of cache 321 used to store the second-level and third-level mapping tables can further improve the mapping table cache hit rate, thereby improving the performance of the memory system under a wider range of random reads.

[0086] In some embodiments, the memory controller 320 is configured to: determine the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; and, based on the difference, determine the amount by which the capacity of the cache 321 used to store the second-level mapping table is increased in this adjustment; wherein the increase is positively correlated with the difference.

[0087] In this embodiment of the present disclosure, the memory controller 320 can calculate the target mapping table cache hit rate based on the random read range and using the firmware stored in the memory device 310, thereby calculating the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; then, the memory controller 320 can determine the increase in the capacity of the cache 321 used to store the second-level mapping table in this adjustment based on the difference, and the larger the difference, the larger the increase in the capacity of the second-level mapping table in this adjustment; the smaller the difference, the smaller the increase in the capacity of the second-level mapping table in this adjustment.

[0088] Thus, when the difference is large, the increase in this adjustment is large (i.e., the single adjustment range is large), thereby reducing the number of adjustments to the multi-level mapping table capacity in cache 321 to achieve the target mapping table cache hit rate, accelerating the speed of mapping table cache capacity adjustment, and improving the performance of the memory system; when the difference is small, the increase in this adjustment is small, so as to accurately achieve the target mapping table cache hit rate, thereby making full use of the limited cache resources.

[0089] In some embodiments, the memory controller 320 is configured to: stop adjusting the capacity of the cache 321 used to store different levels of mapping tables in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, and the proportion of the current capacity of the cache 321 used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaching a preset proportion.

[0090] In this embodiment, the memory controller 320 may further set a preset ratio, which is a threshold value representing the proportion of the capacity of the second-level mapping table in the current cache 321 to the total capacity used to store the second-level and third-level mapping tables. If the current mapping table cache hit rate is still less than the target mapping table cache hit rate, but the proportion of the second-level mapping table capacity in the cache 321 reaches the preset ratio, the memory controller 320 may stop adjusting the capacity of the cache 321 used to store different levels of mapping tables. This prevents the capacity of the second-level mapping table in the cache 321 from becoming too large, thus preventing it from crowding out the cache resources required for the third-level mapping table. The preset ratio can be determined based on the proportional relationship between the capacity of all second-level mapping tables and the capacity of all third-level mapping tables in the memory device 310.

[0091] like Figure 8 As shown, the specific implementation of each embodiment in this disclosure is based on a negative feedback dynamic adjustment mechanism of the current mapping table cache hit rate. The input is the target mapping table cache hit rate Yin of the second-level and third-level mapping tables, and the output is the current mapping table cache hit rate Y_out of the second-level and third-level mapping tables, where X represents the comparison node between Y_In and Y_out. Based on the current dynamic L2P mapping table caching algorithm, according to the following formula: Y_out = K(Y_In - Y_out), where K is an adjustment coefficient, the current mapping table cache hit rate can be dynamically adjusted to achieve the target mapping table cache hit rate, thereby improving the performance of the memory system for large-scale random reads.

[0092] In some embodiments, the memory controller 320 is configured to determine the preset value based on the capacity of the cache 321 currently used to store the second-level mapping table, and in conjunction with the mapping rules between the various levels of mapping tables.

[0093] In this embodiment, the memory controller 320 can utilize the firmware stored in the memory device 310 and, based on the capacity of the current cache 321 used to store the second-level mapping table and the mapping rules between each level of mapping table, calculate a preset value corresponding to the random read range. Here, the mapping rules can refer to the proportional relationship between adjacent level mapping tables and between the data stored in the memory device and the lowest level mapping table.

[0094] For example, taking a three-level mapping scheme, the mapping rule can be that the size of the third-level mapping table is 1 / 1024 of the data storage capacity in the corresponding memory device, the size of the second-level mapping table is 1 / 1024 of the size of the corresponding third-level mapping table, and the size of the first-level mapping table is 1 / 1024 of the size of the corresponding second-level mapping table. That is, if the capacity of the cache 321 used to store the second-level mapping table is 8K, then random reads within an 8G range will not update the second-level mapping table in the cache 321. In this case, the preset value can be set to 8G. When the random read range exceeds 8G, additional reads will occur to reload the second-level mapping table from the memory device. At this point, it is necessary to adjust the capacity of the cache 321 used to store the multi-level mapping tables to improve the random read performance of the memory system.

[0095] In some embodiments, the multi-level mapping table includes a first-level mapping table and a second-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, and the second-level mapping table stores the physical address of the data. The cache 321 stores a portion of the first-level mapping table and a portion of the second-level mapping table. The memory controller 320 is configured to increase the proportion of the capacity of the cache 321 used to store the first-level mapping table in the total capacity used to store the first-level mapping table and the second-level mapping table in response to the random read range being greater than or equal to a preset value.

[0096] In this embodiment, the multi-level mapping table can also be two-level, that is, it includes only a first-level mapping table and a second-level mapping table. Thus, when the random read range is greater than or equal to a preset value, the memory controller 320 can increase the proportion of the capacity in the cache 321 used to store the first-level mapping table to the total capacity used to store the first-level and second-level mapping tables, thereby improving the mapping table cache hit rate. This reduces the number of times the mapping table is updated from the memory device 310 to the cache 321, reduces the time overhead of looking up the corresponding mapping table, and improves the performance of the memory system 300 for large-range random reads.

[0097] refer to Figure 3 This disclosure provides a memory controller 320, including a cache 321 and a control unit 323. The cache 321 is configured to store a portion of a multi-level mapping table in a non-volatile memory device 310. The multi-level mapping table is configured to implement a mapping from logical addresses to physical addresses. The control unit 323 is configured to perform random read operations on data stored in the memory device 310. In response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache 321 used to store different levels of mapping tables is adjusted.

[0098] In some embodiments, the memory controller 320 further includes a flash memory translation layer 322, which connects the control unit 323 and the cache 321; the flash memory translation layer 322 is configured to translate the logical address into a corresponding physical address according to the mapping information in the multi-level mapping table stored in the cache 321.

[0099] In some embodiments, the control unit 323 is further configured to receive instructions from the host 400 to perform read, write, and erase operations on the memory device 310; the cache 321 is further configured to temporarily store data transferred between the host 400 and the memory device 310; the memory controller 320 further includes an encoder / decoder 324 for encoding and decoding data transferred between the host 400 and the memory device 310.

[0100] In this embodiment of the disclosure, the memory controller 320 may include a cache 321, a flash memory conversion layer 322, a control unit 323, and an encoder / decoder 324.

[0101] The memory controller 320 may include one or more caches 321, which may be high-speed caches (such as SRAM). Caches 321 may be used to store any suitable information, including L2P mapping tables, software code, commands, firmware, etc., so that the memory controller 320 can quickly execute various commands and operations. The flash translation layer 322 may be implemented using the allocation section of the memory controller 320 circuitry and control software, and is used to translate logical addresses into physical addresses.

[0102] The control unit 323 can be any suitable integrated circuit (e.g., one or more processors) configured to receive instructions from the host 400 via the host interface 301 and transmit commands and / or data to one or more memory devices 310 via the interface 302 to perform read, program, and erase operations on the memory devices 310. For example, the control unit 323 receives a request for access to flash memory from the host 400. The control unit 323 can also be configured to communicate with and control other components of the memory controller 320. For example, the control unit 323 can command the flash translation layer 322 to scan the cache 321 to obtain mapping information and send / receive address mapping information from the flash translation layer 322. The control unit 323 can also communicate with the encoder / decoder 324 and other suitable components of the memory controller 320.

[0103] The encoder / decoder 324 can provide encoding and decoding of data processed by the memory controller 320. The encoder / decoder 324 can also generate and store error correction codes (ECC) and metadata, and can be used to detect and correct errors in the data stored in the memory device.

[0104] In some embodiments, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache 321 stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table. The control unit 323 is configured to increase the proportion of the capacity of the cache 321 used to store the second-level mapping table to the total capacity used to store the second-level mapping table and the third-level mapping table when the random read range is greater than or equal to a preset value.

[0105] In some embodiments, the control unit 323 is configured to: when the random read range is greater than or equal to a preset value, obtain the target mapping table cache hit rate; detect the current mapping table cache hit rate; when the current mapping table cache hit rate is less than the target mapping table cache hit rate, increase the proportion of the capacity of the cache 321 used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table, until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

[0106] In some embodiments, the control unit 323 is configured to: determine the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; and, based on the difference, determine the increase in the capacity of the cache 321 used to store the second-level mapping table in this adjustment; wherein the increase is positively correlated with the difference.

[0107] In some embodiments, the control unit 323 is configured to: stop adjusting the capacity of the cache 321 used to store different levels of mapping tables when the current mapping table cache hit rate is less than the target mapping table cache hit rate, and when the proportion of the capacity of the cache 321 currently used to store the second level mapping table in the total capacity used to store the second level mapping table and the third level mapping table reaches a preset proportion.

[0108] In some embodiments, the control unit 323 is configured to determine the target mapping table cache hit rate based on the random read range.

[0109] In some embodiments, the control unit 323 is configured to: when the random read range is less than the preset value, keep the capacity of the cache 321 for storing the second-level mapping table and the capacity for storing the third-level mapping table unchanged.

[0110] In some embodiments, the control unit 323 is configured to determine the preset value based on the capacity of the cache 321 for storing the second-level mapping table and the mapping rules between the various levels of mapping tables.

[0111] In some embodiments, the control unit 323 is configured to increase the total capacity of the cache 321 for storing the second-level mapping table and the third-level mapping table when the random read range is greater than or equal to a preset value.

[0112] refer to Figure 3 This disclosure also provides another memory system 300, comprising: at least one non-volatile memory device 310 and a memory controller 320 coupled to the at least one non-volatile memory device 310; wherein the memory device 310 stores a multi-level mapping table for implementing a mapping from logical addresses to physical addresses; the memory controller 320 includes a cache 321 storing a portion of the multi-level mapping table; the memory controller 320 is configured to perform random read operations on data stored in the memory device 310; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the magnitude of different levels of the mapping table loaded from the memory device 310 to the cache 321 at one time is adjusted.

[0113] In this embodiment of the disclosure, the memory controller 320 is configured to issue a mapping table loading instruction when the random read range meets a preset condition (such as the random read range being greater than a certain value), and adjust the capacity of different levels of mapping tables loaded from the memory device 310 to the cache 321 in one go. Here, "one load" refers to one mapping table read operation.

[0114] Taking a three-level mapping scheme as an example, the memory controller 320 can increase the proportion of the second-level mapping table's capacity in the total capacity of the second and third-level mapping tables during a single mapping table load, without increasing the total capacity of the second and third-level mapping tables during a single load. In this way, the capacity in cache 321 used to store the second-level mapping table increases, but the total capacity in cache 321 used to store multi-level mapping tables remains unchanged. This improves the mapping table cache hit rate, reduces the number of additional loadings of mapping tables from memory device 310 to cache 321, reduces the time overhead of looking up the corresponding mapping table, and improves the performance of the memory system 300 for large-scale random reads. Furthermore, dynamically adjusting the capacity of different levels of mapping tables loaded from memory device 310 to cache 321 in a single load can improve the utilization of cache 321 with minimal impact on other task scheduling and reduce problems such as cache resource contention.

[0115] Understandably, if at least one random read operation in a series of random read operations satisfies a preset condition, the memory controller 320 adjusts the values ​​of different levels of mapping tables loaded from the memory device 310 to the cache 321 at one time. Therefore, the capacity of the second-level mapping table loaded in at least one random read operation is different from the capacity of the second-level mapping table loaded in other random read operations (it could also be that the capacity of the third-level mapping table loaded in at least one random read operation is different from the capacity of other operations).

[0116] In some embodiments, the memory controller 320 can load the multi-level mapping table corresponding to the random read operation into the cache 321 within a preset number of reads. That is, it is not limited to loading the multi-level mapping table at once to achieve a 100% mapping table cache hit rate, but there are no reads beyond the preset number of reads used to load the L2P mapping table. Here, the memory controller 320 can calculate the preset number of reads through firmware based on the target mapping table cache hit rate, and the target mapping table cache hit rate is less than 100%.

[0117] This disclosure also provides an operation method for a memory system, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device; wherein, the memory device stores a multi-level mapping table, the multi-level mapping table being used to implement the mapping from logical addresses to physical addresses; the memory controller includes a cache, the cache storing a portion of the multi-level mapping table; the operation method comprising: performing a random read operation on data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation satisfying a preset condition, the capacity of the cache used to store different levels of mapping tables is adjusted.

[0118] In some embodiments, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table. The step of adjusting the capacity of the cache used to store different levels of mapping tables in response to the random read range corresponding to the random read operation satisfying a preset condition includes: in response to the random read range being greater than or equal to a preset value, increasing the proportion of the capacity of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table.

[0119] In some embodiments, the step of increasing the proportion of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table in response to the random read range being greater than or equal to a preset value specifically includes: obtaining the target mapping table cache hit rate in response to the random read range being greater than or equal to the preset value; detecting the current mapping table cache hit rate; and increasing the proportion of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

[0120] Specifically, refer to Figure 7 The method of operating the memory system provided in this disclosure may include the following steps:

[0121] S101, Firmware detects the random read range of random read operations;

[0122] S102. Determine whether the random reading range is greater than or equal to a preset value. If so, proceed to step S103.

[0123] S103. Obtain the target mapping table cache hit rate;

[0124] S104. Detect the current mapping table cache hit rate and determine whether the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate. Otherwise, proceed to step S105.

[0125] S105. Adjust the capacity of the cache used to store different levels of mapping tables, and then re-execute step S104;

[0126] For a detailed understanding of the operation of the memory system, please refer to the specific implementation methods in the above embodiments; they will not be repeated here.

[0127] In some embodiments, the method further includes: determining the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; and determining, based on the difference, the increase in the capacity of the cache used to store the second-level mapping table in this adjustment; wherein the increase is positively correlated with the difference.

[0128] In some embodiments, the method further includes: stopping the adjustment of the capacity of the cache used to store different levels of mapping tables when the current mapping table cache hit rate is less than the target mapping table cache hit rate, and the proportion of the current capacity of the cache used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaches a preset proportion.

[0129] This disclosure provides a storage medium storing executable instructions, which, when executed by a processor, implement the steps of any of the methods described in the above embodiments.

[0130] In this embodiment, the storage medium may be a NAND flash memory in the memory device 310, and the storage medium stores executable instructions, which may be the firmware in the above embodiments. Thus, the control unit 323 in the memory controller 320, including a processor, can execute the executable instructions in the storage medium to implement the steps in any of the methods described above.

[0131] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0132] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory system, comprising: At least one non-volatile memory device and a memory controller coupled to said at least one non-volatile memory device; wherein, The memory device stores a multi-level mapping table, which is used to implement the mapping from logical address to physical address; The memory controller includes a cache that stores a portion of the multi-level mapping table; The memory controller is configured to: A random read operation is performed on the data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation being greater than or equal to a preset value, the target mapping table cache hit rate corresponding to the random read range is obtained, and the current mapping table cache hit rate is detected; and, in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, the capacity of the cache used to store different levels of mapping tables is adjusted.

2. The memory system according to claim 1, wherein, The multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table.

3. The memory system according to claim 2, wherein, The memory controller is configured to: In response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, the proportion of the cache capacity used to store the second-level mapping table to the total capacity used to store the second-level mapping table and the third-level mapping table is increased until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

4. The memory system according to claim 3, wherein, The memory controller is configured to: Determine the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; Based on the difference, determine the increase in the capacity of the cache used to store the second-level mapping table in this adjustment; wherein the increase is positively correlated with the difference.

5. The memory system according to claim 3, wherein, The memory controller is configured to: In response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, and the proportion of the current cache capacity used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaching a preset proportion, the adjustment of the cache capacity used to store different levels of mapping tables is stopped.

6. The memory system according to claim 3, wherein, The memory controller is configured to: The target mapping table cache hit rate is determined based on the random read range.

7. The memory system according to claim 3, wherein, The memory controller is configured to: In response to the random read range being less than the preset value, the capacity of the cache used to store the second-level mapping table and the capacity used to store the third-level mapping table remain unchanged.

8. The memory system according to claim 3, wherein, The memory controller is configured to: The preset value is determined based on the capacity of the cache currently used to store the second-level mapping table, combined with the mapping rules between the various levels of mapping tables.

9. The memory system according to claim 2, wherein, The memory controller is configured to: In response to the random read range being greater than or equal to a preset value, the total capacity of the cache used to store the second-level mapping table and the third-level mapping table is increased.

10. The memory system according to claim 1, wherein, The multi-level mapping table includes a first-level mapping table and a second-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, and the second-level mapping table stores the physical address of the data. The cache stores a portion of the first-level mapping table and a portion of the second-level mapping table. The memory controller is configured to: In response to the random read range being greater than or equal to a preset value, the proportion of the capacity in the cache used to store the first-level mapping table to the total capacity used to store the first-level mapping table and the second-level mapping table is increased.

11. The memory system according to claim 1, wherein, The memory system includes a DRAM-less memory system, and the cache includes static random access memory.

12. The memory system according to claim 1, wherein, The memory system includes general-purpose flash memory, and the memory device includes NAND flash memory.

13. A method of operating a memory system, wherein, The memory system includes: at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device; the memory device stores a multi-level mapping table, which is used to implement the mapping from logical addresses to physical addresses; the memory controller includes a cache, which stores a portion of the multi-level mapping table; the operation method includes: A random read operation is performed on the data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation being greater than or equal to a preset value, the target mapping table cache hit rate corresponding to the random read range is obtained, and the current mapping table cache hit rate is detected; and, in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, the capacity of the cache used to store different levels of mapping tables is adjusted.

14. The operating method according to claim 13, wherein, The multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The first-level mapping table stores the physical address of the second-level mapping table, the second-level mapping table stores the physical address of the third-level mapping table, and the third-level mapping table stores the physical address of the data. The cache stores all of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table. The response that the random read range corresponding to the random read operation meets a preset condition, adjusting the capacity of the cache used to store different levels of mapping tables, includes: In response to the random read range being greater than or equal to a preset value, the proportion of the capacity in the cache used to store the second-level mapping table to the total capacity used to store the second-level mapping table and the third-level mapping table is increased until the current mapping table cache hit rate is greater than or equal to the target mapping table cache hit rate.

15. The operating method according to claim 14, further comprising: Determine the difference between the current mapping table cache hit rate and the target mapping table cache hit rate; Based on the difference, determine the increase in the capacity of the cache used to store the second-level mapping table in this adjustment; wherein the increase is positively correlated with the difference.

16. The operating method according to claim 14, further comprising: When the current mapping table cache hit rate is less than the target mapping table cache hit rate, and the proportion of the current cache capacity used to store the second-level mapping table in the total capacity used to store the second-level mapping table and the third-level mapping table reaches a preset proportion, the adjustment of the cache capacity used to store different levels of mapping tables is stopped.

17. A storage medium, wherein, The storage medium stores executable instructions that, when executed by a processor, implement the steps of the method according to any one of claims 13 to 16.

18. A memory controller, comprising: The caching and control unit, in which, The cache is configured to store a portion of a multi-level mapping table in a non-volatile memory device; the multi-level mapping table is configured to implement a mapping from logical addresses to physical addresses; The control unit is configured to: perform a random read operation on the data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation being greater than or equal to a preset value, obtain the target mapping table cache hit rate corresponding to the random read range and detect the current mapping table cache hit rate; and, in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, adjust the capacity of the cache used to store different levels of mapping tables.

19. The memory controller of claim 18, further comprising: A flash memory conversion layer connects the control unit and the cache; The flash translation layer is configured to convert the logical address into the corresponding physical address based on the mapping information in the multi-level mapping table stored in the cache.

20. The memory controller of claim 18, wherein, The control unit is also configured to receive instructions from the host to perform read, write, and erase operations on the memory device; The cache is also configured to temporarily store data transferred between the host and the memory device; The memory controller also includes: An encoder / decoder is used to encode and decode data transmitted between the host and the memory device.

21. A memory system, comprising: At least one non-volatile memory device and a memory controller coupled to said at least one non-volatile memory device; wherein, The memory device stores a multi-level mapping table, which is used to implement the mapping from logical address to physical address; The memory controller includes a cache that stores a portion of the multi-level mapping table; The memory controller is configured to: A random read operation is performed on the data stored in the memory device; wherein, in response to the random read range corresponding to the random read operation being greater than or equal to a preset value, a target mapping table cache hit rate corresponding to the random read range is obtained, and the current mapping table cache hit rate is detected; and, in response to the current mapping table cache hit rate being less than the target mapping table cache hit rate, the amount of different levels of mapping tables loaded from the memory device into the cache at one time is adjusted.

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