A method for improving the tolerance of hafnium-based ferroelectric devices

Abstract

The present invention discloses a method for improving the tolerance of hafnium-based ferroelectric devices. The method includes the following steps: forming a first HZO layer on a Si substrate, then forming a first TiN layer, and performing rapid thermal annealing treatment in a nitrogen atmosphere. Subsequently, etching away the first TiN layer; forming a ZrO2 layer and a second HZO layer, then forming a second TiN layer, and performing rapid thermal annealing treatment in a nitrogen atmosphere. By controlling the thickness of the ZrO2 layer to have appropriate antiferroelectric characteristics, the intensity of the polarization current during the polarization reversal process of the ferroelectric device is weakened, thereby improving the tolerance of the hafnium-based ferroelectric device; performing photolithography etching on the second TiN layer to form a gate; performing ion implantation doping to form source and drain regions in the silicon substrate on both sides of the gate, and performing high-temperature annealing to activate the impurities.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the tolerance of hafnium-based ferroelectric devices. Background Art

[0002] Ferroelectric memories are a new type of non-volatile memories. Traditional ferroelectric materials such as perovskite, lithium niobate, and PVDF have problems such as difficulty in compatibility with MOS processes. It was not until 2011 that T.S. Boscke found that HfO2 doped with Si has ferroelectricity, and then ferroelectric characteristics were observed in the doping of elements such as Al, Zr, and La with HfO2. Subsequently, the research on FeFETs has shifted to hafnium-based ferroelectrics that are compatible with mainstream CMOS.

[0003] At present, hafnium-based ferroelectric field-effect transistors have become a research hotspot due to their low power consumption, high writing speed, and compatibility with MOS processes. However, currently, those based on hafnium-based ferroelectrics have a relatively low tolerance of about 10 5 This will severely limit the development of hafnium-based ferroelectric transistors, and it is necessary to develop hafnium-based ferroelectric devices with more excellent durability to meet the requirements of storage applications. Summary of the Invention

[0004] The present invention discloses a method for improving the tolerance of hafnium-based ferroelectric devices, including the following steps: forming a first HZO layer on a Si substrate, then forming a first TiN layer, and performing rapid thermal annealing treatment in a nitrogen atmosphere. Subsequently, the first TiN layer is etched away; a ZrO2 layer and a second HZO layer are formed, then a second TiN layer is formed, and rapid thermal annealing treatment is performed in a nitrogen atmosphere. By controlling the thickness of the ZrO2 layer to have appropriate antiferroelectric characteristics, the intensity of the polarization current during the polarization reversal process of the ferroelectric device is weakened, thereby improving the tolerance of the hafnium-based ferroelectric device; the second TiN layer is lithographically etched to form a gate; ion implantation doping is performed to form source and drain regions in the silicon substrate on both sides of the gate, and high-temperature annealing is performed to activate the impurities.

[0005] In the method for improving the tolerance of hafnium-based ferroelectric devices of the present invention, preferably, the thickness of the ZrO2 layer is 6 nm to 9 nm.

[0006] In the method for improving the tolerance of hafnium-based ferroelectric devices of the present invention, preferably, the thickness of the HZO layer is 1 nm to 3 nm.

[0007] In the method for improving the tolerance of hafnium-based ferroelectric devices of the present invention, preferably, the temperature of the rapid thermal annealing is 500 °C and the time is 30 s.

[0008] In the method for improving the tolerance of hafnium-based ferroelectric devices according to the present invention, preferably, the ZrO2 layer, the first HZO layer, and the second HZO layer are formed by plasma-enhanced atomic layer deposition method.

[0009] Beneficial effects:

[0010] The HZO / ZrO2 interface formed by PEALD deposition can control the grain size in the HZO thin film, which is beneficial to increasing the proportion of the ferroelectric phase in the ferroelectric layer and thus expanding the storage window.

[0011] In the constructed HZO / ZrO2 / HZO stacked structure, by adjusting the thickness of the ZrO2 layer to have appropriate antiferroelectric characteristics, the intensity of the polarization current during the polarization reversal process of the ferroelectric device can be weakened, and the tolerance of the hafnium-based ferroelectric device can be improved.

[0012] Using atomic layer deposition technology to grow dielectric thin films can precisely control the thickness of the thin films, obtain highly conformal and high-quality dielectric thin films, and the dielectric constant of hafnium oxide will also increase after appropriate doping, which can reduce the electric field intensity borne by the dielectric layer and improve the working life of the dielectric layer, largely ensuring the stability of the device operation. Description of the drawings

[0013] Figure 1 is a flowchart of the method for improving the tolerance of hafnium-based ferroelectric devices.

[0014] Figures 2 to 8 is a schematic structural diagram of each stage of the method for improving the tolerance of hafnium-based ferroelectric devices. Detailed implementation manners

[0015] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0016] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0017] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details. Unless specifically pointed out below, each part in the device can be made of materials well known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0018] Figure 1 is a flowchart of a method for improving the tolerance of hafnium-based ferroelectric devices. As Figure 1 shown, the method for improving the tolerance of hafnium-based ferroelectric devices includes the following steps:

[0019] Step S1, soak the n-type silicon substrate 100 in a diluted HF solution (HF:H2O = 1:100) for 1 min to 3 min to remove the native oxide layer on the Si surface, and finally dry it with N2.

[0020] Step S2, perform field isolation on the silicon substrate 100 by the LOCOS method, and form a field oxide layer 101 and a field region by photolithography, as Figure 2 shown.

[0021] Step S3, use plasma-enhanced atomic layer deposition (PEALD) to grow a 1 nm to 3 nm thick HZO 102. Then, use physical vapor deposition (PVD) to prepare a TiN layer 103, and perform a rapid heat treatment at a temperature of 500 °C for 30 s in an N2 environment. The resulting structure is as Figure 3 shown. By the action of stress application, the proportion of the orthorhombic phase in HfO2 is increased. Then, wet-etch the TiN layer 103 with a mixed solution of H2O2:NH3.H2O = 5:1 and then clean it with deionized water.

[0022] Step S4, deposit a 6 nm to 9 nm thick ZrO2 layer 104 and a 1 nm to 3 nm thick HZO layer 105, then use PVD to prepare a 50 nm to 80 nm thick TiN layer 106, and perform a rapid annealing heat treatment at a temperature of 500 °C for 30 s in an N2 environment. The resulting structure is as Figure 4 shown. By controlling the thickness of ZrO2 to have appropriate antiferroelectric characteristics, the intensity of the polarization current during the polarization reversal process of the ferroelectric device is effectively weakened, thereby improving the tolerance of the device.

[0023] Step S5, form a photoresist 107, perform photolithography and etching on the TiN layer 106 to define the gate. The resulting structure is as Figure 5 shown.

[0024] Step S6, perform P+ Ion implantation doping is used to form a source region 109 and a drain region 110 in the silicon substrate 100 on both sides of the gate, and annealing is performed at a temperature of 600 °C to 900 °C for 5 minutes to activate impurities, such as Figure 6 shown.

[0025] In step S7, the photoresist 107 is removed, silicon dioxide is deposited, and anisotropic etching is performed to form sidewalls 111, such as Figure 7 shown.

[0026] In step S8, a metal Ni layer 112 is formed on the source region 109 and the drain region 110 by physical vapor deposition, rapid thermal annealing is performed at 310 °C for 1 minute, and then the excess metal is removed with aqua regia (concentrated nitric acid: concentrated sulfuric acid = 3:1), and then rapid thermal annealing is performed at 510 °C for 10 s to form an ohmic contact, such as Figure 8 shown.

[0027] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for improving the tolerance of hafnium-based ferroelectric devices, characterized in that, it includes the following steps: Form a first HZO layer on a Si substrate, then form a first TiN layer, and perform rapid thermal annealing treatment in a nitrogen atmosphere. Subsequently, etch away the first TiN layer; Form a ZrO2 layer and a second HZO layer, then form a second TiN layer, and perform rapid thermal annealing treatment in a nitrogen atmosphere. By controlling the thickness of the ZrO2 layer to have appropriate antiferroelectric characteristics, the intensity of the polarization current during the polarization reversal process of the ferroelectric device is weakened, and the tolerance of the hafnium-based ferroelectric device is improved; Lithographically pattern and etch the second TiN layer to form a gate; Perform ion implantation doping to form source and drain regions in the silicon substrate on both sides of the gate, and perform high-temperature annealing to activate the impurities.

2. The method for improving the tolerance of hafnium-based ferroelectric devices according to claim 1, characterized in that, the thickness of the ZrO2 layer is 6 nm to 9 nm.

3. The method for improving the tolerance of hafnium-based ferroelectric devices according to claim 2, characterized in that, the thickness of the HZO layer is 1 nm to 3 nm.

4. The method for improving the tolerance of hafnium-based ferroelectric devices according to claim 1, characterized in that, the temperature of the rapid thermal annealing is 500 °C and the time is 30 s.

5. The method for improving the tolerance of hafnium-based ferroelectric devices according to claim 1, characterized in that, the ZrO2 layer, the first HZO layer, and the second HZO layer are formed by plasma-enhanced atomic layer deposition method.

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