Improved method for passivation layer etching

Abstract

The present invention relates to an improved method for etching a passivation layer, comprising: step A, obtaining a wafer structure; the wafer structure comprising a substrate, a metal structure on the substrate, and a passivation layer covering the metal structure; step B, photolithographically forming an etching window; step C, dry-etching the passivation layer through the etching window at a first radio frequency power, stopping before etching reaches the metal structure; step D, continuing to dry-etch downward at a second radio frequency power through the etching window until etching reaches the metal structure; the second radio frequency power being less than the first radio frequency power. The present invention reduces the radio frequency power of the dry etching before the passivation layer is etched to the metal structure, thereby reducing the plasma charge density when the dry etching plasma begins to contact the metal structure, improving plasma damage, and avoiding abnormal device turn-on voltage caused by plasma damage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an improved method for etching a passivation layer. Background Art

[0002] Passivation layer etching is a dry etching process in the semiconductor manufacturing process. After the top aluminum pattern is formed, the CVD method is used to cover the silicon dioxide and silicon nitride dielectrics, and then the pattern is formed by photolithography technology, and then dry etching is used to transfer the pattern to the wafer. Passivation layer etching can specifically use plasma technology combined with physical bombardment and chemical reactions to remove specific materials. During the mass production process, the WAT (Wafer Acceptance Test) test Vt (turn-on voltage) parameter abnormality occurs occasionally, which is manifested as a large Vt uniformity within the chip.

[0003] When the WAT Vt parameter exceeds the specification, the chip cannot be used normally, resulting in scrap or yield loss. Summary of the Invention

[0004] In order to solve the problem of abnormal device turn-on voltage, it is necessary to provide an improved method for etching the passivation layer.

[0005] An improved method for etching a passivation layer comprises: step A, obtaining a wafer structure; the wafer structure comprises a substrate, a metal structure on the substrate, and a passivation layer covering the metal structure; step B, photolithographically forming an etching window; step C, dry-etching the passivation layer through the etching window at a first radio frequency power, stopping before etching reaches the metal structure; step D, continuing to dry-etch downward through the etching window at a second radio frequency power until etching reaches the metal structure; the second radio frequency power being less than the first radio frequency power.

[0006] The improved method for etching the passivation layer mentioned above reduces the RF power of the dry etching before the passivation layer is etched to the metal structure, thereby reducing the plasma charge density when the dry etching plasma begins to contact the metal structure, improving plasma damage, and avoiding abnormal device turn-on voltage caused by plasma damage.

[0007] In one embodiment, the second RF power is a power at which the plasma generated by the dry etching in step C does not cause plasma damage to the metal structure.

[0008] In one embodiment, the second RF power is 400W to 600W.

[0009] In one embodiment, the metal structure includes a conductive body and an auxiliary layer on the conductive body, and step D stops after etching to the auxiliary layer. Step D also includes: step E, continuing to dry-etch downward to the conductive body through the etching window with a third RF power, and the third RF power is greater than the second RF power.

[0010] In one embodiment, the first radio frequency power and the third radio frequency power are equal.

[0011] In one embodiment, the first RF power and the third RF power are 800W to 1500W.

[0012] In one embodiment, the conductive body includes aluminum copper, and the auxiliary layer includes a titanium layer and a titanium nitride layer on the titanium layer.

[0013] In one embodiment, the step D stops after etching reaches the titanium nitride layer.

[0014] In one embodiment, the passivation layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

[0015] In one embodiment, the silicon oxide layer includes a silicon dioxide layer, and the silicon nitride layer includes a silicon nitride layer.

[0016] In one embodiment, the wafer structure obtained in step A further includes an etching stop layer disposed between the metal structure and the silicon oxide layer, the etching stop layer being an insulating medium and having a material different from that of the silicon oxide layer; and step C is etching to the etching stop layer.

[0017] In one embodiment, the method further includes detecting the spectral wavelength of the etching products of step C and step D; in step C, etching is stopped when an increase in the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer is detected, and step D is executed; in step D, etching is stopped when a decrease in the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer is detected, and step E is executed.

[0018] In one embodiment, the material of the etching stop layer includes silicon nitride; in step C, when the spectral wavelength is detected When the concentration of increases, the etching is stopped and step D is performed; the step D is performed when the spectral wavelength is detected. When the concentration of MgO decreases, etching is stopped and step E is performed.

[0019] In one embodiment, step C and step D are dry-etched in the same equipment.

[0020] In one embodiment, step C, step D, and step E are dry-etched in the same equipment.

[0021] In one embodiment, the etching gas in step C and step D includes CF4, CHF3, AR, SF6 and N2.

[0022] In one embodiment, the step B is to form an etching window of the contact hole by photolithography.

[0023] In one embodiment, the metal structure is a top metal layer, and the wafer structure obtained in step A also includes a layer before the top metal layer. The present application also provides another improved method for etching a passivation layer, comprising: obtaining a wafer structure; the wafer structure includes a substrate, a metal structure on the substrate, and a passivation layer covering the metal structure; photolithographically forming an etching window; dry-etching the passivation layer through the etching window at a first radio frequency power, stopping before etching reaches the metal structure; after reducing the plasma charge density to a level that does not cause plasma damage to the metal structure, continuing to dry-etch downward through the etching window until etching reaches the metal structure.

[0024] In one embodiment, the second RF power is 400W to 600W.

[0025] In one embodiment, the metal structure includes a conductive body and an auxiliary layer on the conductive body, and step D stops after etching to the auxiliary layer. Step D also includes: step E, continuing to dry-etch downward to the conductive body through the etching window with a third RF power, and the third RF power is greater than the second RF power.

[0026] In one embodiment, the first radio frequency power and the third radio frequency power are equal.

[0027] In one embodiment, the first RF power and the third RF power are 800W to 1500W.

[0028] In one embodiment, the conductive body includes aluminum copper, and the auxiliary layer includes a titanium layer and a titanium nitride layer on the titanium layer.

[0029] In one embodiment, the step D stops after etching reaches the titanium nitride layer.

[0030] In one embodiment, the passivation layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

[0031] In one embodiment, the silicon oxide layer includes a silicon dioxide layer, and the silicon nitride layer includes a silicon nitride layer.

[0032] In one embodiment, the wafer structure obtained in step A further includes an etching stop layer disposed between the metal structure and the silicon oxide layer, the etching stop layer being an insulating medium and having a material different from that of the silicon oxide layer; and step C is etching to the etching stop layer.

[0033] In one embodiment, the method further includes detecting the spectral wavelength of the etching products of step C and step D; in step C, etching is stopped when an increase in the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer is detected, and step D is executed; in step D, etching is stopped when a decrease in the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer is detected, and step E is executed.

[0034] In one embodiment, the material of the etching stop layer includes silicon nitride; in step C, when the spectral wavelength is detected When the concentration of increases, the etching is stopped and step D is performed; the step D is performed when the spectral wavelength is detected. When the concentration of MgO decreases, etching is stopped and step E is performed.

[0035] In one embodiment, step C and step D are dry-etched in the same equipment.

[0036] In one embodiment, step C, step D, and step E are dry-etched in the same equipment.

[0037] In one embodiment, the etching gas in step C and step D includes CF4, CHF3, AR, SF6 and N2.

[0038] In one embodiment, the step B is to form an etching window of the contact hole by photolithography.

[0039] In one embodiment, the metal structure is a top metal layer, and the wafer structure obtained in step A also includes layers before the top metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0041] Figure 1 is a flow chart of an improved method for etching a passivation layer in one embodiment;

[0042] Figures 2a to 2e In one embodiment, Figure 1A schematic cross-sectional view of a device during the process of manufacturing the device using the method shown;

[0043] Figures 3a to 3d In one embodiment, Figure 4 A schematic cross-sectional view of a device during the process of manufacturing the device using the method shown;

[0044] Figure 4 is a flow chart of an improved method for etching a passivation layer in another embodiment;

[0045] Figure 5 This is a comparison chart of the turn-on voltage test results of a device made using an improved passivation layer etching method in an embodiment and a WAT in a comparative example;

[0046] Figure 6 This is a comparison chart of the turn-on voltage test results of a device made using an improved passivation layer etching method in another embodiment and a WAT in a comparative example. DETAILED DESCRIPTION

[0047] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0053] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0054] The inventors analyzed the test results of the Vt chip uniformity being too large and found that the anomaly corresponded one-to-one with the passivation layer etching cavity, and there was no obvious difference in the physical structure of the device. The inventors believed that the electrical anomaly was caused by plasma damage.

[0055] The core factor affecting plasma damage is the imbalance of plasma in a local area. This imbalance is inevitable. The industry has the following approaches to studying plasma damage:

[0056] 1. For product design: Add protection circuits to new products to enhance the chip's ability to resist plasma damage.

[0057] 2. For the equipment side: optimize the cavity to make the plasma source more stable and uniform.

[0058] 3. For the process end: Introduce a gradual process at the beginning of the plasma generation step to avoid sudden changes in the plasma that may cause instability and unevenness.

[0059] Option 3 primarily addresses potential instability and unevenness during plasma initiation. For example, increasing the power from 0W to 2000W could be further divided into multiple steps: 0W to 500W, 500W to 1000W, and 1000W to 2000W. Alternatively, the pressure stabilization process could be divided into multiple, gradual steps. The core idea is to reduce sudden changes in plasma process conditions, thereby reducing the possibility of plasma instability and unevenness.

[0060] In an attempt to address the plasma damage issue, the inventors attempted to reduce the sudden change in plasma process conditions (by gradually changing the initial step), but this approach proved ineffective. Analysis revealed the following reasons: reducing sudden changes in plasma process conditions is only applicable to processes with significant initial and process variations. However, in the exemplary process, process conditions remained unchanged throughout the passivation layer etching process, so only gradual changes at the initial step could enhance plasma stability. Experimental results revealed that no matter how the initial step was optimized, the electrical performance of the WAT was not improved, indicating that plasma damage did not occur at the initial step.

[0061] Based on the above phenomenon, the present application combines the entire etching process of the passivation layer and considers improving the plasma damage effect of the entire etching process of the passivation layer.

[0062] In order to improve the plasma damage effect of the entire passivation layer etching process, this application must focus on the key points in the etching process, mainly considering the following aspects:

[0063] 1. Etching process conditions: In the exemplary process, the process conditions remain unchanged from the beginning to the end of the etching process.

[0064] 2. Corresponding equipment: In the exemplary process, from the beginning to the end of the etching process, the etching equipment does not have any alarm messages.

[0065] 3. Etched Materials: Analysis revealed that the largest change in the etched material during the exemplary process was from insulating materials (silicon nitride and silicon dioxide) to conductive materials (titanium nitride and aluminum copper).

[0066] During the entire etching process, the process conditions and corresponding equipment remain unchanged. The only change is the change in the etching material. The inventor first confirmed the effect of improving the plasma damage effect during the etching process by optimizing the process conditions. After long-term experiments, it was finally determined that the process condition with the greatest impact on plasma is power, and the most critical process point is the moment when the insulating material contacts the conductive material. The greater the power at this moment, the more severe the plasma damage (the inventor used enhanced sensitive products to verify the plasma damage). The plasma is always present throughout the entire passivation layer etching process. As long as the power is reduced before the etching process contacts the metal layer, the charge density in the plasma is reduced, which can improve the plasma damage effect. Based on actual conditions, the inventor designed a device structure that is convenient for mass production and refined control, as well as a matching improved method for passivation layer etching.

[0067] Figure 1 1 is a flow chart of an improved method for etching a passivation layer in one embodiment, comprising the following steps:

[0068] S110, obtaining a wafer structure.

[0069] Reference Figure 2aThe wafer structure includes a substrate 210, a metal structure 220 on the substrate 210, and a passivation layer 230 covering the metal structure 220. Various device structures known in the art may be formed in the substrate 210, such as active regions, well regions, and contact regions. Other device structures known in the art may also be formed on the substrate 210, such as gates and dielectric layers. The metal structure 220 may be a top metal layer, such as a metal interconnect. The substrate 210 and the layers before the top metal layer are formed on the substrate, i.e., structures formed by multiple front-end processing steps before the top metal layer. The substrate 210 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, or a multilayer structure composed of these semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI).

[0070] exist Figure 2a In the illustrated embodiment, the passivation layer 230 includes a silicon oxide layer 232 and a silicon nitride layer 234 on the silicon oxide layer. Further, the silicon oxide layer 232 may be a silicon dioxide layer, and the silicon nitride layer 234 may be a silicon nitride layer.

[0071] In one embodiment of the present application, the metal structure 220 includes a conductive body and an auxiliary layer on the conductive body. Further, the conductive body includes aluminum copper, and the auxiliary layer includes a titanium layer and a titanium nitride layer on the titanium layer.

[0072] S120 , forming an etching window by photolithography.

[0073] See also Figure 2b A patterned photoresist layer 240 is formed on the passivation layer 230 by photolithography to expose an etching window 241 for etching the passivation layer.

[0074] The photoresist layer 240 may be made of a common positive or negative photoresist material and patterned through operations such as exposure and development to expose the etching window 241 .

[0075] In one embodiment of the present application, the etching window 241 is an etching window of a contact hole.

[0076] S130 , dry-etching the passivation layer through the etching window with a first radio frequency power, and stopping before etching reaches the metal structure.

[0077] See also Figure 2c , etching away the entire silicon nitride layer 234 and most of the silicon oxide layer 232. In one embodiment of the present application, the etching of step S130 is performed using a time mode (ie, a preset etching time).

[0078] S140 , continuing to perform dry etching downward through the etching window with a second radio frequency power until the metal structure is etched.

[0079] In one embodiment of the present application, the RF power of the dry etching machine used in step S130 is lowered before the product is etched. Specifically, we hope that the second RF power is a power at which the plasma generated by the dry etching will not cause plasma damage to the metal structure 220. The inventors have confirmed through experiments that when the power is between 800 and 1000W, there will be a significant change in the probability of plasma damage. Therefore, the RF power of the etching machine cannot be too high when the etching process contacts the metal structure 220. In one embodiment of the present application, the second RF power is 400W to 600W, and the first RF power is 800W to 1500W.

[0080] The improved method for etching the passivation layer mentioned above reduces the RF power of the dry etching before the passivation layer is etched to the metal structure 220, thereby reducing the plasma charge density when the dry etching plasma begins to contact the metal structure, improving plasma damage, and avoiding abnormal device turn-on voltage caused by plasma damage.

[0081] In one embodiment of the present application, step S140 is stopped after etching reaches the titanium nitride layer in the metal structure 220. Figure 2d After step S140, step S150 is also included: dry etching is continued downwards through the etching window 241 to the aluminum and copper in the metal structure 220 with the third radio frequency power, see Figure 2e The third RF power is greater than the second RF power. After step S140 is completed, etching is resumed at a high power, which is beneficial to improving the selectivity of the titanium nitride / titanium material and the barrier layer photoresist material during the etching process, and avoiding excessive loss of the photoresist that may result in removal / damage of the protected material beneath the photoresist during etching.

[0082] In one embodiment of the present application, the third RF power is 800W to 1500W. In one embodiment of the present application, the first RF power and the third RF power are equal. It is understood that step S150 and steps S130 and S140 are all performed using the same etching machine. In one embodiment of the present application, the passivation layer etching is performed using an eMax machine from AMAT.

[0083] In one embodiment of the present application, the etching in step S140 uses an endpoint mode. In one embodiment of the present application, the etching in step S150 uses a time mode.

[0084] In one embodiment of the present application, the etching gases used in steps S130 , S140 and S150 include CF 4 , CHF 3 , AR, SF 6 and N 2 .

[0085] In one embodiment of the present application, steps S130 , S140 , and S150 have the same process conditions except for the RF power.

[0086] Using the optimized passivation layer etching process, we conducted product segmentation verification and found that when the old process caused plasma damage that affected the product WAT Vt, the new process conditions can effectively improve this phenomenon, such as Figure 5 and Figure 6 This demonstrates that the improved passivation layer etching method can effectively mitigate the plasma damage effect of passivation layer etching. Based on this, it has been proven that high-power plasma directly contacting the metal structure 220 is the main factor causing plasma damage. Switching to low power before etching the metal structure 220 is an effective method.

[0087] Figure 4 This is a flow chart of an improved method for etching a passivation layer in another embodiment. In this embodiment, an etch stop layer is added to the metal structure to facilitate more accurate control of the time point when the RF power of the dry etching changes from high to low. Figure 4 The method of the illustrated embodiment includes the following steps:

[0088] S410, obtaining a wafer structure.

[0089] See also Figure 3a The wafer structure includes a substrate 310 , a metal structure 320 on the substrate 310 , an etch stop layer 324 covering the metal structure 320 , and a passivation layer 330 on the etch stop layer 324 .

[0090] Various device structures known in the art, such as active regions, well regions, and contact regions, may be formed in the substrate 310. Other device structures known in the art, such as gates and dielectric layers, may also be formed on the substrate 310. The substrate 310 may be made of at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. It may also be a multilayer structure composed of these semiconductors, or a silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). The metal structure 320 may be a top metal, such as a metal interconnect.

[0091] exist Figure 3aIn the illustrated embodiment, the passivation layer 330 includes a silicon oxide layer 332 and a silicon nitride layer 334 on the silicon oxide layer. Further, the silicon oxide layer 332 may be a silicon dioxide layer, and the silicon nitride layer 334 may be a silicon nitride layer.

[0092] The etch stop layer 324 is an insulating dielectric and needs to have a high etching selectivity with the silicon oxide layer 332. Therefore, a material having a high etching selectivity with the silicon oxide layer 332 is selected as the etch stop layer 324. In one embodiment of the present application, the etch stop layer 324 is a silicon nitride layer.

[0093] In one embodiment of the present application, the metal structure 320 includes a conductive body and an auxiliary layer on the conductive body. Further, the conductive body includes aluminum copper, and the auxiliary layer includes a titanium layer and a titanium nitride layer on the titanium layer.

[0094] S420 , forming an etching window by photolithography.

[0095] In one embodiment of the present application, the etching window 341 is an etching window of a contact hole.

[0096] S430 , dry-etching the passivation layer through the etching window with a first radio frequency power, and stopping when etching reaches the etching stop layer.

[0097] First, a high-power etchant is used to etch away the silicon oxide layer 332 and the silicon nitride layer 334 at the location of the etching window 341, and the etching stops on the etching stop layer 324. Specifically, the spectral wavelength of the etching product is detected during the etching process, and the etching is stopped when the concentration of the characteristic spectral wavelength of the etching product in the etching stop layer 324 is detected to increase.

[0098] In one embodiment of the present application, based on the actual etching process, the spectrum signal of the silicon nitride layer 334 is filtered out during the etching process, and when the spectrum wavelength is detected, When the concentration of increases, the etching of step S430 is stopped ( This is a characteristic spectrum of the etching product CN when the etching stop layer 324 is a silicon nitride layer).

[0099] S440 , etching the etch stop layer through the etching window with a second radio frequency power until the metal structure is etched.

[0100] Switch to low power etching to etch the etch stop layer 324. Stop etching when the concentration of the characteristic spectral wavelength of the etching product of the etch stop layer 324 decreases. In one embodiment of the present application, when the spectral wavelength is detected, The etching of step S440 is stopped when the concentration of decreases.

[0101] In another embodiment of the present application, the etching in step S440 adopts a time mode. For some semiconductor products, the characteristic spectrum signal may be weak due to product design problems, and etching can also be performed according to a fixed time.

[0102] In one embodiment of the present application, the second RF power is 400W to 600W, and the first RF power is 800W to 1500W.

[0103] The improved passivation layer etching method adds a thin etch stop layer 324, which significantly reduces the etching rate when dry etching reaches the etch stop layer 324, thereby ensuring switching to low RF power before etching to the metal structure 320 to achieve stable process control.

[0104] In one embodiment of the present application, step S440 is stopped after etching reaches the titanium nitride layer in the metal structure 320. Figure 3c After step S440, the process further includes step S450: continuing to dry etch downward to the aluminum copper through the etching window 341 with the third RF power. Figure 3d , based on actual product requirements, the corresponding over-etching amount is set to etch the titanium and titanium nitride on the aluminum and copper of the metal structure 320. The third RF power is greater than the second RF power. In one embodiment of the present application, the third RF power is 800W to 1500W. In one embodiment of the present application, the first RF power and the third RF power are equal. It can be understood that step S450 and steps S430 and S440 are all etched using the same etching machine.

[0105] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0106] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0107] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An improved method for etching a passivation layer, comprising: Step A, obtaining a wafer structure; The wafer structure includes a substrate, a metal structure on the substrate, and a passivation layer covering the metal structure, wherein the metal structure includes a conductive body and an auxiliary layer on the conductive body; Step B, photolithography to form an etching window; Step C, dry etching the passivation layer through the etching window with a first radio frequency power, and stopping before etching reaches the metal structure; Step D, continuing to dry etch downward through the etching window at a second RF power until the metal structure is etched; the second RF power is less than the first RF power, and the second RF power is a power at which the plasma generated by the dry etching in Step C does not cause plasma damage to the metal structure; In step E, dry etching is continued downwards to the conductive body through the etching window at a third RF power, wherein the third RF power is greater than the second RF power; and in step D, etching is stopped after the auxiliary layer is reached.

2. The improved method for passivation layer etching according to claim 1, characterized in that: The second radio frequency power is 400W to 600W.

3. The improved method for passivation layer etching according to claim 1, characterized in that: The conductive body includes aluminum copper, and the auxiliary layer includes a titanium layer and a titanium nitride layer on the titanium layer.

4. The improved method for passivation layer etching according to claim 1 or 3, characterized in that: The passivation layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

5. The improved method for passivation layer etching according to claim 4, characterized in that: The silicon oxide layer includes a silicon dioxide layer, and the silicon nitride layer includes a silicon nitride layer.

6. The improved method for passivation layer etching according to claim 4, characterized in that: The wafer structure obtained in step A further includes an etching stop layer provided between the metal structure and the silicon oxide layer, wherein the etching stop layer is an insulating medium and the material thereof is different from that of the silicon oxide layer; The step C is etching to the etching stop layer.

7. The improved method for passivation layer etching according to claim 6, characterized in that: The method further includes detecting the spectral wavelength of the etching products of step C and step D; in step C, etching is stopped when it is detected that the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer increases, and step D is executed; in step D, etching is stopped when it is detected that the concentration of the characteristic spectral wavelength of the etching products of the etching stop layer decreases, and step E is executed.

8. The improved method for passivation layer etching according to claim 7, characterized in that: The material of the etching stop layer includes silicon nitride; in the step C, when the spectral wavelength is detected When the concentration of increases, the etching is stopped and step D is performed; the step D is performed when the spectral wavelength is detected. When the concentration of MgO decreases, etching is stopped and step E is performed.

9. The improved method for passivation layer etching according to claim 1, characterized in that: The metal structure is a top metal layer, and the wafer structure obtained in step A also includes layers before the top metal layer.

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