Copper bonded memory stack with copper bonded interconnect memory system

Abstract

The present application relates to a copper bonded memory stack with a copper bonded interconnect memory system. A memory system includes: a memory stack including a plurality of memory dies interconnected via copper bonds; a logic die coupled to the memory stack via copper bonds. The memory system further includes: a buffer die extended to provide the copper bonds between the logic die and the memory stack; and a silicon carrier layer bonded to the memory stack and the logic die.

Description

Technical Field

[0001] The present description relates generally to integrated circuits, and in particular, to copper bonded memory stacks having copper bonded interconnect memory systems. Background Art

[0002] High bandwidth memory (HBM) is widely used to provide large capacity memory with high bandwidth interconnection with processing logic die in integrated modules for high performance computing, artificial intelligence, machine learning and other applications. Conventional HBM is implemented using several layers of dynamic random access memory (DRAM) die stacked on a buffer die using solder microbumps to interconnect. Compared with solder microbumps, direct copper bonding (hybrid copper bonding or copper fusion bonding, hereinafter referred to as "copper bonding") can provide denser interconnect pitches while also reducing thermal resistance and parasitic electrical impedance between bonded dies.

[0003] Replacing solder microbumps with copper bonding has the potential to significantly increase the practical stacking limit in HBM stacks. For example, the current maximum stack height for solder bonding may be 12 layers. However, with copper bonding, 24 or 32 layers can be stacked, with thinner silicon per layer, lower thermal resistance, and higher bonding yield. Since copper bonding is used to increase the maximum capacity of the HBM stack, memory structures are required to use copper bonding to increase the interconnect bandwidth between the HBM stack and the logic die. Summary of the invention

[0004] On the one hand, the present application relates to a memory system comprising: a memory stack comprising a plurality of memory dies interconnected via copper bonding; a logic die coupled to the memory stack via copper bonding; a buffer die extended to provide the copper bonding between the logic die and the memory stack; and a silicon carrier layer bonded to the memory stack and the logic die.

[0005] On the other hand, the present application relates to a method comprising: manufacturing a memory stack by interconnecting multiple memory dies via copper bonding; coupling a logic die to the memory stack via copper bonding; placing an extended buffer die to provide the copper bonding between the logic die and the memory stack; and bonding a silicon carrier layer to the memory stack and the logic die.

[0006] On the other hand, the present application relates to a system comprising: a memory; and a processor coupled to the memory, wherein: the memory comprises a memory stack including a plurality of memory dies interconnected via copper bonding; the processor is implemented on a logic die coupled to the memory stack via copper bonding; and an extended buffer die is used to provide the copper bonding between the logic die and the memory stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Certain features of the present technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the present technology are set forth in the drawings.

[0008] Figure 1 is a schematic diagram illustrating an example of a memory system including a hybrid copper bond (HCB) bridge-connected memory stack in accordance with various aspects of the present technology.

[0009] Figure 2 is a schematic diagram illustrating an example of a memory system including a high bandwidth memory (HBM) stack with bottom overlapping buffer die connections in accordance with various aspects of the present technology.

[0010] Figure 3 is a schematic diagram illustrating an example of a memory system including an HBM stack with intermediate overlapping buffer die connections in accordance with various aspects of the present technology.

[0011] Figure 4A and 4B is a diagram illustrating an example of a process flow for fabricating HBM dynamic random access memory (DRAM) stacks connected by passive hybrid copper bond (HCB) bridges in accordance with various aspects of the present technology.

[0012] Figure 5A , 5B 5C are diagrams illustrating an example of a process flow for fabricating an HCB DRAM stack with an overlapping buffer at the bottom of the stack in accordance with various aspects of the present technology.

[0013] Fig. 6A , 6B , 6C, and 6D are diagrams illustrating examples of a process flow for fabricating an HCB DRAM stack with an overlapping buffer in the middle of the stack in accordance with various aspects of the present technology.

[0014] Figure 7 is a diagram illustrating a comparison of HCB-connected DRAM stack configurations according to various aspects of the present technology.

[0015] Figure 8 is a schematic diagram illustrating an example of a conventional memory stack. DETAILED DESCRIPTION

[0016] The detailed description set forth below is intended as a description of various configurations of the technology and is not intended to represent the only configuration in which the technology may be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which contains specific details for providing a thorough understanding of the technology. However, the technology is not limited to the specific details set forth herein and may be implemented without one or more of the specific details. In some examples, structures and components are shown in block diagram form in order to avoid confusing the concepts of the technology.

[0017] The present technology relates to a memory system and a system for a copper-bonded memory stack with a copper-bonded interconnect memory system. The disclosed invention defines three different physical configurations for replacing solder microbumps and inserts and / or package connections from HBM to logic die with copper-bonded connections, together with a process sequence for assembling a proposed copper-bonded HBM with copper-bonded connections to logic die. The copper-bonded interconnect memory system of the present technology increases the interconnection bandwidth between a high-bandwidth memory (HBM) stack and a logic die. Relative to other conventional memories, conventional HBMs achieve high-bandwidth interconnection through wider connections to logic die (i.e., connections using a greater number of data lines). In the case of conventional HBM memories, the width of the interface is 1,024 data lines (e.g., compared to 64 data lines in other conventional memories). Compared to conventional solder-bonded HBMs, memory stacks with copper-bonded interconnects can significantly increase the number of data lines, and thus increase interconnection bandwidth. Compared to solder microbump pitch, the increased data line capacity comes from the reduced copper-bonded connection pitch.

[0018] Conventional HBM stacks may use a 55μm solder microbump pitch, while a copper bonded memory stack may have a 9μm connection pitch (or less), a connection density multiplier of more than 37 times that of 55 2 / 9 2 The increased interconnect density with copper bonding also allows for much shorter link distances as the connection array area is dramatically reduced. In conventional HBM, link line lengths are typically several millimeters, while copper bond link lengths can be half a millimeter or less. The reduced link lengths of copper bond connections and reduced parasitic capacitance, resistance, and inductance also allow for higher energy efficiency compared to conventional solder bond HBM.

[0019] The increased interconnect bandwidth provided by copper bonded interconnects is important to realizing the full potential benefits of copper bonded dynamic random access memory (DRAM) stacks. Copper bonded stacks can significantly increase memory stack capacity by increasing the practical limit to the number of layers in the stack due to improved thermal conductivity, improved bonding yield, and increased planarity and mechanical integrity supporting thinner individual DRAM silicon layers. However, if the interconnect bandwidth is not increased, the value of increasing the overall capacity of a copper bonded DRAM stack may not be fully realized in terms of system functionality.

[0020] Figure 1 1 is a schematic diagram illustrating an example memory system 100 including a hybrid copper bond (HCB) bridge-connected memory stack 104 according to various aspects of the present technology. The memory system 100 includes an HCB bridge-connected memory stack 104 (hereinafter, memory stack 100), a logic die 102 (e.g., including a data processing circuit system), a memory stack 104 (e.g., a DRAM stack), an interposer 110, a buffer die 120, a silicon carrier 130, a heat sink 132, and a passive bridge die 140. The memory stack 104 includes a number of memory dies interconnected via copper bonds 108. The memory stack 104 is connected to the interposer 110 via conductive microbumps 112. The logic die 102 is coupled to the interposer 110 via copper bonds 108, through silicon vias (TSVs) 124, and conductive microbumps 112. The passive bridge die 140 is copper-bonded to the logic die 102 and the buffer die 120 and provides interconnection between the logic die 102 and the memory stack 104. Implementing the passive bridge die 140 as a medium to facilitate coupling the logic die 102 and the memory stack 104 through the copper bond 108 is an important feature of the present technology, which allows data signals to be passed through the copper bond instead of TSV and microbumps. This can increase the interconnect bandwidth between the logic die 102 and the memory stack 104. It should be noted that Figure 1 The structural features shown are not drawn to scale.

[0021] Figure 22 is a schematic diagram illustrating an example of a memory system 200 including an HBM stack 204 with a bottom overlapping buffer die connection according to various aspects of the present technology. The memory system 200 includes an HBM stack 204 (e.g., a DRAM stack), a logic die 202 (e.g., including a data processing circuit system), an interposer 210, a buffer die 220, a silicon carrier 230, and a heat sink 232. The HBM stack 204 includes a number of memory dies interconnected via copper bonds 208. The HBM stack 204 is connected to the interposer 210 via conductive microbumps 212. The logic die 202 is coupled to the interposer 210 via copper bonds 208, TSVs 224 through a support die 206, and the conductive microbumps 212. The buffer die 220 extends toward the support die 206 and is connected to the logic die 202 via copper bonds 208. The buffer die 220 facilitates coupling the HBM stack 204 to the logic die 202 via copper bonds 208. Implementing an extension of the buffer die 220 as a medium for providing coupling between the logic die 202 and the HBM stack 204 through copper bonding 208 is an important feature of the present disclosure, which allows data signals to be transmitted through copper bonding instead of TSVs and microbumps, which increases the interconnection bandwidth between the logic die 202 and the HBM stack 204. The maximum data capacity is increased by using copper bonding within the layers of the stack, thereby achieving a larger maximum number of layers through improved thermal conductivity, mechanical integrity, and electrical properties. In this case, the copper bonding interconnection through the bridge die may not increase the capacity, but it does allow the system to take full advantage of the increased capacity, which would otherwise be limited by the narrower conventional interface between the memory and the logic die. As described above, in the memory system 200, the buffer die 220 is on the bottom of the HBM stack 204, where the buffer is extended to overlap with the logic die 202 (processor). The depth of the support die 206 on the logic die 202 is limited to exactly one level. It should be noted that Figure 2 The structural features shown are not drawn to scale.

[0022] Figure 33 is a schematic diagram illustrating an example of a memory system 300 including an HBM stack 304 with a middle overlapping buffer die connection according to various aspects of the present technology. The memory system 300 includes an HBM stack 304 (e.g., a DRAM stack), a logic die 302 (e.g., including data processing circuitry), an interposer 310, a buffer die 320, a silicon carrier 330, and a heat sink 332. The HBM stack 304 includes a number of memory dies interconnected via copper bonds 308. The HBM stack 304 is connected to the interposer 310 via conductive microbumps 312. The logic die 302 is coupled to the interposer 310 via copper bonds 308, TSVs 324 through a support die 306, and conductive microbumps 312. The buffer die 320 is disposed in the middle of the HBM stack 304 and extends toward the support die 306 and is connected to the logic die 302 via copper bonds 308. The intermediate buffer die 320 facilitates coupling the HBM stack 304 to the logic die 302 via copper bonds 308. Therefore, extending the intermediate buffer die 320 as a medium to provide coupling between the logic die 302 and the HBM stack 304 through copper bonds 308 is an important feature of the present disclosure and allows data signals to be passed through copper bonds instead of TSVs and microbumps, which increases the interconnection bandwidth between the logic die 302 and the HBM stack 304. In the memory system 300, the buffer die 320 is in the middle of the HBM stack 304, where the buffer die 320 is extended to overlap with the logic die 302 (processor). The support die 306 on the logic die 302 has a depth greater than or equal to two levels. It should be noted that Figure 3 The structural features shown are not drawn to scale.

[0023] Figure 4A and 4BFIG401 is a diagram illustrating an example of a process flow 400A and 400B for manufacturing a HBM dynamic DRAM stack connected by a passive HCB bridge according to various aspects of the present technology. The process flow 400A shows only the main steps and skips the description of the process flow of the well-known individual layers. In process step 401, a structure 415 including a logic die 410 (e.g., including a data processing circuit system), a buffer die 420 (where each of 410 and 420 includes a copper bond 408 and an active layer 418 (including active elements such as transistors)) is attached face down (i.e., where the active surface 418 and the copper bond layer 408 are oriented downward) on a temporary carrier 425 using a temporary adhesive layer 409. These dies have been manufactured by a normal wafer manufacturing process completed through a standard interconnect stack, followed by adding a copper bond layer 408 and singulation before being attached to the temporary carrier in the first FIG401. In process step 402, filler 417 (e.g., dielectric material) is deposited and structure 415 (including buffer die 420 and logic die 410) is thinned to the desired thickness. In process step 403, silicon carrier layer 430 is permanently bonded to the in-process product of process step 402, and the result is flipped so that temporary carrier 425 can be removed in the next process step 404. It should be noted that the above description of processing a single die in practice applies to an entire wafer full of such die that are processed simultaneously. Moreover, although the drawings show only one memory stack attached to a logic die, in actual use, several memory stacks will be connected to each logic die, and during the formation of the entire system, the various logic dies themselves may also be interconnected to each other by copper bonding bridges.

[0024] Figure 4B Process flow 400B of FIG. 4 is a continuation of process flow 400A and includes process steps 405, 406, and 407. In process step 405, a structure 435 including an HCB memory stack 424, a supporting die 426, a passive bridge 442, and corresponding active layers and copper bonding layers are prepared and aligned face-to-face and wafer-to-die with the in-process product of step 404 (e.g., a reconstituted wafer). In process step 406, the memory stack 424, the passive bridge 442, and the supporting die 426 are copper bonded to the in-process product of step 404. In process step 407, the backside of the attached dies 424, 432, and 426 (structure 435) bonded to the in-process product of step 404 is processed (e.g., using chemical mechanical polishing) to the desired thickness to expose the TSVs. The structure is then completed by adding solder microbumps or pillars and attaching an interposer and heat sink (steps not shown) to produce Figure 1 A memory system 100 is provided.

[0025] Figure 5A , 5B5 and 5C are diagrams illustrating examples of process flows 500A, 500B, and 500C for manufacturing an HCB DRAM stack with an overlapping buffer at the bottom of the stack according to various aspects of the present technology. Process flow 500A shows only the main steps and skips the description of the process flow of the well-known individual layers. In process step 501, a logic die (e.g., including a processor) 510 and a memory stack die 524 (e.g., an HCB DRAM stack) are mounted on a temporary carrier 525 using a temporary adhesive layer 513. In process step 502, a filler 517 (e.g., a dielectric material) is deposited to fill the gap, such as Figure 5A In process step 503, a silicon carrier wafer 530 is permanently bonded to the in-process product of process step 502 and the result is flipped so that it can be Figure 5B In the next process step 504, the temporary carrier 525 is removed.

[0026] Figure 5B Process flow 500B is a continuation of process flow 500A and includes process steps 504, 505, 506, and 507. In process step 504, temporary carrier 525 is removed to expose logic die 510 and memory stack die 524 and corresponding copper bonding layers. In process step 505, buffer die 520, support die 516 and corresponding active layers and copper bonding layers are prepared and aligned face-to-face and die-to-wafer with the in-process product of step 504. In process step 506, buffer die 520 and support die 516 of process step 505 are copper bonded to the aligned in-process product of step 504.

[0027] Figure 5C is a continuation of process flow 500B and includes process step 507. In process step 507, the buffer die 520 and the support die 516 bonded to the in-process product of step 504 are processed (e.g., by chemical mechanical polishing) to a desired thickness to produce Figure 3 Portions of the memory system 300 (eg, the logic die 302, the top portion of the memory stack 304, the buffer die 320, the support die 308, and the silicon carrier 330).

[0028] Fig. 6A , 6B, 6C and 6D are diagrams illustrating examples of process flows 600A, 600B, 600C and 600D for manufacturing an HCB DRAM stack according to various aspects of the present technology, wherein there is an overlapping buffer in the middle of the stack. Although the overlapping copper bond buffer is described herein as being placed exactly in the middle of the stack (a "half stack" on either side) for minimizing worst-case path delays, in some embodiments, the buffer may be anywhere within the stack. Process flow 600A shows only the major steps and skips descriptions of the process flows for well-known individual layers. In process step 601, a temporary adhesive layer 613 is used to bond a logic die (e.g., including a processor) 610 and a half memory stack 624 (e.g., an HCB DRAM stack) to a temporary carrier 625. In process step 602, a filler 617 (e.g., a dielectric material) is deposited to fill the gap, such as Fig. 6A In process step 603, a silicon carrier wafer 630 is permanently bonded to the in-process product of process step 602 and the result is flipped so that it can be Figure 6B In the next process step 604, the temporary carrier 625 is removed.

[0029] Figure 6B Process flow 600B is a continuation of process flow 600A and includes process steps 604, 605, and 606. In process step 604, temporary carrier 625 is removed to expose logic die 610 and half memory stack die 624 and corresponding copper bonding layers. In process step 605, buffer die 620, support die 616 and corresponding active layers and copper bonding layers are prepared and aligned face-to-face and die-to-wafer with the in-process product of step 604. In process step 606, buffer die 620 and support die 616 of process step 605 are copper bonded to the aligned in-process product of step 604.

[0030] Figure 6C is a continuation of process flow 600B and includes process steps 607 and 608. In process step 607a, the buffer die 620 and support die 616 bonded to the product in process of step 604 are processed to the desired thickness, exposing the TSVs. Process step 607b shows the product of process step 607a being prepared for subsequent copper bonding by adding a patterned copper bonding layer 615 over the exposed TSVs. In process step 608, a half memory stack 626 and a second support die 618 and corresponding active layers and copper bonding are prepared and aligned face-to-face and die-to-wafer with the product in process of step 607.

[0031] Fig.6Dis a continuation of process flow 600C and includes process steps 609 and 610. In process step 609, the half memory stack 626 and the second support die 618 are permanently bonded to the in-process product of step 607b. In process step 610, the half memory stack 626 and the second support die 618 bonded to the in-process product of step 607b are processed to the desired thickness to expose the TSVs. In process step 608, the half memory stack 626 and the second support die 618 and the corresponding active layers and copper bonds are prepared and aligned face-to-face and die-to-wafer with the in-process product of step 607 to produce Figure 2 Portions of the memory system 200 (eg, logic die 202, memory stack 204, buffer die 220, support die 208, and silicon carrier 230).

[0032] Figure 7 is a diagram illustrating a comparison of HCB-connected DRAM stack configurations 710, 720, and 730 according to various aspects of the present technology. HCB-connected DRAM stack configurations 710, 720, and 730 are the products of the process flows of FIG. 4 (4A and 4B), FIG. 5 (5A, 5B, and 5C), and FIG. 6 (6A, 6B, 6C, and 6D), respectively, and are completed by adding a copper redistribution layer with associated dielectrics and solder microbumps for connecting to an interposer or other package. In the orientation shown in these configurations, the primary heat removal is through the top surface, which is the back side of the silicon carrier. It should be noted that the silicon carrier may include embedded microfluidic cooling.

[0033] By connecting to Figure 7 The micro-bump connections of an interposer or other package (not shown) exposed at the bottom of the surface oriented in the configuration of 710 provide power and ground connections for the DRAM stack (and logic die). It should be noted that in configurations 710 and 730, the power and ground of the buffer die are fed through the DRAM stack, while in configuration 720, the TSV array in the DRAM stack only carries power for the DRAM layer (as in conventional HBM).

[0034] The external connections to the logic die need to be brought down to the same interposer / package plane used by the bottom TSV connections on the DRAM stack. Figure 7As shown in the figure of , this can be accomplished by one or more layers of support dies stacked with the logic die, or it can be achieved using through dielectric vias (not shown). Additional methods for making these external connections to the dummy die may include replacing the currently shown support die with a passive glass die with through glass vias, or using a three-dimensional spring structure formed on and released from the interposer surface. The three configurations 710, 720, and 730 provide different depths that can be used to stack support dies, with the bridge die configuration 710 providing the maximum depth, the bottom buffer configuration 720 providing the minimum depth, and the middle buffer configuration 730 providing an intermediate depth. The middle buffer configuration 730 has the potential benefit that the maximum vertical distance from any DRAM layer to the buffer is halved compared to the other configurations, thereby potentially improving efficiency or reducing latency.

[0035] Figure 8 800 is a schematic diagram illustrating an example of a conventional memory stack 800. The conventional memory system 800 includes an HBM stack 804 (e.g., a DRAM stack), a logic die 802 (e.g., including a data processing circuit system), an interposer 810, a buffer die 820, and a heat sink 832. The HBM stack 804 includes several memory dies interconnected via solder microbump interconnects 808. The HBM stack 804 is connected to the buffer die 820 via solder microbumps 808, and the buffer die 820 is connected to the interposer 810 face-down via solder bumps 812, and a power delivery network (PDN) of the logic die 802 is implemented through TSVs and solder bumps, and communication between the logic die 802 and the HBM stack 804 is provided through solder bumps and the interposer. In the present technology (e.g., Figure 7 In an implementation of 710), the buffer die is connected to the silicon carrier using the back side, the PDNs of both the memory die and the buffer die are through TSVs and copper-to-copper bonding, and communication with the processor is provided through a copper bonding bridge, as described above with respect to Figure 1 described.

[0036] The present technology has several applications, such as applications in high performance logic systems, such as processing units or networking equipment typically installed in data centers. Systems that require the memory capacity of such memory stacks typically consume too much power and generate too much heat for mobile applications.

[0037] It will be appreciated by those skilled in the art that the various illustrative blocks, modules, elements, components, memory systems, and algorithms described herein may be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, memory systems, and algorithms have been described above with respect to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. The described functionality may be implemented in different ways by a technician for each specific application. The various components and blocks may be arranged differently (e.g., arranged in different orders or partitioned in different ways) without departing from the scope of the present technology.

[0038] It should be understood that any particular order or hierarchy of blocks in the disclosed process is an illustration of an example method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the process can be rearranged, or all illustrated blocks should be executed. Any of the blocks can be executed simultaneously. In one or more embodiments, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0039] As used in this specification and any claims of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms do not include people or groups of people. For example, for the purpose of this specification, the term "display" means displaying on an electronic device.

[0040] As used herein, the phrase "at least one of..." preceding a series of items (where the terms "and" or "or" are used to separate any of the items) modifies the list as a whole, rather than each member (i.e., each item) of the list. The phrase "at least one of..." does not require selection of at least one of each listed item; rather, the phrase allows for a meaning that includes at least one of any of the items, and / or at least one of any combination of the items, and / or at least one of each of the items. For example, the phrases "at least one of A, B, and C" and "at least one of A, B, or C" each refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0041] The predicates "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of the subject matter, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control an operation or component may also mean that the processor is programmed to monitor and control the operation or that the processor is operable to monitor and control the operation. Similarly, a processor configured to execute code may be interpreted as a processor programmed to execute code or operable to execute code.

[0042] Phrases such as "on one hand", "the aspect", "on the other hand", "some aspects", "one or more aspects", "an embodiment", "the embodiment", "another embodiment", "some embodiments", "one or more embodiments", "an example", "the example", "another example", "some examples", "one or more examples", "a configuration", "the configuration", "another configuration", "some configurations", "one or more configurations", "the present technology", "the disclosure / the present disclosure" and other variations thereof are for convenience and do not imply that the disclosure associated with such phrase(s) is essential to the present technology or that the disclosure applies to all configurations of the present technology. The disclosure associated with such phrase(s) may apply to all configurations or one or more configurations. The disclosure associated with such phrase(s) may provide one or more examples. Phrases such as "on one hand" or "some aspects" may refer to one or more aspects and vice versa, and this applies similarly to the other aforementioned phrases.

[0043] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, to the extent the terms "including," "having," and the like are used in the description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising," as interpreted when "including" is used as a transitional word in a claim.

[0044] All structural and functional equivalents to the elements of various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public regardless of whether the disclosure is expressly recited in the claims. A claim element should not be interpreted under 35 U.S.C. §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a memory system claim, the phrase “step for”.

[0045] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but to conform to the full range consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean "one and only one", unless explicitly stated, but rather to mean "one or more". Unless otherwise explicitly stated, the term "some" refers to one or more. Male pronouns (e.g., his) include female and neutral genders (e.g., her and its) and vice versa. Titles and subtitles (if any) are used only for convenience and do not limit the present disclosure.

Claims

1. A memory system, comprising: a memory stack comprising a plurality of memory dies interconnected via copper bonding; a logic die coupled to the memory stack via the copper bond; a buffer die extended to provide the copper bond between the logic die and the memory stack; a silicon carrier layer bonded to the memory stack and the logic die; and An interposer layer is coupled to the logic die and the memory stack.

2. The memory system of claim 1, wherein the buffer die is located in a middle position of the memory stack.

3. The memory system of claim 1, wherein the buffer die is located in a bottom position of the memory stack.

4. The memory system of claim 1, further comprising a passive bridge die between the memory stack and the logic die.

5. The memory system of claim 4, wherein the passive bridge die is conductively coupled to the logic die and the buffer die via copper bonds, and wherein the buffer die is connected to the memory stack via copper bonds.

6. The memory system of claim 1, wherein the logic die includes one or more data processing circuitry.

7. The memory system of claim 1, wherein the memory stack comprises a hybrid copper bonded HCB memory including a dynamic random access memory (DRAM).

8. The memory system of claim 1, wherein the interposer layer is coupled to the logic die via one or more supporting dies including through silicon vias (TSVs) coupled to each other and to the logic die via copper bonding.

9. The memory system of claim 1, further comprising a heat spreader layer bonded to the silicon carrier layer.

10. The memory system of claim 1, wherein the buffer die overlaps the logic die.

11. A method for manufacturing a memory system, comprising: fabricating a memory stack by interconnecting a plurality of memory dies via copper bonding; coupling a logic die to the memory stack via the copper bond; positioning an extended buffer die to provide the copper bond between the logic die and the memory stack; bonding a silicon carrier layer to the memory stack and the logic die; and An interposer layer is coupled to the logic die and the memory stack.

12. The method of claim 11, further comprising placing the extended buffer die in a bottom position of the memory stack.

13. The method of claim 11, further comprising placing the extended buffer die in a middle position of the memory stack.

14. The method according to claim 11, further comprising: placing a passive bridge die between the memory stack and the logic die; conductively coupling the passive bridge die to the logic die and the extended buffer die via copper bonding; and The extended buffer die is connected to the memory stack via the copper bond.

15. The method according to claim 11, further comprising: The interposer layer is coupled to the logic die and the The one or more support dies are coupled to each other and to the logic die via copper bonding.

16. The method of claim 11, further comprising bonding a heat spreader layer to the silicon carrier layer.

17. The method of claim 11, wherein fabricating the memory stack comprises fabricating a hybrid copper bonded HCB memory including dynamic random access memory (DRAM), and wherein coupling the logic die comprises coupling data processing circuitry.

18. The method of claim 11, wherein coupling the interposer layer to the logic die and the memory stack comprises coupling through copper bonding.

19. A memory system comprising: The memory includes a memory stack comprising a plurality of memory dies interconnected via copper bonding; a processor coupled to the memory, the processor being implemented on a logic die coupled to the memory stack via copper bonding; an extended buffer die configured to provide the copper bond between the logic die and the memory stack, the extended buffer die being located in one of a middle position or a bottom position of the memory stack; and An interposer layer is coupled to the logic die via one or more support dies including through silicon vias (TSVs) coupled to each other and to the logic die via the copper bonds, wherein the interposer layer is coupled to the memory stack by solder bumps.

20. The memory system of claim 19, wherein the solder bumps comprise conductive solder bumps.

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