Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a semiconductor substrate, a ring-shaped isolation structure and a gate structure, the semiconductor substrate comprises an active region, the gate structure is located on the active region, and the ring-shaped isolation structure is located on the active region and surrounds the gate structure. A body region doped with a first conductive type is included in the active region outside the ring-shaped isolation structure, source-drain regions doped with a second conductive type are included in the active region on both sides of the gate structure, and the source-drain regions on both sides of the gate structure are spaced apart by the gate structure; the body region and the source-drain region are electrically isolated by the ring-shaped isolation structure. The ring-shaped isolation structure can separate the source-drain region and the body region to be independent of each other, so that direct contact is avoided, thereby enabling the source-drain region and the body region to be provided with independent contact structures in the future, guaranteeing the contact effect and improving the reliability of the semiconductor device; meanwhile, the ring-shaped isolation structure can realize the electrical isolation performance between the source-drain region and the body region, and further improve the reliability of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Integrated circuits and electronic components will produce total dose, single particle, transient radiation and other radiation effects under irradiation conditions. Radiation effects mainly cause rapid degradation of devices and failure of circuit functions by accumulating electrons on the oxide surface and forming leakage channels. In field effect transistors, the shallow trench isolation (STI) structure is mainly composed of oxide and is one of the radiation-sensitive regions. The device using the ring gate structure can avoid the influence of radiation effects because the channel region is in the active area and does not contact the oxide of the STI region.

[0003] However, the ring gate structure needs to lead out the source end and the substrate outside the ring gate structure through respective contact holes. In the case of small size, the source region and the substrate region will be in poor contact due to the contact between the source region and the substrate region, thereby reducing the reliability of the semiconductor device. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device and a preparation method thereof to improve the reliability of the semiconductor device.

[0005] In order to achieve the purpose of the present application, the following technical solutions are adopted in the present application:

[0006] A semiconductor device comprises:

[0007] A semiconductor substrate comprising an active region, the semiconductor substrate having a first conductivity type;

[0008] A gate structure disposed on the active region;

[0009] A ring-shaped isolation structure disposed on the active region and surrounding the gate structure;

[0010] The active region outside the ring-shaped isolation structure comprises a body region doped with the first conductivity type, the active region on both sides of the gate structure comprises a source-drain region doped with a second conductivity type, and the source-drain regions on both sides of the gate structure are spaced apart by the gate structure.

[0011] The body region and the source-drain region are electrically isolated by the ring-shaped isolation structure, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0012] In one of the embodiments, the ring-shaped isolation structure is an open ring-shaped isolation structure; and the semiconductor device further comprises:

[0013] a first gate lead-out structure disposed on the semiconductor substrate and connected with the gate structure, the first gate lead-out structure extending to outside of the active region through the opening of the ring-shaped isolation structure.

[0014] In one of the embodiments, the semiconductor substrate further comprises a trench isolation region surrounding the periphery of the active region;

[0015] the opening end of the ring-shaped isolation structure extends to or is adjacent to and contacts the trench isolation region.

[0016] In one of the embodiments, the ring-shaped isolation structure is a closed ring-shaped isolation structure.

[0017] In one of the embodiments, the semiconductor device further comprises:

[0018] a second gate lead-out structure comprising a lead-out portion and a connecting portion, the lead-out portion being disposed on the semiconductor substrate outside of the active region, the connecting portion being connected with the gate structure and connecting with the lead-out portion by bypassing the ring-shaped isolation structure, the connecting portion being electrically insulated from the ring-shaped isolation structure.

[0019] In one of the embodiments, the gate structure is a ring-shaped gate structure; and the semiconductor device further comprises:

[0020] a first conductive structure disposed on the source-drain region for leading out the source-drain region;

[0021] a second conductive structure disposed on the body region for leading out the body region;

[0022] wherein the source-drain region comprises a drain region in the active region surrounded by the gate structure and a source region in the active region between the gate structure and the ring-shaped isolation structure; and the first conductive structure comprises:

[0023] a drain region conductive structure disposed on the drain region for leading out the drain region;

[0024] a source region conductive structure disposed on the source region for leading out the source region.

[0025] In one of the embodiments, the active region, the gate structure and the ring-shaped isolation structure have the same symmetry axis.

[0026] In one of the embodiments, the ring-shaped isolation structure is a circular ring structure, an elliptical ring structure or a polygonal ring structure.

[0027] A method for manufacturing a semiconductor device, comprising:

[0028] providing a semiconductor substrate having a first conductivity type, and forming an active region on the semiconductor substrate;

[0029] forming a gate structure and a ring-shaped isolation structure on the active region;

[0030] performing a second conductivity type doping in the active region on both sides of the gate structure to form a source-drain region;

[0031] performing a first conductivity type doping in the active region outside the ring-shaped isolation structure to form a body region, the body region being electrically isolated from the source-drain region by the ring-shaped isolation structure, the first conductivity type and the second conductivity type being opposite conductivity types.

[0032] In one embodiment, the providing a semiconductor substrate having a first conductivity type, and forming an active region on the semiconductor substrate further comprises forming a trench isolation region around the active region while forming the active region on the semiconductor substrate;

[0033] The forming a gate structure and a ring-shaped isolation structure on the active region further comprises forming a ring-shaped isolation structure with an opening on the active region outside a closed ring-shaped gate structure while forming the closed ring-shaped gate structure on the active region, the opening end of the ring-shaped isolation structure extending onto or adjacent to and contacting the trench isolation region.

[0034] In one embodiment, the providing a semiconductor substrate having a first conductivity type, and forming an active region on the semiconductor substrate further comprises forming a trench isolation region around the active region while forming the active region on the semiconductor substrate;

[0035] The forming a gate structure and a ring-shaped isolation structure on the active region further comprises forming a closed ring-shaped isolation structure on the active region outside a closed ring-shaped gate structure while forming the closed ring-shaped gate structure on the active region.

[0036] In one embodiment, the performing a second conductivity type doping in the active region on both sides of the gate structure to form a source-drain region further comprises:

[0037] The source-drain region comprises a source region and a drain region, the drain region being formed by performing a second conductivity type doping in the active region enclosed by the ring-shaped gate structure, and the source region being formed by performing a second conductivity type doping in the active region between the ring-shaped gate structure and the ring-shaped isolation structure.

[0038] The semiconductor device and the preparation method thereof provided above, wherein the semiconductor device comprises a semiconductor substrate, a ring-shaped isolation structure and a gate structure, the semiconductor substrate comprises an active region, the gate structure is located on the active region, and the ring-shaped isolation structure is located on the active region and surrounds the gate structure. The active region outside the periphery of the ring-shaped isolation structure comprises a body region doped with a first conductive type, the active region on both sides of the gate structure comprises a source-drain region doped with a second conductive type, and the source-drain regions on both sides of the gate structure are spaced apart by the gate structure; the body region and the source-drain region are electrically isolated by the ring-shaped isolation structure. The ring-shaped isolation structure can separate the source-drain region and the body region to be independent of each other, avoiding direct contact, so that the source-drain region and the body region can be provided with independent contact structures in the subsequent process, ensuring the contact effect and improving the reliability of the semiconductor device. At the same time, the ring-shaped isolation structure can achieve the electrical isolation performance between the source-drain region and the body region, further improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 It is a schematic diagram of the cross-sectional structure of the semiconductor device in an embodiment;

[0040] Figure 2 It is a schematic diagram of the cross-sectional structure of the semiconductor device in an embodiment;

[0041] Figure 3 It is a schematic diagram of the planar structure of the ring-shaped isolation structure in an embodiment;

[0042] Figure 4 It is a schematic diagram of the planar structure of the ring-shaped isolation structure in an embodiment;

[0043] Figure 5 It is a schematic diagram of the planar structure of the ring-shaped isolation structure in an embodiment;

[0044] Figure 6 It is a schematic diagram of the cross-sectional structure of the semiconductor device in an embodiment;

[0045] Figure 7 It is a schematic diagram of the planar structure of the gate structure in an embodiment;

[0046] Figure 8 It is a schematic diagram of the planar structure of the semiconductor device in an embodiment;

[0047] Figure 9 It is Figure 8 It is a schematic diagram of the cross-sectional structure of the semiconductor device in an embodiment;

[0048] Figure 10 It is a schematic diagram of the planar structure of the semiconductor device in an embodiment;

[0049] Figure 11 It is Figure 10A cross-sectional structure schematic diagram of the EE' direction of the semiconductor device in an embodiment;

[0050] Figure 12 A planar structure schematic diagram of the semiconductor device in an embodiment;

[0051] Figure 13 A planar structure schematic diagram of the semiconductor device in an embodiment;

[0052] Figure 14 A planar structure schematic diagram of the semiconductor device in an embodiment; Figure 13 A cross-sectional structure schematic diagram of the EE' direction of the semiconductor device in an embodiment;

[0053] Figure 15 A planar structure schematic diagram of the semiconductor device in an embodiment;

[0054] Figure 16 A planar structure schematic diagram of the semiconductor device in an embodiment; Figure 15 A cross-sectional structure schematic diagram of the EE' direction of the semiconductor device in an embodiment;

[0055] Figure 17 A planar structure schematic diagram of the semiconductor device in an embodiment;

[0056] Figure 18 A planar structure schematic diagram of the semiconductor device in an embodiment; Figure 17 A cross-sectional structure schematic diagram of the FF' direction of the semiconductor device in an embodiment;

[0057] Figure 19 A method flow chart of the preparation method of the semiconductor device in an embodiment. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application can be more thoroughly and completely understood.

[0059] It can be understood that the terms "first", "second", and the like used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0060] It should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like are used herein for ease of description to indicate one orientation or position relative to the method or position shown in the drawings, and are merely intended to facilitate the description and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting of the application.

[0062] Figure 1 A structure schematic diagram of a semiconductor device is shown in the figure. The semiconductor device 10 includes a semiconductor substrate 100, a ring isolation structure 200, and a gate structure (not shown in the figure).

[0063] In the embodiment, the semiconductor substrate 100 includes an active area AA, the semiconductor substrate 100 has a first conductive type; a gate structure is disposed on the active area AA; and the ring isolation structure is disposed on the active area AA and surrounds the gate structure.

[0064] In the embodiment, the semiconductor substrate 100 includes an active area AA, the semiconductor substrate 100 has a first conductive type; a gate structure is disposed on the active area AA; and the ring isolation structure is disposed on the active area AA and surrounds the gate structure.

[0065] In the embodiment, the semiconductor substrate 100 includes an active area AA, the semiconductor substrate 100 has a first conductive type; a gate structure is disposed on the active area AA; and the ring isolation structure is disposed on the active area AA and surrounds the gate structure. Figure 2 As shown in the figure, the semiconductor substrate 100 includes a substrate 101, an insulating buried layer 102, and a semiconductor layer 103. The insulating buried layer 102 is implanted in the substrate 101, and the semiconductor layer 103 is disposed on the side of the substrate 101 close to the insulating buried layer 102. In the embodiment, the semiconductor device is an SOI (Silicon-On-Insulator) device, the substrate 101 is a silicon substrate, the insulating buried layer 102 is an oxygen buried layer, and the semiconductor layer 103 is a top silicon layer.

[0066] As shown in the figure, the semiconductor substrate 100 includes a substrate 101, an insulating buried layer 102, and a semiconductor layer 103. The insulating buried layer 102 is implanted in the substrate 101, and the semiconductor layer 103 is disposed on the side of the substrate 101 close to the insulating buried layer 102. In the embodiment, the semiconductor device is an SOI (Silicon-On-Insulator) device, the substrate 101 is a silicon substrate, the insulating buried layer 102 is an oxygen buried layer, and the semiconductor layer 103 is a top silicon layer. Figure 2As shown, the active region AA is disposed on the semiconductor layer 103 of the semiconductor substrate 100, and includes source-drain regions AA10 on both sides of the gate structure, a body region AA20 outside the ring-shaped isolation structure, a channel region (not shown in the figure) having a top surface provided with the gate structure, and a ring-shaped isolation region AA30 having a top surface provided with the ring-shaped isolation structure 200, so that the body region AA20 surrounds the source-drain regions AA10, and the channel region between the source-drain regions AA10 on both sides of the gate structure is in the active region AA, which can avoid the influence of the radiation effect.

[0067] The source-drain regions AA10 are formed by doping of the second conductive type, and the body region AA20 is formed by doping of the first conductive type. The source-drain regions AA10 and the body region AA20 can be doped by self-aligned implantation, so that no ions are implanted in the channel region and the ring-shaped isolation region AA30, ensuring complete isolation of the source-drain regions AA10 and the body region AA20.

[0068] The second conductive type and the first conductive type are one of P-type and N-type, and the other is N-type. One of the first conductive type doping and the second conductive type doping is P Plus type, and the other is N Plus type. The P Plus type doping ions include but are not limited to P-type ions such as boron ions and fluoroborane ions, and the N Plus type doping ions include but are not limited to N-type ions such as phosphorus ions and arsenic ions.

[0069] The doping types of the source-drain regions AA10 and the body region AA20 are selected according to the specific type of the device. For a PMOS device, the source-drain doping is P Plus, and the body contact doping is N Plus; for an NMOS device, the source-drain doping is N Plus, and the body contact doping is P Plus.

[0070] In the embodiment, the ring-shaped isolation structure 200 is disposed on the active region AA and surrounds the gate structure.

[0071] A first projection region of the ring-shaped isolation structure 200 in the active region AA is located between the source-drain regions AA10 and the body region AA20, and the ring-shaped isolation structure 200 is used to isolate the source-drain regions AA10 and the body region AA20.

[0072] The first projection area of the annular isolation structure 200 is located between the source-drain region AA10 and the body region AA20, so that the source-drain region AA10 and the body region AA20 are spaced apart to be independently arranged, and direct contact is avoided, so that the source-drain region AA10 and the body region AA20 can be provided with independent contact structures to ensure the contact effect; at the same time, the annular isolation structure 200 electrically isolates the source-drain region AA10 and the body region AA20. It should be noted that the orthographic projection of the annular isolation structure 200, the source-drain region AA10 and the body region AA20 on the projection area of the insulating buried layer 102 does not coincide, so as to ensure that the source-drain region AA10 and the body region AA20 are completely independent in the semiconductor substrate 100.

[0073] The annular isolation structure 200 can include an insulating layer arranged on the active region AA and a polysilicon layer arranged on the insulating layer, and the orthographic projection area of the insulating layer on the active region AA is the first projection area, so that the insulating layer divides the active region AA into the source-drain region AA10 and the body region AA20, so as to achieve the effect of isolating the source-drain region AA10 and the body region AA20; at the same time, the annular isolation structure 200 can be prepared at the same time as the gate structure, so as to simplify the process and improve the preparation efficiency.

[0074] In some embodiments, the annular isolation structure 200 includes an open ring structure or a closed ring structure. The open ring structure can be a circular open ring structure, an elliptical open ring structure or a polygonal open ring structure, for example, a three-edge open ring (for example, as shown in FIG. 3, only the annular isolation structure is shown in the figure, with an adjacent edge included angle of 90°), a five-edge open ring (for example, as shown in FIG. 4, only the annular isolation structure is shown in the figure, with an adjacent edge included angle of 90°) or other polygonal open ring structures. Figure 3 The closed ring structure can be a circular closed ring structure, an elliptical closed ring structure or a polygonal closed ring structure, for example, a four-edge closed ring structure (for example, as shown in FIG. 5, only the annular isolation structure is shown in the figure, with an adjacent edge included angle of 90°). Figure 4 Figure 5 In some embodiments, the first surface of the annular isolation structure 200 away from the semiconductor substrate 100 side is flush with the second surface of the gate structure away from the semiconductor substrate side, that is, the thickness of the annular isolation structure 200 is the same as that of the gate structure, so as to facilitate planarization in the subsequent preparation process, and to simplify the process to reduce the preparation cost and preparation time.

[0075] In the embodiment, the gate structure is arranged on the active region AA.

[0076] In the embodiment, the gate structure is arranged on the active region AA.

[0077] ​The gate structure is surrounded by an annular isolation structure 200, and the gate structure and the annular isolation structure 200 are spaced apart, so that the gate structure and the annular isolation structure 200 are independent of each other and do not affect each other. The preset distance of the spacing is not limited and can be adjusted according to the actual layout area requirements.

[0078] In some embodiments, such as Figure 6 As shown, the source and drain regions AA10 on both sides of the gate structure are spaced apart by the gate structure. The source and drain regions AA10 include the drain region AA11 within the active region AA10 surrounded by the gate structure and the source region AA12 within the active region AA10 between the gate structure and the annular isolation structure 200. The gate structure 300 is annular, and the second projection area of ​​the gate structure 300 projected onto the active region AA is located between the drain region AA11 and the source region AA12. The gate structure 300 is used to separate the drain region AA11 and the source region AA12. Thus, the gate structure 300 and the annular isolation structure 200 form a double-ring structure disposed on the active region AA, which can effectively separate the drain region AA11 and the source region AA12, and effectively electrically isolate the source region AA12 from the body region AA20. At the same time, it also makes the drain region AA11, the source region AA12, and the body region AA20 independently disposed, avoiding mutual contact and further improving the contact effect when each region is led out.

[0079] In some embodiments, the gate structure 300 is a ring structure, and the active region AA, the gate structure 300 and the ring isolation structure 200 have the same axis of symmetry. This allows the double-ring structure to divide the symmetrical active region AA into multiple symmetrical regions, including a symmetrical drain region AA11, a symmetrical source region AA12 and a symmetrical body region AA20. This allows for the acquisition of two symmetrically arranged semiconductor devices, which facilitates layout design and effectively utilizes area while reducing manufacturing costs.

[0080] In some embodiments, the gate structure 300 includes an insulating layer disposed on the active region AA and a doped polysilicon layer disposed on the insulating layer. The orthogonal projection region of the insulating layer onto the active region AA is the channel region AA40. The insulating layer separates the drain region and the source region AA12 so that they are independently disposed, avoiding direct contact. Therefore, the drain region AA11 and the source region AA12 can have independent contact structures, further ensuring contact effectiveness. The doping type of the doped polysilicon layer is the same as the doping type of the source / drain regions AA10, and opposite to the doping type of the body region AA20.

[0081] In some embodiments, the gate structure may be a circular ring structure, an elliptical ring structure, or a polygonal ring structure, and is not limited thereto. For example, Figure 7As shown, the gate structure 300 can be an octagonal ring structure, and in order to facilitate layout drawing and process manufacturing, the included angle between two adjacent sides of the octagonal ring structure is set to 135°.

[0082] In some embodiments, as shown in FIG. 2A, the semiconductor device further comprises a first gate lead-out structure 400 for leading out the gate structure 300. Figure 8 and Figure 9 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 8 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 4 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 9 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 8 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example,

[0083] For example, the material of the first gate lead-out structure 400 is the same as that of the gate structure 300, and the upper surface of the first gate lead-out structure 400 is flush with the upper surface of the gate structure 300, that is, the upper thickness of the first gate lead-out structure 400 is the same as the thickness of the gate structure 300. Thus, in the preparation, the first gate lead-out structure 400 and the gate structure 300 can be prepared integrally, and then patterned to obtain.

[0084] Further, in some embodiments, the semiconductor substrate 100 further comprises a trench isolation region B1 surrounding the periphery of the active region AA.

[0085] As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 10 and Figure 11 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 10 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 4 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 11 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 10 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 12 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 12 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example, Figure 4 As shown in FIG. 2A, the shape of the annular isolation structure in the ring isolation structure 200 is taken as an example,

[0086] The first gate lead-out structure 400 can be T-shaped, with the horizontal end of the T-shape being the lead-out part (401 in the figure), which is located in the trench isolation region B1 and is used to lead out the gate structure 300; the vertical end of the T-shape is the connecting part (402 in the figure), which is used to connect to the gate structure 300 and the lead-out part respectively.

[0087] In some embodiments, such as Figure 13 and Figure 14 As shown ( Figure 13 The ring-shaped isolation structure in Figure 5 Taking the shape shown as an example, Figure 14 for Figure 13 (In a cross-sectional view along the EE' direction), when the annular isolation structure 200 is a closed annular isolation structure, the semiconductor device further includes a second gate lead-out structure 500 for leading out the gate structure 300. The second gate lead-out structure 500 includes a lead-out portion 501 and a connecting portion 502. The lead-out portion 501 is disposed on the semiconductor substrate 100 and located outside the active region AA. The connecting portion 502 is connected to the gate structure 300 and bypasses the annular isolation structure 200 to connect to the lead-out portion 501. The connecting portion 502 is electrically insulated from the annular isolation structure 200. By disposing of the second gate lead-out structure 500 on the semiconductor substrate 100 and leading out the gate structure 300 by bypassing the annular isolation structure 200, the area occupied by the second gate lead-out structure 500 on the semiconductor substrate 100 can be reduced. This effectively utilizes the area of ​​the active region AA to expand the area occupied by the annular isolation structure 200, thereby expanding the area of ​​the body region AA20.

[0088] Furthermore, in some embodiments, such as Figure 15 and Figure 16 ( Figure 15 The ring-shaped isolation structure in Figure 5 Taking the shape shown as an example, Figure 16 for Figure 15 As shown in the cross-sectional view in the EE' direction, the semiconductor substrate 100 also includes a trench isolation region B2 surrounding the active region AA.

[0089] The lead-out portion 501 is disposed on the trench isolation region B2, and the connecting portion 502 extends from the gate structure 300 of the active region AA, bypasses the annular isolation structure 200, and crosses to the trench isolation region B2 to connect with the lead-out portion 501.

[0090] The connecting part 502 can be in the shape of an arch, an inverted U, or an inverted V. Figure 14 and Figure 16 Taking an inverted U-shape as an example, an arched, inverted U-shaped, or inverted V-shaped structure is advantageous for the connecting part to bypass the annular isolation structure 200 and connect to the lead-out part 501 with a shorter distance.

[0091] It should be noted that both the trench isolation region B1 and the trench isolation region B2 mentioned above can be used to further isolate and protect the active region AA by setting a trench isolation structure. The trench isolation structure can be a shallow trench isolation structure; for example, a shallow trench isolation structure is disposed in the semiconductor layer 103 of the semiconductor substrate 100. For a thicker semiconductor layer 103, the shallow trench isolation structure can extend to the interface between the semiconductor layer 103 and the buried insulating layer 102; for a thinner semiconductor layer 103, the shallow trench isolation structure can extend to the buried insulating layer 102.

[0092] In some embodiments, when the annular isolation structure 200 is a closed annular isolation structure, the gate structure 300 can also lead out the gate structure 300 by providing a through hole above the gate structure 300 and filling it with conductive material, thereby effectively reducing the area occupied by the lead-out structure on the semiconductor substrate 100, and thus effectively utilizing the area of ​​the active region AA to expand the area occupied by the annular isolation structure 200, thereby expanding the area of ​​the body region AA20.

[0093] In some embodiments, such as Figure 17 and Figure 18 As shown ( Figure 17 The ring-shaped isolation structure in Figure 4 Taking the shape as an example, Figure 18 for Figure 17 In the cross-sectional view along the EE' direction (where B is the trench isolation region), the semiconductor device also includes a first conductive structure 600 and a second conductive structure 700.

[0094] The first conductive structure 600 is disposed on the source / drain region AA10 and is used to lead out the source / drain region AA10; the second conductive structure 700 is disposed on the body region AA20 and is used to lead out the body region AA20.

[0095] The first conductive structure 600 is used to connect with the first metal layer of the subsequently fabricated semiconductor device, thereby bringing out the source / drain region AA10; the second conductive structure 700 is used to connect with the first metal layer of the subsequently fabricated semiconductor device, thereby bringing out the body region AA20. Where the area of ​​the active region AA is permissible, the more first conductive structures 600 and second conductive structures 700 there are, the lower the equivalent resistance can be. For example, a planarization layer can be formed on the semiconductor substrate 100, the gate structure 300, and the annular isolation structure 200. Contact holes are etched on the planarization layer in the regions corresponding to the source / drain region AA10 and the body region AA20, and the contact holes are filled with a conductive dielectric to obtain the first conductive structure 600 and the second conductive structure 700.

[0096] In some embodiments, the source-drain region AA10 includes a drain region AA11 in the active region surrounded by the gate structure 300 and a source region AA12 in the active region between the gate structure 300 and the ring-shaped isolation structure 200; the first conductive structure 600 includes a drain region conductive structure 601 and a source region conductive structure 602.

[0097] The drain region conductive structure 601 is arranged in the drain region AA11 and is used to lead out the drain region AA11; the source region conductive structure 602 is arranged in the source region AA12 and is used to lead out the source region AA12.

[0098] The drain region conductive structure 601 is specifically used to connect the drain region with a first layer metal layer of a semiconductor device prepared subsequently, thereby leading out the drain region; the source region conductive structure 602 is specifically used to connect the source region AA12 with a first layer metal layer of a semiconductor device prepared subsequently, thereby leading out the source region AA12. In the case that the area of the source-drain region AA10 allows, the more the number of the drain region conductive structure 601 and the source region conductive structure, the lower the equivalent resistance. Exemplarily, a planarization layer can be arranged on the semiconductor substrate 100, the gate structure 300 and the ring-shaped isolation structure 200, a contact hole is etched on the region corresponding to the drain region and the source region AA12 on the planarization layer, and a conductive medium is filled in the contact hole to obtain the drain region conductive structure 601 and the source region conductive structure 602.

[0099] The gate structure 300 and the ring-shaped isolation structure 200 form a double-ring structure arranged on the active region AA, can effectively separate the drain region AA11 and the source region AA12, effectively isolate the source region AA12 and the body region AA20, so that the drain region AA11, the source region AA12 and the body region AA20 are independently arranged and do not contact each other; at the same time, the drain region conductive structure 601, the source region conductive structure 602 and the second conductive structure 700 on the body region AA20 can be effectively spaced, so that the drain region conductive structure 601, the source region conductive structure 602 and the second conductive structure 700 are independently arranged and do not contact each other, further improving the contact effect when leading out each region.

[0100] The semiconductor device provided by the embodiment comprises a semiconductor substrate 100, a ring-shaped isolation structure 200 and a gate structure 300, wherein the semiconductor substrate 100 comprises an active region AA, the gate structure 300 is arranged on the active region AA, and the ring-shaped isolation structure 200 is arranged on the active region AA and surrounds the gate structure 300. The active region AA outside the ring-shaped isolation structure comprises a body region AA20 doped with a first conductive type, the active region AA on both sides of the gate structure 300 comprises a source-drain region AA10 doped with a second conductive type, and the source-drain regions AA10 on both sides of the gate structure 300 are arranged at intervals through the gate structure 300; the body region AA20 and the source-drain region AA10 are electrically isolated through the ring-shaped isolation structure 200, and the first conductive type and the second conductive type are opposite conductive types. Through the arrangement of the ring-shaped isolation structure 200, the source-drain region AA10 and the body region AA20 can be spaced apart to be independent of each other, direct contact is avoided, and therefore the source-drain region AA10 and the body region AA20 can be provided with independent contact structures in the subsequent process, the contact effect is ensured, and the reliability of the semiconductor device is improved. Meanwhile, the arrangement of the ring-shaped isolation structure 200 achieves the electrical isolation performance between the source-drain region AA10 and the body region AA20, and further improves the reliability of the semiconductor device.

[0101] Figure 19 A preparation method of a semiconductor device of an embodiment is shown, which is used for preparing the semiconductor device described in the above embodiments, and comprises steps 101, 102 and 103.

[0102] Step 101: providing a semiconductor substrate, forming an active region on the semiconductor substrate, and the semiconductor substrate has a first conductive type.

[0103] It should be noted that the preparation method of the semiconductor substrate can be a conventional preparation method of a semiconductor substrate, and is not limited in the embodiment.

[0104] Step 102: forming a gate structure and a ring-shaped isolation structure on the active region.

[0105] It should be noted that the descriptions of the gate structure and the ring-shaped isolation structure are the same as the descriptions in the above embodiments, and are not repeated here.

[0106] Step 103: performing second conductive type doping in the active region on both sides of the gate structure to form a source-drain region.

[0107] It should be noted that the description of the source-drain region is the same as the description in the above embodiments, and is not repeated here.

[0108] In some embodiments, step 103 further comprises: forming a drain region by doping the active region surrounded by the gate structure with the second conductive type, and forming a source region by doping the active region between the gate structure and the ring-shaped isolation structure with the second conductive type.

[0109] Step 104: forming a body region by doping the active region outside the ring-shaped isolation structure with the first conductive type, the body region being electrically isolated from the source-drain region by the ring-shaped isolation structure, the first conductive type and the second conductive type being opposite conductive types.

[0110] In some embodiments, the source-drain region and the body region are formed by self-aligned ion implantation, so that no ions are implanted in the active region under the ring-shaped isolation structure and the gate structure, ensuring complete isolation of the source-drain region and the body region.

[0111] In some embodiments, the source-drain region and the body region are formed by self-aligned ion implantation, so that no ions are implanted in the active region under the ring-shaped isolation structure and the gate structure, ensuring complete isolation of the source-drain region and the body region.

[0112] The preparation method provided by the embodiment includes: forming an active region on a semiconductor substrate, forming a gate structure and a ring-shaped isolation structure on the active region, forming a source-drain region by doping the active region on both sides of the gate structure with a second conductive type, and forming a body region by doping the active region outside the ring-shaped isolation structure with a first conductive type, the body region being electrically isolated from the source-drain region by the ring-shaped isolation structure, the first conductive type and the second conductive type being opposite conductive types. The ring-shaped isolation structure can separate the source-drain region and the body region to be independent of each other, avoiding direct contact, so that the source-drain region and the body region can be provided with independent contact structures in the subsequent process, ensuring the contact effect and improving the reliability of the semiconductor device. At the same time, the ring-shaped isolation structure achieves the electrical isolation between the source-drain region and the body region, further improving the reliability of the semiconductor device.

[0113] In some embodiments, the gate structure includes a doped polysilicon layer, the ring-shaped isolation structure includes a polysilicon layer, and the gate structure and the ring-shaped isolation structure are flush, and step 102 can include step 201 and step 202.

[0114] Step 201: depositing a polysilicon layer on the active region, and performing a patterning process on the polysilicon layer to obtain a preform of the gate structure and the ring-shaped isolation structure. The patterning process can be photolithography and etching processing on the polysilicon layer.

[0115] Step 202: doping the preform of the gate structure to obtain the gate structure. The doping type of the preform is the same as the doping type of the source-drain region and opposite to the doping type of the body region, and step 201 can be performed simultaneously with step 103.

[0116] In some embodiments, the gate structure and the ring-shaped isolation structure each further comprises an insulating layer disposed on the source-drain region, and the polysilicon layer is disposed on the insulating layer, and step 102 further comprises step 200.

[0117] Step 200: Forming an insulating layer on the semiconductor substrate. The insulating layer can be a gate oxide layer, and the material of the gate oxide layer can be an oxide, a nitride, and an oxynitride of silicon; or can be hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate, and lead zirconium titanate; or can be other insulating materials.

[0118] In some embodiments, step 101 further comprises forming a trench isolation region around the active region while forming the active region on the semiconductor substrate; and step 102 further comprises forming an open ring-shaped isolation structure around the closed ring-shaped gate structure while forming the closed ring-shaped gate structure on the active region, the open ring-shaped isolation structure having an opening end extending onto or adjacent to the trench isolation region.

[0119] The descriptions of the trench isolation region, the closed ring-shaped gate structure, and the open ring-shaped isolation structure are the same as those in the above embodiments, and are not repeated here.

[0120] Further, when the ring-shaped isolation structure is an open ring-shaped isolation structure, the preparation method can further comprise step 105.

[0121] Step 105: Forming a first gate lead-out structure on the semiconductor substrate, the first gate lead-out structure being connected with the gate structure and extending to outside of the active region through the opening of the ring-shaped isolation structure.

[0122] The descriptions of the first gate lead-out structure are the same as those in the above embodiments, and are not repeated here.

[0123] For example, the material of the first gate lead-out structure is the same as that of the gate structure, such as both being doped polysilicon, and the first gate lead-out structure is flush with the gate structure, so that step 102 and step 104 can be performed simultaneously.

[0124] In some embodiments, step 101 further comprises forming a trench isolation region around the active region while forming the active region on the semiconductor substrate; and step 102 further comprises forming a closed ring-shaped isolation structure around the closed ring-shaped gate structure while forming the closed ring-shaped gate structure on the active region.

[0125] The descriptions of the trench isolation region, the closed ring-shaped gate structure, and the closed ring-shaped isolation structure are the same as those in the above embodiments, and are not repeated here.

[0126] Further, in some embodiments, when the ring isolation structure is a closed ring isolation structure, the preparation method can further include steps 106 and 107.

[0127] Step 106: forming a lead-out portion on the semiconductor substrate and outside the active region.

[0128] Step 107: forming a connecting portion connected with the lead-out portion and the gate structure respectively around the ring isolation structure to form a second gate lead-out structure.

[0129] For the second gate lead-out structure, refer to the related description in the above embodiments, which will not be repeated here.

[0130] For example, the material of the lead-out portion is the same as that of the gate structure, such as doped polysilicon, and the lead-out portion is flush with the gate structure, so that steps 102 and 106 can be performed simultaneously.

[0131] Further, in some embodiments, when the ring isolation structure is a closed ring isolation structure, the preparation method of the semiconductor device can further include: setting a via on the gate structure and filling a conductive material to lead out the gate structure, so that the occupation area of the lead-out structure on the semiconductor substrate can be effectively reduced, and the area of the active region can be effectively utilized to expand the occupation area of the ring isolation structure, thereby expanding the area of the body region.

[0132] In some embodiments, the semiconductor device further includes a first conductive structure and a second conductive structure, and the preparation method of the semiconductor device can further include step 108.

[0133] Step 108: setting a planarization layer on the semiconductor substrate, the gate structure and the ring isolation structure, etching a contact hole on the planarization layer corresponding to the source / drain region and the body region, and filling a conductive medium in the contact hole to obtain the first conductive structure and the second conductive structure.

[0134] For the first conductive structure and the second conductive structure, refer to the related description in the above embodiments, which will not be repeated here.

[0135] In some embodiments, the source / drain region includes a source region and a drain region, and the preparation method can further include step 109.

[0136] Step 109: setting a planarization layer on the semiconductor substrate, the gate structure and the ring isolation structure, etching a contact hole on the planarization layer corresponding to the drain region, the source region and the body region, and filling a conductive medium in the contact hole to obtain a drain conductive structure, a source conductive structure and a second conductive structure.

[0137] For the drain conductive structure and the source conductive structure, refer to the related description in the above embodiments, which will not be repeated here.

[0138] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, however, as long as the combinations of the technical features do not result in contradictions, they shall be considered as falling within the scope of the present disclosure.

[0139] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the scope of the patent right of the present application. It shall be pointed out that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall fall within the protection scope of the present application. Therefore, the protection scope of the patent right of the present application shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate including an active region, the semiconductor substrate having a first conductivity type; A gate structure is disposed on the active region; A ring-shaped isolation structure is disposed on the active region and surrounds the gate structure; the ring-shaped isolation structure includes an insulating layer disposed on the active region and a polysilicon layer disposed on the insulating layer; The active region surrounding the annular isolation structure includes a body region doped with the first conductivity type, and the active regions on both sides of the gate structure include source and drain regions doped with the second conductivity type. The source and drain regions on both sides of the gate structure are spaced apart by the gate structure. The body region and the source / drain region are located on opposite sides below the annular isolation structure. The body region and the source / drain region are electrically isolated by the annular isolation structure. The first conductivity type and the second conductivity type are opposite conductivity types.

2. The semiconductor device according to claim 1, characterized in that, The annular isolation structure is an annular isolation structure with an opening; The semiconductor device further includes: A first gate lead-out structure is disposed on the semiconductor substrate and connected to the gate structure, and the first gate lead-out structure extends through the opening of the annular isolation structure to the outside of the active region.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor substrate also includes a trench isolation region surrounding the active region; The open end of the annular isolation structure extends onto or is adjacent to and in contact with the trench isolation area.

4. The semiconductor device according to claim 1, characterized in that, The ring-shaped isolation structure is a closed ring-shaped isolation structure.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: The second gate lead-out structure includes a lead-out portion and a connecting portion. The lead-out portion is disposed on the semiconductor substrate outside the active region. The connecting portion is connected to the gate structure and bypasses the annular isolation structure to connect to the lead-out portion. The connecting portion is electrically insulated from the annular isolation structure.

6. The semiconductor device according to claim 1, characterized in that, The gate structure is a ring gate structure; the semiconductor device further includes: A first conductive structure is disposed on the source / drain region for leading out the source / drain region; A second conductive structure is disposed on the body region for leading out the body region; Wherein, the source / drain region includes a drain region within the active region surrounded by the gate structure and a source region within the active region between the gate structure and the annular isolation structure; the first conductive structure includes: A conductive structure is disposed in the drain region for leading out the drain region; A source region conductive structure is disposed in the source region for leading out the source region.

7. The semiconductor device according to claim 1, characterized in that, The active region, the gate structure, and the annular isolation structure have the same axis of symmetry.

8. The semiconductor device according to claim 1, characterized in that, The ring-shaped isolation structure can be a circular ring structure, an elliptical ring structure, or a polygonal ring structure.

9. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, on which an active region is formed, the semiconductor substrate having a first conductivity type; A gate structure and a ring-shaped isolation structure are formed on the active region; the ring-shaped isolation structure includes an insulating layer disposed on the active region and a polysilicon layer disposed on the insulating layer; A second conductivity type doping is performed in the active regions on both sides of the gate structure to form source and drain regions; A first conductivity type doping is performed in the active region surrounding the annular isolation structure to form a body region. The body region and the source / drain region are located on opposite sides below the annular isolation structure. The body region and the source / drain region are electrically isolated by the annular isolation structure. The first conductivity type and the second conductivity type are opposite conductivity types.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The provision of a semiconductor substrate, forming an active region on the semiconductor substrate, the semiconductor substrate having a first conductivity type, further includes: forming a trench isolation region around the active region while forming the active region on the semiconductor substrate; The method of forming a gate structure and annular isolation structure on the active region further includes: forming a closed annular gate structure on the active region while forming an open annular isolation structure on the active region surrounding the closed annular gate structure, wherein the open end of the annular isolation structure extends to or is adjacent to and in contact with the trench isolation region.

11. The method for fabricating a semiconductor device according to claim 9, characterized in that, The provision of a semiconductor substrate, forming an active region on the semiconductor substrate, the semiconductor substrate having a first conductivity type, further includes: forming a trench isolation region around the active region while forming the active region on the semiconductor substrate; The step of forming a gate structure and a ring isolation structure on the active region further includes: forming a closed ring gate structure on the active region while simultaneously forming a closed ring isolation structure on the active region surrounding the closed ring gate structure.

12. The method for fabricating a semiconductor device according to claim 9, characterized in that, The step of forming source / drain regions by doping with a second conductivity type in the active regions on both sides of the gate structure further includes: The source and drain regions include a source region and a drain region. The drain region is formed by doping with a second conductivity type within the active region surrounded by the gate structure, and the source region is formed by doping with a second conductivity type within the active region between the gate structure and the annular isolation structure.

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