Semiconductor device

Abstract

The application provides a semiconductor device. By arranging a first active layer on a substrate, a first insulating layer covering the first active layer, a first via hole on the first insulating layer, a second active layer on the first insulating layer, and a third active layer in the first via hole and connecting the first active layer and the second active layer, the channel length of the semiconductor device can be determined according to the thickness of the first insulating layer, the channel width of the semiconductor device can be determined according to the perimeter of the first via hole, the preparation of the semiconductor device with extremely small channel length is facilitated, and the mobility of the semiconductor device is improved. In addition, compared with the design mode that the first active layer, the second active layer and the third active layer are all arranged in the same plane, the semiconductor device has a smaller area, and the exposure precision and etching precision are avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a semiconductor device. BACKGROUND

[0002] To cope with the increase of the requirements of narrow frame, high aperture ratio, high resolution and other parameters, the space area occupied by the semiconductor device needs to be adjusted to be as small as possible. However, the existing active layer is placed in a plane, as shown in FIG. 1, which causes the semiconductor device to occupy a large area, and the channel length of the semiconductor device is greater than 1 micrometer due to the limitation of exposure accuracy and etching accuracy, which is not conducive to improving the mobility of the semiconductor device. Figure 1 SUMMARY

[0003] The embodiment of the present application provides a semiconductor device, which can reduce the occupied area of the semiconductor device and improve the mobility of the semiconductor device.

[0004] The embodiment of the present application provides a semiconductor device, which comprises a substrate, a first active layer, a first insulating layer and a second active layer. The first active layer is located on the substrate, and the first insulating layer covers the first active layer; the second active layer is located on the first insulating layer. Wherein, the first insulating layer is provided with a first via hole, a third active layer is located in the first via hole, and the third active layer connects the first active layer and the second active layer.

[0005] Optionally, in some embodiments of the present application, the semiconductor device further comprises a first conductive layer, the first conductive layer is located in the first insulating layer, the first conductive layer comprises a gate, and the gate is provided with a first opening. Wherein, in the top view, the first via hole is located in the first opening.

[0006] Optionally, in some embodiments of the present application, the third active layer comprises a main body part and an extension part. The main body part is located in the first via hole, and the extension part is connected to the main body part and located between the second active layer and the first insulating layer. Wherein, in the top view, the boundary of the main body part on the extension part is located in the boundary of the extension part.

[0007] Optionally, in some embodiments of the present application, in the top view, the extension part partially overlaps with the gate.

[0008] Optionally, in some embodiments of the present application, the distance between the boundary of the extension part and the boundary of the main body part is greater than or equal to 0.5 micrometer and less than or equal to 5 micrometers.

[0009] ​Optionally, in some embodiments of the present application, the first insulating layer comprises a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer covers the first active layer, and the second sub-insulating layer covers the first conductive layer. The second active layer is located on the second sub-insulating layer.

[0010] Optionally, in some embodiments of the present application, the semiconductor device further comprises a second conductive layer and a second insulating layer. The second conductive layer is located between the substrate and the first active layer, and the second conductive layer comprises a first electrode. The second insulating layer covers the second conductive layer, and the second insulating layer is provided with a second via. The first active layer is electrically connected to the first electrode through the second via.

[0011] Optionally, in some embodiments of the present application, the semiconductor device further comprises a third insulating layer and a third conductive layer. The third insulating layer covers the second active layer, and the third insulating layer is provided with a third via. The third conductive layer is located on the third insulating layer, and the third conductive layer comprises a second electrode and an electrode connecting portion spaced apart from the second electrode. The second electrode is electrically connected to the second active layer through the third via, and the electrode connecting portion is electrically connected to the first electrode through a fourth via penetrating through the third insulating layer, the first insulating layer and the second insulating layer.

[0012] Optionally, in some embodiments of the present application, the first electrode comprises a first electrode portion, a second electrode portion and a third electrode portion connected between the first electrode portion and the second electrode portion. In a top view, the first electrode portion partially overlaps the first active layer, and the second electrode portion partially overlaps the electrode connecting portion.

[0013] Optionally, in some embodiments of the present application, the width of the third electrode portion is smaller than the width of the second electrode portion, and the width of the second electrode portion is smaller than the width of the first electrode portion.

[0014] Optionally, in some embodiments of the present application, the first via is frustoconical.

[0015] Optionally, in some embodiments of the present application, the present application further provides an array substrate comprising any of the above semiconductor devices.

[0016] Optionally, in some embodiments of the present application, the present application further provides a driving chip comprising any of the above semiconductor devices.

[0017] Optionally, in some embodiments of the present application, the present application further provides a display panel comprising any of the above semiconductor devices.

[0018] Optionally, in some embodiments of the present application, the present application further provides a display device, which comprises any of the above semiconductor devices.

[0019] The present application provides a semiconductor device. By locating a first active layer on a substrate, covering the first active layer with a first insulating layer, and providing a first via on the first insulating layer, locating a second active layer on the first insulating layer, locating a third active layer in the first via, and connecting the first active layer and the second active layer with the third active layer, the channel length of the semiconductor device can be determined according to the thickness of the first insulating layer, the channel width of the semiconductor device can be determined according to the perimeter of the first via, which is conducive to the preparation of a semiconductor device with an extremely small channel length, thereby improving the mobility of the semiconductor device. In addition, since the third active layer is located in the first via and connects the first active layer and the second active layer, compared with the design in which the first active layer, the second active layer, and the third active layer are located in the same plane, the present application can reduce the occupied area of the semiconductor device, and avoid the limitations of exposure accuracy and etching accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a structural schematic diagram of a semiconductor device in the prior art;

[0022] Figures 2A-2D is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0023] Figure 3 is a flowchart of a preparation process of a semiconductor device provided by an embodiment of the present application;

[0024] Figures 4A-4I is a schematic diagram of a preparation process of a semiconductor device provided by an embodiment of the present application;

[0025] Figures 5A-5B is a structural schematic diagram of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0027] Specifically, as Figures 2A-2D FIG. 1 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application. The present application provides a semiconductor device, which comprises a substrate 100, a first insulating layer 101, a first active layer Np1, a second active layer Np2 and a third active layer Ch.

[0028] Optionally, the substrate 100 comprises a flexible substrate and a rigid substrate. Optionally, the substrate 100 comprises glass, polyimide, etc.

[0029] The first active layer Np1 is located on the substrate 100.

[0030] The first insulating layer 101 covers the first active layer Np1, and the first insulating layer 101 is provided with a first via hole H1. Optionally, the first insulating layer 101 comprises a silicon compound, a metal oxide, etc. Optionally, the first insulating layer 101 comprises silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. Optionally, the first insulating layer 101 can be a single-layer film layer structure, or a laminated structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0031] The second active layer Np2 is located on the first insulating layer 101.

[0032] The third active layer Ch is located in the first via hole H1, and the third active layer Ch connects the first active layer Np1 and the second active layer Np2, so that the channel length of the semiconductor device is determined by the thickness of the first insulating layer 101, and the channel width of the semiconductor device is equal to the circumference of the first via hole H1, which is beneficial to the preparation of a semiconductor device with extremely small channel length, thereby also being beneficial to the improvement of the mobility of the semiconductor device.

[0033] Optionally, the first active layer Np1 and the second active layer Np2 at least partially overlap, the third active layer Ch is located within the first via H1, and the third active layer Ch is located between the overlapping portions of the first active layer Np1 and the second active layer Np2, and the first via H1 is completely filled by the third active layer Ch, thereby giving the semiconductor device a shorter channel length.

[0034] Because in the existing technology, the first active layer, the second active layer, and the third active layer are all located on the same horizontal plane (i.e., as shown in the figure). Figure 1 As shown in the diagram, the channel length of a semiconductor device is determined by the width of the gate G. Therefore, during the fabrication of the semiconductor device, exposure accuracy and etching accuracy limit the channel length. However, in this application, since the third active layer Ch is located within the first via H1, the channel length of the semiconductor device is determined by the thickness of the first insulating layer 101. Therefore, the channel length of the semiconductor device is not limited by exposure accuracy and etching accuracy, and the channel length can reach 0.1 μm to 1 μm, significantly smaller than the channel length greater than 1 μm in existing designs. That is, the channel length of the semiconductor device can reach 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm.

[0035] Furthermore, compared to the prior art design where the first, second, and third active layers are all located on the same horizontal plane, the third active layer Ch in this application is located within the first opening H1 and connected to the first active layer Np1 and the second active layer Np2. Therefore, from a top-view perspective, the first active layer Np1, the second active layer Np2, and the third active layer Ch at least partially overlap, thus reducing the area occupied by the semiconductor device. Additionally, in the thickness direction of the semiconductor device, since the first active layer Np1, the second active layer Np2, and the third active layer Ch are located between different film layers, the degree of mutual interference between the first active layer Np1, the second active layer Np2, and the third active layer Ch can be reduced during the fabrication of the semiconductor device.

[0036] It can be understood that when the top surface of the third active layer Ch is flush with the top surface of the first insulating layer 101, the channel length of the semiconductor device is less than or equal to the thickness of the first insulating layer 101, that is, the channel length of the semiconductor device is equal to the depth of the first via H1.

[0037] Optionally, the first via hole H1 is in a frustum shape or in a frustum shape with steps. Optionally, in a direction from the first active layer Np1 to the second active layer Np2, the width of the first via hole H1 gradually increases to reduce the process difficulty. It can be understood that the first via hole H1 can also be in a prism shape.

[0038] Please continue to refer to Figures 2A-2C The semiconductor device further includes a first conductive layer 102 located in the first insulating layer 101. The first conductive layer 102 includes a gate G of the semiconductor device, and the gate G is provided with a first opening A1. Wherein, in a top view, the first via hole H1 is located in the first opening A1, so that the gate G is provided corresponding to the third active layer Ch. The first conductive layer 102 and the first active layer Np1, the second active layer Np2 and the third active layer Ch are insulated by the first insulating layer 101.

[0039] Optionally, the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), tungsten (W), etc. Optionally, the first conductive layer 102 can be a single-layer film layer structure, or a Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb laminated structure.

[0040] Optionally, the first opening A1 is in a frustum shape, a prism shape, etc. Optionally, the size of the first opening A1 is greater than or equal to 0.5 microns and less than or equal to 15 microns. Optionally, the size of the first opening A1 is greater than or equal to 1 micron and less than or equal to 10 microns. Optionally, the size of the first opening A1 is equal to 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1 micron, 5 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns or 15 microns.

[0041] Optionally, please continue to refer to Figure 2BThe third active layer Ch includes a main body part Ch1 and an extension part Ch2. The main body part Ch1 is located in the first via hole H1, and the extension part Ch2 is connected to the main body part Ch1 and located between the second active layer Np2 and the first insulating layer 101, so as to increase the contact effect of the third active layer Ch and the second active layer Np2; and / or the extension part Ch2 is connected to the main body part Ch1 and located between the first active layer Np1 and the first insulating layer 101, so as to increase the contact effect of the third active layer Ch and the first active layer Np1. In a top view, the projection of the boundary of the main body part Ch1 on the extension part Ch2 is located within the boundary of the extension part Ch2.

[0042] Optionally, in a top view, the extension part Ch2 partially overlaps with the gate G, so as to increase the control area of the gate G and the third active layer Ch, and facilitate to improve the control ability of the gate. It can be understood that, in order to avoid short circuit between the extension part Ch2 and the gate G, the extension part Ch2 overlaps with the gate G through the first insulating layer 101.

[0043] Optionally, the distance P between the boundary of the extension part Ch2 and the boundary of the main body part Ch1 is greater than or equal to 0.5 microns and less than or equal to 5 microns, so as to increase the contact effect of the third active layer Ch and the second active layer Np2 and / or the first active layer Np1. Optionally, the distance P between the boundary of the extension part Ch2 and the boundary of the main body part Ch1 is equal to 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns or 5 microns. Optionally, the distance P between the boundary of the extension part Ch2 and the boundary of the main body part Ch1 is greater than or equal to 1 micron and less than or equal to 3 microns.

[0044] Optionally, the distance between the main body part Ch1 and the gate G is greater than or equal to 0.05 microns and less than or equal to 2 microns. Optionally, the distance between the main body part Ch1 and the gate G is equal to 0.05 microns, 0.06 microns, 0.07 microns, 0.08 microns, 0.09 microns, 0.1 microns, 0.15 microns, 0.2 microns, 0.5 microns, 1 micron, 1.2 microns, 1.5 microns, 1.8 microns or 2 microns.

[0045] Optionally, the extension Ch2 can be located in the first via H1, i.e. the first via H1 includes a first sub-via and a second sub-via which are in communication in the thickness direction of the semiconductor device, the size of the second sub-via is larger than that of the first sub-via, the main body Ch1 is located in the first sub-via, and the extension Ch2 is located in the second sub-via. In addition, the extension Ch2 can also be located on the first insulating layer 101, as shown in Figure 2C so that the extension Ch2 is located between the main body Ch1 and the second active layer Np1; and / or the extension Ch2 can also be located under the first insulating layer 101, so that the extension Ch2 is located between the main body Ch1 and the first active layer Np1.

[0046] Optionally, in order to ensure that there is no short circuit problem between the first active layer Np1, the second active layer Np2 and the gate G, the first insulating layer 101 includes a first sub-insulating layer 1011 and a second sub-insulating layer 1012. The first sub-insulating layer 1011 covers the first active layer Np1, the second sub-insulating layer 1012 covers the first conductive layer 102, the second active layer Np2 is located on the second sub-insulating layer 1012, and the first via H1 penetrates the first sub-insulating layer 1011 and the second sub-insulating layer 1012.

[0047] It can be understood that the thicker the thickness of the first conductive layer 102 and the first insulating layer 101, the longer the channel length of the semiconductor device, and in order to reduce the channel length of the semiconductor device, the film thickness of the first conductive layer 102 is greater than or equal to 0.05 microns and less than or equal to 1 micron; the thickness of the first sub-insulating layer 1011 is greater than or equal to 0.05 microns and less than or equal to 0.5 microns; and the thickness of the second sub-insulating layer 1012 is greater than or equal to 0.05 microns and less than or equal to 0.5 microns.

[0048] Optionally, the film thickness of the first conductive layer 102 is equal to 0.05 microns, 0.08 microns, 0.1 microns, 0.15 microns, 0.2 microns, 0.25 microns, 0.3 microns, 0.4 microns, 0.45 microns, 0.5 microns, 0.55 microns, 0.6 microns, 0.65 microns, 0.7 microns, 0.8 microns, 0.9 microns, 0.95 microns or 1 micron.

[0049] Optionally, the thickness of the first sub-insulating layer 1011 is equal to 0.05 microns, 0.06 microns, 0.08 microns, 0.1 microns, 0.15 microns, 0.2 microns, 0.25 microns, 0.3 microns, 0.4 microns, 0.45 microns, 0.48 microns, 0.5 microns.

[0050] Optionally, the thickness of the second sub-insulating layer 1012 is equal to 0.05 microns, 0.06 microns, 0.08 microns, 0.1 microns, 0.15 microns, 0.2 microns, 0.25 microns, 0.3 microns, 0.4 microns, 0.45 microns, 0.48 microns, or 0.5 microns.

[0051] Optionally, the semiconductor device includes a field effect semiconductor device, a thin film semiconductor device, or the like.

[0052] In subsequent applications of the semiconductor device, the first active layer Np1 and the second active layer Np2 need to be connected with corresponding signal lines or devices (for example, the first active layer Np1 can be electrically connected with a pixel electrode or a light emitting device, the second active layer Np2 can be electrically connected with a data line or the like). Since the first active layer Np1 and the second active layer Np2 are located at different levels, the depths of the via hole exposing the first active layer Np1 and the via hole exposing the second active layer Np2 are different. In the preparation of the semiconductor device, over-etching of the first active layer Np1 or the second active layer Np2 can occur, affecting the performance of the semiconductor device. Therefore, the semiconductor device can further include a second conductive layer 103, a second insulating layer 104, a third conductive layer 105, and a third insulating layer 106, as shown in the following figure. Figures 2A-2C

[0053] The second conductive layer 103 is located between the substrate 100 and the first active layer Np1, and the second conductive layer 103 includes a first electrode E1 electrically connected with the first active layer Np1.

[0054] The second insulating layer 104 covers the second conductive layer 103, and the second insulating layer 104 is provided with a second via hole H2. The first active layer Np1 is electrically connected with the first electrode E1 through the second via hole H2 penetrating the second insulating layer 104.

[0055] The third insulating layer 106 covers the second active layer Np2, and the third insulating layer 106 is provided with a third via hole H3.

[0056] ​The third conductive layer 105 is located on the third insulating layer 106, and the third conductive layer 105 comprises a second electrode E2 electrically connected with the second active layer Np2, and an electrode connecting part Ec spaced from the second electrode E2 and electrically connected with the first electrode E1. The second electrode E2 is electrically connected with the second active layer Np2 through the third via hole H3 penetrating through the third insulating layer 106, and the electrode connecting part Ec is electrically connected with the first electrode E1 through the fourth via hole H4 penetrating through the third insulating layer 106, the first insulating layer 101 and the second insulating layer 104.

[0057] Optionally, one of the first electrode E1 and the second electrode E2 is one of the source and the drain of the semiconductor device, and the other of the first electrode E1 and the second electrode E2 is the other of the source and the drain of the semiconductor device.

[0058] Optionally, the second conductive layer 103 and the third conductive layer 105 comprise at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), tungsten (W) and the like. Optionally, the second conductive layer 103 and the third conductive layer 105 can be a single layer film structure respectively, or can be a Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb laminated structure respectively.

[0059] Optionally, the second insulating layer 104 and the third insulating layer 106 comprise a silicon compound, a metal oxide and the like. Optionally, the second insulating layer 104 and the third insulating layer 106 can respectively comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide and the like. Optionally, the second insulating layer 104 and the third insulating layer 106 can be a single layer film structure respectively, or can be a laminated structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide and the like respectively.

[0060] By setting the first electrode E1, the second electrode E2 and the electrode connecting part Ec, the influence of etching process and the like on the first active layer Np1 and the second active layer Np2 is reduced when the semiconductor device is prepared, so that the semiconductor device has better performance.

[0061] Optionally, please continue to refer to Figures 2A-2DThe first electrode E1 includes a first electrode part E11, a second electrode part E12, and a third electrode part E13 connected between the first electrode part E11 and the second electrode part E12. In a top view, the first electrode part E11 at least partially overlaps the first active layer Np1, and the second electrode part E12 at least partially overlaps the electrode connection part Ec, so as to realize electrical connection between the first active layer Np1 and the electrode connection part Ec through the first electrode E1.

[0062] Optionally, the first active layer Np1 projects on the first electrode part E11 within the boundary of the first electrode part E11, so as to shield light for the active layer by the first electrode part E11.

[0063] Optionally, the width W3 of the third electrode part E13 is less than the width W2 of the second electrode part E12, and the width W2 of the second electrode part E12 is less than the width W1 of the first electrode part E11, so as to reduce the area of the first electrode E1, thereby reducing the accumulation of electric charges on the first electrode E1, and reducing the probability of generating static electricity problems.

[0064] It can be understood that the semiconductor device can be used in integrated circuit design (such as being used for driving chips, etc.), and can also be used in pixel driving circuits, gate driving circuits, backlight driving circuits, amplification circuits, switching circuits, etc. It can be understood that the semiconductor device can be used in the field of display technology (such as being used in array substrates, display panels, display devices, backlight modules, etc.), and can also be used in the field of monitoring technology (such as being used in monitoring equipment, etc.), the field of detection technology (such as being used in detection equipment, etc.), the field of automobiles, etc.

[0065] As shown in Figure 3 is a preparation flowchart of a semiconductor device provided by an embodiment of the present application, Figures 4A-4I is a preparation process schematic diagram of a semiconductor device provided by an embodiment of the present application. The present application further provides a preparation method of a semiconductor device, which is used for preparing any of the above semiconductor devices. The preparation method of the semiconductor device includes:

[0066] Step S100: providing a substrate 100, and preparing the first active layer Np1 on the substrate 100, as shown in Figure 4B .

[0067] Step S200: preparing a first insulating layer 101. The first insulating layer 101 covers the first active layer Np1, and the first insulating layer 101 is provided with a first via hole H1, as shown in Figure 4D .

[0068] Step S300: preparing the third active layer Ch, the third active layer Ch is located in the first via hole H1, the first via hole H1 is completely filled with the third active layer Ch, as shown in Figure 4E

[0069] Step S400: preparing the second active layer Np2, as shown in Figure 4F

[0070] Optionally, in the top view, the first active layer Np1 and the second active layer Np2 at least partially overlap, the third active layer Ch is connected between the first active layer Np1 and the second active layer Np2, and the third active layer Ch corresponds to the part between the overlapping part of the first active layer Np1 and the second active layer Np2, so that the semiconductor device has a shorter channel length.

[0071] Optionally, the first active layer Np1 is prepared by amorphous silicon film forming, excimer laser annealing, exposure, etching, and ion doping process. The second active layer Np2 is prepared by amorphous silicon film forming, excimer laser annealing, exposure, etching, and ion doping process. The third active layer Ch is prepared by amorphous silicon film forming, excimer laser annealing, exposure, etching process. The first insulating layer 101 is prepared by exposure and etching process to obtain the first via hole H1.

[0072] Optionally, in the step S200, it also includes: preparing a first conductive layer 102, as shown in Figure 4C

[0073] Optionally, the first conductive layer 102 is prepared by film forming, exposure, and etching process to obtain the gate G with the first opening A1.

[0074] Optionally, the first insulating layer 101 includes a first sub-insulating layer 1011 and a second sub-insulating layer 1012. In the step S200, it also includes:

[0075] Step S201: preparing the first sub-insulating layer 1011 on the first active layer Np1.

[0076] ​​​Step S202: preparing the first conductive layer 102 on the first sub-insulating layer 1011. Wherein, the first conductive layer 102 comprises the gate G provided with the first opening A1, as shown in Figure 4C .

[0077] Step S203: preparing the second sub-insulating layer 1012 on the first conductive layer 102. Wherein, the first via hole H1 penetrates the first sub-insulating layer 1011 and the second sub-insulating layer 1012 and exposes the first active layer Np1, as shown in Figure 4D .

[0078] Optionally, the step S100 further comprises: preparing a second conductive layer 103 on the substrate 100. Wherein, the second conductive layer 103 comprises a first electrode E1 electrically connected with the first active layer Np1. Optionally, the second conductive layer 103 is prepared into the first electrode E1 through film forming, exposure and etching processes.

[0079] Optionally, the step S100 further comprises: preparing a second insulating layer 104 on the second conductive layer 103, and preparing a second via hole H2 penetrating the second insulating layer 104 and exposing the first electrode E1, as shown in Figure 4A . Wherein, the first active layer Np1 is electrically connected with the first electrode E1 through the second via hole H2. Optionally, the second insulating layer 104 is prepared into the second via hole H2 through film forming, exposure and etching processes.

[0080] Optionally, the step S400 further comprises: preparing a third insulating layer 106 on the second active layer Np2, and preparing a fourth via hole H4 penetrating the third insulating layer 106, the second sub-insulating layer 1012, the first sub-insulating layer 1011 and the second insulating layer 104 and exposing the first electrode E1, and a third via hole H3 penetrating the third insulating layer 106 and exposing the second active layer Np2, as shown in Figures 4G-4H . Optionally, the third insulating layer 106 is prepared into the fourth via hole H4 and the third via hole H3 through film forming, hydrogen activation, exposure and etching processes. Optionally, the third via hole H3 and the fourth via hole H4 can also be prepared through one half-tone photo mask.

[0081] Optionally, after the step S400, a third conductive layer 105 is prepared. The third conductive layer 105 includes a second electrode E2 electrically connected to the second active layer Np2, and an electrode connecting part Ec spaced from the second electrode E2 and electrically connected to the first electrode E1. The second electrode E2 is electrically connected to the second active layer Np2 through the third via hole H3, and the electrode connecting part Ec is electrically connected to the first electrode E1 through the fourth via hole H4, as shown in Figure 4I Optionally, the third conductive layer 105 is prepared by a film forming, exposure, and etching process to obtain the second electrode E2 and the electrode connecting part Ec.

[0082] It can be understood that the third active layer Ch can also be in the form as shown in Figure 2A and Figure 2B

[0083] As shown in Figures 5A-5B is a structural schematic diagram of a display panel provided by an embodiment of the present application. The present application also provides a display panel including any of the above semiconductor devices or semiconductor devices prepared according to the preparation method of any of the above semiconductor devices.

[0084] Optionally, the display panel includes a passive light-emitting display panel and a self-luminous display panel. Optionally, the display panel includes a liquid crystal display panel, a touch display panel, and a display panel including a light-emitting device. Optionally, the light-emitting device includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, and the like.

[0085] Please continue to refer to Figure 5A The display panel further includes a planar layer 201, a bottom electrode 202 on the planar layer, a protective layer 203 on the bottom electrode 202, and a top electrode 204 on the protective layer 203. Optionally, the third conductive layer 105 further includes a first connecting part, the bottom electrode is electrically connected to the first connecting part through a via hole penetrating the planar layer 201, and the top electrode 204 is electrically connected to the electrode connecting part Ec through a via hole penetrating the planar layer 201 and the protective layer 203.

[0086] Optionally, the bottom electrode 202 is a touch electrode, and the top electrode 204 is a pixel electrode. Optionally, the bottom electrode 202 and the top electrode 204 are transparent electrodes.

[0087] Please continue to refer to Figure 5B ​The display panel further comprises the planar layer 201, an anode layer 205, a pixel definition layer 206, a light emitting layer 207 and a cathode layer 208. The anode layer 205 is located on the planar layer 201 and comprises a plurality of anodes electrically connected with the electric connection part Ec. The pixel definition layer 206 is located on the anode layer 205 and is provided with a pixel definition area exposing the anodes. The light emitting layer 207 is located in the pixel definition area, and the cathode layer 208 is located on the light emitting layer 207 and comprises a plurality of cathodes. The light emitting device comprises the anodes, the light emitting layer and the cathodes. It can be understood that the third active layer Ch can also adopt the forms shown in Figure 2A and Figure 2B .

[0088] The present application further provides a display device comprising any of the above semiconductor devices or the semiconductor devices prepared according to the preparation method of any of the above semiconductor devices. It can be understood that the display device comprises a movable display device (such as a notebook computer, a mobile phone and the like), a fixed terminal (such as a desktop computer, a television and the like), a measuring device (such as a sports bracelet, a temperature measuring instrument and the like) and the like.

[0089] The principles and implementation modes of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a first active layer on the substrate; a first insulating layer covering the first active layer; and a second active layer on the first insulating layer; a first conductive layer in the first insulating layer, comprising a gate electrode, the gate electrode being provided with a first opening; wherein the first insulating layer is provided with a first via, a third active layer is in the first via and connects the first active layer and the second active layer, the third active layer serving as a channel of the semiconductor device; in a top view, the first via is in the first opening; the third active layer comprises: a main body in the first via; and an extension connected to the main body and between the second active layer and the first insulating layer; wherein, in a top view, a normal projection of a boundary of the main body on the extension is in a boundary of the extension. In a top view, the extension partially overlaps the gate electrode.

2. The semiconductor device according to claim 1, wherein A distance between the boundary of the extension and the boundary of the main body is greater than or equal to 0.5 microns and less than or equal to 5 microns.

3. The semiconductor device of claim 2, wherein The first insulating layer comprises:

4. The semiconductor device of claim 1, wherein a first sub-insulating layer covering the first active layer; a second sub-insulating layer covering the first conductive layer; wherein the second active layer is on the second sub-insulating layer. Further comprising:

5. The semiconductor device of claim 1, wherein a second conductive layer between the substrate and the first active layer, comprising a first electrode; a second insulating layer covering the second conductive layer, the second insulating layer being provided with a second via; wherein the first active layer is electrically connected to the first electrode through the second via. Further comprising:

6. The semiconductor device of claim 5, wherein, a third insulating layer covering the second active layer, the third insulating layer being provided with a third via; a third conductive layer on the third insulating layer, comprising a second electrode and an electrode connecting portion spaced apart from the second electrode; wherein the second electrode is electrically connected to the second active layer through the third via, and the electrode connecting portion is electrically connected to the first electrode through a fourth via penetrating through the third insulating layer, the first insulating layer and the second insulating layer. The first electrode comprises a first electrode portion, a second electrode portion and a third electrode portion connected between the first electrode portion and the second electrode portion; 7. The semiconductor device of claim 6, wherein, wherein, in a top view, the first electrode portion partially overlaps the first active layer, and the second electrode portion partially overlaps the electrode connecting portion. A width of the third electrode portion is less than a width of the second electrode portion, and the width of the second electrode portion is less than a width of the first electrode portion.

8. The semiconductor device of claim 7, wherein, The first via is a circular truncated cone.

9. The semiconductor device of claim 1, wherein, ​

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