Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises a first input circuit, a second input circuit, a first positive feedback circuit, a second positive feedback circuit and an output circuit. The first input circuit is configured to generate first differential signals according to a first input signal and a first reference signal in a sampling stage. The second input circuit is configured to generate second differential signals according to a second input signal and a second reference signal in the sampling stage. The first positive feedback circuit is configured to accelerate the difference between the first differential signals. The second positive feedback circuit is configured to accelerate the difference between the second differential signals. The output circuit is configured to amplify and latch the voltage signals at the output end of the first input circuit and the voltage signals at the output end of the second input circuit in a regeneration stage, so as to output a comparison result. The application can improve the response rate of the comparator and reduce the power consumption of the comparator.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among these, the comparator is a crucial device for realizing DRAM data read and write operations, and existing comparators cannot meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to improve the comparator's response rate and reduce its power consumption.

[0005] In a first aspect, this application provides a comparator having four input terminals and two output terminals, including:

[0006] The first input circuit has two input terminals and two output terminals. Its two input terminals serve as the input terminals of a comparator, which are used to generate a first differential signal based on the first input signal and the first reference signal during the sampling stage.

[0007] The first positive feedback circuit is connected to the two output terminals of the first input circuit and is used to accelerate the difference between the first differential signals.

[0008] The second input circuit has two input terminals and two output terminals. Its two input terminals serve as the input terminals of a comparator, and its two output terminals are connected to the two output terminals of the first input circuit. It is used to generate a second differential signal based on the second input signal and the second reference signal during the sampling stage.

[0009] The second positive feedback circuit is connected to the two output terminals of the second input circuit and is used to accelerate the difference between the second differential signals.

[0010] The output circuit has two input terminals and two output terminals. The two output terminals are the output terminals of the comparator, and the two input terminals are connected to the two output terminals of the first input circuit. It is used to amplify and latch the voltage signal at the output terminal of the first input circuit and the voltage signal at the output terminal of the second input circuit during the regeneration phase, so as to output the comparison result.

[0011] In a second aspect, this application provides a decision feedback equalization circuit, characterized in that it includes four comparators as described in the first aspect, which are sequentially labeled as a first comparator, a second comparator, a third comparator, and a fourth comparator;

[0012] The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator.

[0013] The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the first comparator, and a fourth input terminal connected to the second output terminal of the first comparator.

[0014] The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the second comparator, and a fourth input terminal connected to the second output terminal of the second comparator.

[0015] The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the third comparator, and a fourth input terminal connected to the second output terminal of the third comparator.

[0016] This application provides a comparator and a decision feedback equalization circuit. The comparator includes a first input circuit, a second input circuit, a first positive feedback circuit, a second positive feedback circuit, and an output circuit. The first input circuit generates a first differential signal based on a first input signal and a first reference signal during the sampling phase. The second input circuit generates a second differential signal based on a second input signal and a second reference signal during the sampling phase. The first positive feedback circuit accelerates the difference between the first and second differential signals, and the second positive feedback circuit accelerates the difference between the second differential signals. The output circuit amplifies and latches the voltage signals at the outputs of the first and second input circuits during the regeneration phase to output the comparison result. When either or both of the first and second reference signals are not properly selected, generating a differential signal with a large difference in the corresponding input circuit takes a relatively long time. The positive feedback circuit in the corresponding input circuit accelerates the difference through a positive feedback mechanism after a slight difference exists between the two outputs of the input circuit, shortening the sampling phase time, thereby improving the comparator's response rate and reducing its power consumption. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0019] Figure 2 The timing diagram of the comparator provided in this application;

[0020] Figure 3 A structural block diagram of a comparator provided in this application;

[0021] Figure 4 For based on Figure 3 A specific circuit diagram of one type of comparator is provided;

[0022] Figure 5 For based on Figure 3 A specific circuit diagram of another comparator is provided;

[0023] Figure 6 A structural block diagram of a comparator provided in this application;

[0024] Figure 7 For based on Figure 6 A specific circuit diagram of one type of comparator is provided;

[0025] Figure 8 for Figure 7 The specific circuit diagram of the controllable positive feedback module in the provided comparator;

[0026] Figure 9 For based on Figure 6 A specific circuit diagram of another comparator is provided;

[0027] Figure 10 for Figure 9 The specific circuit diagram of the controllable positive feedback module in the provided comparator;

[0028] Figure 11 A block diagram of a decision feedback equalization circuit provided in this application;

[0029] Figure 12 A schematic diagram illustrating the effect of the decision feedback equalization circuit provided in this application;

[0030] Figure 13 The timing diagram of the decision feedback equalization circuit provided in this application.

[0031] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 106. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 106 is also connected to the output circuit 102.

[0034] The input circuit 101 includes transistors N1, N2, and N3. Transistors N1 and N2 form a differential transistor pair. The gates of transistors N1 and N2 form the first input terminal IP and the second input terminal IN of the input circuit. The drains of transistors N1 and N2 form the two output terminals of the input circuit.

[0035] The output circuit 102 includes transistors P1, P2, N4, and N5, which form a cross-coupled transistor pair. The drains of transistors P1 and N4 form the first output terminal ON of the output circuit 102, and the drains of transistors P2 and N5 form the second output terminal OP of the output circuit 102. The reset circuit 106 includes transistors P3 and P4.

[0036] The comparator's operation consists of four stages: reset, sampling, regeneration, and decision. The following section will discuss these stages in conjunction with... Figure 2 describe Figure 1 The working process of the comparator shown is as follows:

[0037] During the reset phase, from time t0 to time t1, the clock signal is low, transistor N3 is open, the input and output circuits stop working, transistors P3 and P4 are closed, the reset circuit works, and pulls the drain voltage of transistor N4 and the drain voltage of transistor N5 to high level.

[0038] During the sampling phase, from time t1 to t2, the clock signal is high, transistors P3 and P4 are open, and the reset circuit stops working. Transistor N3 is closed, and the input circuit acquires the input signal through the first input terminal IP and the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the rate at which the input signal pulls down the drain voltage of transistor N1 is faster, resulting in the drain voltage of transistor N4 being lower than that of transistor N5.

[0039] During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0040] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0041] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0042] However, when the reference signal is not properly selected, the time it takes for the input signal and the reference signal to generate a differential signal at the output of the input circuit is relatively long, resulting in a reduced comparator response rate and increased power consumption. For example... Figure 2 In the comparator shown, when the reference signal is small, transistors N1 and N2 need to be turned on for a longer time, which reduces the charging current of nodes VP and VN. Transistors N1 and N2 drive transistors N5 and N4 to slow down, resulting in a decrease in the comparator's response rate and an increase in the comparator's power consumption.

[0043] like Figure 3As shown, one embodiment of this application provides a comparator with four input terminals and two output terminals. The four input terminals of the comparator are sequentially labeled as the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal. The two output terminals of the comparator are sequentially labeled as the first output terminal and the second output terminal. The comparator includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0044] The first input circuit 101 has two input terminals and two output terminals, and the second input circuit 102 also has two input terminals and two output terminals. The two output terminals of the first input circuit 101 and the two output terminals of the second input circuit 102 are connected together. The first input terminal of the first input circuit 101 serves as the first input terminal of a comparator, used to receive a first input signal. The second input terminal of the first input circuit 101 serves as the second input terminal of a comparator, used to receive a first reference signal. The first input terminal of the second input circuit 102 serves as the third input terminal of a comparator, used to receive a second reference signal. The second input terminal of the second input circuit 102 serves as the fourth input terminal of a comparator, used to receive a second input signal.

[0045] The output circuit 105 also has two input terminals and two output terminals. The two input terminals of the output circuit 105 are connected to the two output terminals of the first input circuit 101, and the two input terminals of the output circuit 105 are also connected to the two output terminals of the second input circuit 102. The two output terminals of the output circuit 105 serve as the two output terminals of a comparator.

[0046] After receiving the first input signal and the first reference signal, the two input terminals of the first input circuit 101 generate a first differential signal based on the first input signal and the first reference signal during the sampling phase. After receiving the second input signal and the second reference signal, the two input terminals of the second input circuit 102 generate a second differential signal based on the second input signal and the second reference signal during the sampling phase.

[0047] The first differential signal and the second differential signal are a pair of voltage signals. The first positive feedback circuit 103 is used to accelerate the difference between the first differential signal and the second positive feedback circuit 104 is used to accelerate the difference between the second differential signal. The first input circuit 101 is also used to output the accelerated first differential signal, and the second input circuit 102 is also used to output the accelerated second differential signal. The output circuit 105 is used to amplify and latch the voltage signals at the output terminals of the first input circuit 101 and the second input circuit 102 during the regeneration phase, so as to output the comparison result through the two output terminals.

[0048] When the first reference signal is not properly selected, the response time of the first input circuit 101 becomes longer, meaning that the first input circuit 101 needs a longer time to present a first differential signal with a relatively large difference at the output. The first positive feedback circuit 103 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time it takes for the first input circuit 101 to present a first differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0049] Similarly, when the second reference signal is not properly selected, the response time of the second input circuit 102 becomes longer, meaning that the second input circuit 102 needs a longer time to present a second differential signal with a relatively large difference at the output. The second positive feedback circuit 104 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time that the second input circuit 102 presents a second differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0050] In one embodiment, the first positive feedback circuit 103 includes a first feedback unit 1031 and a second feedback unit 1032, both of which are provided with a control terminal and a first terminal.

[0051] The control terminal of the first feedback unit 1031 is connected to the first output terminal of the first input circuit 101, and the first end of the first feedback unit 1031 is connected to the second output terminal of the first input circuit 101. The control terminal of the second feedback unit 1032 is connected to the second output terminal of the first input circuit 101, and the first end of the second feedback unit 1032 is connected to the first output terminal of the first input circuit 101.

[0052] The first feedback unit 1031 is used to pull the voltage of the second output terminal of the first input circuit 101 according to the voltage of the first output terminal of the first input circuit 101 during the sampling phase, and the second feedback unit 1032 is used to pull the voltage of the first output terminal of the first input circuit 101 according to the voltage of the second output terminal of the first input circuit 101 during the sampling phase.

[0053] The direction in which the first feedback unit 1031 pulls the voltage at the second output terminal of the first input circuit 101 is the same as the direction in which the second feedback unit 1032 pulls the voltage at the first output terminal of the first input circuit 101. When the first feedback unit 1031 pulls the voltage at the second output terminal of the first input circuit 101 upwards, the second feedback unit 1032 also pulls the voltage at the first output terminal of the first input circuit 101 upwards. When the first feedback unit 1031 pulls the voltage at the second output terminal of the first input circuit 101 downwards, the second feedback unit 1032 also pulls the voltage at the first output terminal of the first input circuit 101 downwards.

[0054] In one embodiment, the second positive feedback circuit 104 includes a third feedback unit 1033 and a fourth feedback unit 1034, both of which are provided with a control terminal and a first terminal.

[0055] The control terminal of the third feedback unit 1033 is connected to the first output terminal of the second input circuit 102, and the first terminal of the third feedback unit 1033 is connected to the second output terminal of the second input circuit 102. The control terminal of the fourth feedback unit 1034 is connected to the second output terminal of the second input circuit 102, and the first terminal of the fourth feedback unit 1034 is connected to the first output terminal of the second input circuit 102.

[0056] The third feedback unit 1033 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 during the sampling phase, and the fourth feedback unit 1034 is used to pull the voltage of the first output terminal of the second input circuit 102 according to the voltage of the second output terminal of the second input circuit 102 during the sampling phase.

[0057] The third feedback unit 1033 pulls the voltage at the second output terminal of the second input circuit 102 in the same direction as the fourth feedback unit 1034 pulls the voltage at the first output terminal of the second input circuit 102. When the third feedback unit 1033 pulls the voltage at the second output terminal of the second input circuit 102 upwards, the fourth feedback unit 1034 also pulls the voltage at the first output terminal of the second input circuit 102 upwards. When the third feedback unit 1033 pulls the voltage at the second output terminal of the second input circuit 102 downwards, the fourth feedback unit 1034 also pulls the voltage at the first output terminal of the second input circuit 102 downwards.

[0058] The following example illustrates the effect of pulling down the voltage of the two output terminals of the first input circuit 101: When the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1031 has a stronger ability to pull down the voltage of the second output terminal of the first input circuit 101, while the second feedback unit 1032 has a weaker ability to pull down the voltage of the first output terminal of the first input circuit 101. In other words, the voltage drop rate of the first output terminal is lower than that of the second output terminal, which in turn makes the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0059] When the voltage at the first output terminal of the first input circuit 101 is lower than the voltage at the second output terminal of the first input circuit 101, the first feedback unit 1031 has a weaker ability to pull down the voltage at the second output terminal of the first input circuit 101, while the second feedback unit 1032 has a stronger ability to pull down the voltage at the first output terminal of the first input circuit 101. In other words, the voltage drop rate at the first output terminal is higher than the voltage drop rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0060] The following example illustrates the effect of pulling up the voltage of the two output terminals of the first input circuit 101: When the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1031 has a weaker ability to pull up the voltage of the second output terminal of the first input circuit 101, while the second feedback unit 1032 has a stronger ability to pull up the voltage of the first output terminal of the first input circuit 101. In other words, the voltage rise rate of the first output terminal is higher than that of the second output terminal, which in turn makes the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0061] When the voltage at the first output terminal of the first input circuit 101 is lower than the voltage at the second output terminal of the first input circuit 101, the first feedback unit 1031 has a stronger ability to pull up the voltage at the second output terminal of the first input circuit 101, while the second feedback unit 1032 has a weaker ability to pull up the voltage at the first output terminal of the first input circuit 101. In other words, the voltage rise rate at the first output terminal is lower than the voltage rise rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0062] In the above technical solution, when any one or both of the first reference signal and the second reference signal are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through the positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortens the sampling stage time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0063] Figure 4 A circuit diagram of a comparator provided in another embodiment of this application is shown below. Figure 4 As shown, the comparator provided in this application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0064] The first input circuit 101 includes a first input transistor N1, a second input transistor N2, and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the first input circuit 101, and its first terminal serves as the first output terminal. The control terminal of the second input transistor N2 serves as the second input terminal of the first input circuit 101, and its first terminal serves as the second output terminal. The first terminal of the third input transistor N3 is connected to the second terminals of both the first and second input transistors N1 and N2, and its second terminal is connected to ground.

[0065] The control terminal of the third input transistor N3 receives a clock signal to control the operating state of the first input circuit 101. When the third input transistor N3 is closed, the first input circuit 101 operates. When the third input transistor N3 is open, the first input circuit 101 stops operating.

[0066] The control terminal of the first input transistor N1 receives the first input signal, and the control terminal of the second input transistor N2 receives the first reference signal. After the first input signal and the first reference signal are amplified by the first input transistor N1 and the second input transistor N2, a first differential signal is generated at the first terminal of the first input transistor N1 and the first terminal of the second input transistor N2.

[0067] The second input circuit 102 includes a fourth input transistor N4, a fifth input transistor N5, and a sixth input transistor N6. The control terminal of the fourth input transistor N4 serves as the first input terminal of the second input circuit 102, and its first terminal serves as the first output terminal. The control terminal of the fifth input transistor N5 serves as the second input terminal of the second input circuit 102, and its first terminal serves as the second output terminal. The first terminal of the sixth input transistor N6 is connected to the second terminals of the fourth and fifth input transistors, and its second terminal is connected to ground.

[0068] The control terminal of the sixth input transistor N6 receives a clock signal to control the operating state of the second input circuit 102. When the sixth input transistor N6 is closed, the second input circuit 102 operates. When the sixth input transistor N6 is open, the second input circuit 102 stops operating.

[0069] The control terminal of the fourth input transistor N4 receives the second reference signal, and the control terminal of the fifth input transistor N5 receives the second input signal. After the second reference signal and the second input signal are amplified by the fourth input transistor N4 and the fifth input transistor N5, a second differential signal is generated at the first terminal of the fourth input transistor N4 and the first terminal of the fifth input transistor N5.

[0070] The output circuit 105 includes a first output transistor N7, a second output transistor N8, a third output transistor P1, and a fourth output transistor P2 forming a cross-coupled circuit. The first terminal of the first output transistor N7 is connected to the second terminal of the third output transistor P1, and the first terminal of the second output transistor N8 is connected to the second terminal of the fourth output transistor P2. The control terminal of the first output transistor N7 is connected to the control terminal of the third output transistor P1, and then to the second terminal of the fourth output transistor P2. Similarly, the control terminal of the second output transistor N8 is connected to the control terminal of the fourth output transistor P2, and then to the second terminal of the third output transistor P1.

[0071] The second terminal of the first output transistor N7 is the first input terminal of the output circuit 105, and the second terminal of the second output transistor N8 is the second input terminal of the output circuit 105. The second terminal of the first output transistor N7 is connected to the first terminal of the first input transistor N1, and the second terminal of the second output transistor N8 is connected to the first terminal of the second input transistor N2. The second terminal of the third output transistor P1 serves as the first output terminal of the output circuit 105, and the second terminal of the fourth output transistor P2 serves as the second output terminal of the output circuit 105.

[0072] The first input transistor N1 and the second input transistor N2 are turned on under the control of the first input signal and the first reference signal, which also pulls down the voltage at the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8. The fourth input transistor N4 and the fifth input transistor N5 are turned on under the control of the second input signal and the second reference signal, which also pull down the voltage at the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8. By controlling the magnitudes of the first and second input signals, the difference between the voltage at the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8 can be controlled.

[0073] When the voltage is pulled down to the switching voltage, the transistors conduct. That is, the first output transistor N7 and the fourth output transistor P2 conduct, or the second output transistor N8 and the third output transistor P1 conduct. If the first output transistor N7 and the fourth output transistor P2 conduct, the voltage at the second terminal of the fourth output transistor P2 is pulled up, and the voltage at the second terminal of the third output transistor P1 is pulled down. If the second output transistor N8 and the third output transistor P1 conduct, the voltage at the second terminal of the fourth output transistor P2 is pulled down, and the voltage at the second terminal of the third output transistor P1 is pulled up, thus amplifying and latching the voltage signal output from the input circuit.

[0074] In one embodiment, the first feedback unit 1031 includes a first feedback transistor N9. The control terminal of the first feedback transistor N9 is the control terminal of the first feedback unit 1031, and the first terminal of the first feedback transistor N9 is the first terminal of the first feedback unit 1031. The control terminal of the first feedback transistor N9 is connected to the first terminal of the first input transistor N1, and the first terminal of the first feedback transistor N9 is connected to the first terminal of the second input transistor N2. The second terminal of the first feedback transistor N9 is also connected to the first terminal of the third input transistor N3.

[0075] The control terminal of the second feedback transistor N10 is the control terminal of the second feedback unit 1032, and the first terminal of the second feedback transistor N10 is the first terminal of the second feedback unit 1032. The control terminal of the second feedback transistor N10 is connected to the first terminal of the second input transistor N2, and the first terminal of the second feedback transistor N1 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N10 is connected to the second terminal of the first input transistor N1, and the second terminal of the second feedback transistor N10 is also connected to the first terminal of the third input transistor N3.

[0076] In one embodiment, the first feedback transistor N9, the second feedback transistor N10, the first input transistor N1, and the second input transistor N2 are of the same type, ensuring that the direction in which the first feedback transistor N9 pulls the voltage at the second output terminal of the first input circuit 101 is the same as the direction in which the second feedback transistor N10 pulls the voltage at the first output terminal of the first input circuit 101. It is also ensured that the direction in which the feedback transistor pulls the voltage at the output terminal of the first input circuit 101 and the direction in which the input transistor pulls the voltage at the output terminal of the first input circuit 101 are the same, thereby achieving positive feedback.

[0077] The greater the voltage at the first terminal of the first input transistor N1, the greater the ability of the first feedback transistor N9 to pull down the voltage at the first terminal of the second input transistor N2, and the faster the voltage at the first terminal of the second input transistor N2 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the first input transistor N1 and the second input transistor N2.

[0078] In one embodiment, the third feedback unit 1033 includes a third feedback transistor N11. The control terminal of the third feedback transistor N11 is the control terminal of the third feedback unit 1033, and the first terminal of the third feedback transistor N11 is the first terminal of the third feedback unit 1033. The control terminal of the third feedback transistor N11 is connected to the first terminal of the fourth input transistor N4, and the first terminal of the third feedback transistor N11 is connected to the first terminal of the fifth input transistor N5. The second terminal of the third feedback transistor N11 is connected to the second terminal of the fourth input transistor N4. The second terminal of the third feedback transistor N11 is also connected to the first terminal of the sixth input transistor N6.

[0079] The control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 1034, and the first terminal of the fourth feedback transistor N12 is the first terminal of the fourth feedback unit 1034. The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fifth input transistor N5, and the first terminal of the fourth feedback transistor N12 is also connected to the first terminal of the fourth input transistor N4. The second terminal of the fourth feedback transistor N12 is connected to the second terminal of the fifth input transistor N5, and the second terminal of the fourth feedback transistor N12 is also connected to the first terminal of the sixth input transistor N6.

[0080] In one embodiment, the third feedback transistor N11, the fourth feedback transistor N12, the fourth input transistor N4, and the fifth input transistor N5 are of the same type, ensuring that the direction of the voltage at the second output terminal of the second input circuit 102 pulled by the third feedback transistor N11 is the same as the direction of the voltage at the first output terminal of the second input circuit 102 pulled by the fourth feedback transistor N12. It is also ensured that the direction of the voltage at the output terminal of the second input circuit 102 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the second input circuit 102 pulled by the input transistor, thereby achieving positive feedback.

[0081] The greater the voltage at the first terminal of the fourth input transistor N4, the greater the ability of the third feedback transistor N11 to pull down the voltage at the first terminal of the fifth input transistor N5, and the faster the voltage at the first terminal of the fifth input transistor N5 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the fourth input transistor N4 and the fifth input transistor N5.

[0082] In one embodiment, the first input transistor N1, the second input transistor N2, the fourth input transistor N4, and the fifth input transistor N5 are of the same type.

[0083] In one embodiment, the comparator further includes a first reset circuit 1061, which is connected between a first output terminal and a second output terminal of the first input circuit 101. The first reset circuit 1061 is used to reset the voltage at the first output terminal and the voltage at the second output terminal of the first input circuit 101.

[0084] The first reset circuit 1061 includes a first clocked transistor P5 and a second clocked transistor P6. The second terminal of the first clocked transistor P5 is connected to the first output terminal of the first input circuit 101, and the second terminal of the second clocked transistor P6 is connected to the second output terminal of the first input circuit 101. The first terminal of the second clocked transistor P6 is connected to the first terminal of the first clocked transistor P5 and then connected to a power supply. The control terminals of both the first clocked transistor P5 and the second clocked transistor P6 receive clock signals and are turned on when the clock signal is at a low level, pulling the first and second output terminals of the first input circuit 101 to a high level.

[0085] In one embodiment, the comparator further includes a second reset circuit 1062 and a third reset circuit 1063. The second reset circuit 1062 is connected to the first output terminal of the output circuit 105, and the third reset circuit 1063 is connected to the second output terminal of the output circuit 105. The second reset circuit 1062 is used to reset the voltage at the first output terminal of the output circuit 105. The third reset circuit 1063 is used to reset the voltage at the second output terminal of the output circuit 105.

[0086] The second reset circuit 1062 includes a third clocked transistor P3, the second terminal of which is connected to the first output terminal of the output circuit 105. The control terminal of the third clocked transistor P3 is used to receive a clock signal and pull the first output terminal of the output circuit 105 to a high level when the clock signal is low. The third reset circuit 1063 includes a fourth clocked transistor P4, the second terminal of which is connected to the second output terminal of the output circuit 105. The control terminal of the fourth clocked transistor P4 is used to receive a clock signal and pull the second output terminal of the output circuit 105 to a high level when the clock signal is low.

[0087] Compared to the second reset circuit 1062 and the third reset circuit 1063 pulling the voltage of the two output terminals of the first input circuit 101 through the output circuit 105 to achieve reset, the reset time is shorter by setting the first reset circuit 1061 to directly pull the voltage of the two output terminals of the first input circuit 101, thereby improving the response rate of the comparator.

[0088] In one embodiment, the first clocked transistor P5, the second clocked transistor P6, the third clocked transistor P3, and the fourth clocked transistor P4 are of the same type, so as to pull the two output terminals of the input circuit and the two output terminals of the output circuit 105 to the same level.

[0089] In one embodiment, when the first feedback transistor N9, the second feedback transistor N10, the third feedback transistor N11, the fourth feedback transistor N12, the first input transistor N1, the second input transistor N2, the third input transistor N3, and the fourth input transistor N4 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0090] In one embodiment, when both the first output transistor N7 and the second output transistor N8 are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0091] When the third output transistor P1 and the fourth output transistor P2 are both P-type transistors, and the first clocked transistor P5, the second clocked transistor P6, the third clocked transistor P3 and the fourth clocked transistor P4 are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0092] In one embodiment, the first feedback transistor N9 and the second feedback transistor N10 are of the same size, and the first input transistor N1 and the second input transistor N2 are of the same size. The size of the first feedback transistor N9 is less than half the size of the first input transistor N1. This avoids the first feedback transistor N9 and the second feedback transistor N10 from affecting the sensing of the first input signal and the first reference signal by the first input transistor N1 and the second input transistor N2, thereby improving the accuracy of the comparator output.

[0093] In one embodiment, the third feedback transistor N11 and the fourth feedback transistor N12 are of the same size, and the fourth input transistor N4 and the fifth input transistor N5 are of the same size. The size of the third feedback transistor N11 is less than half the size of the fourth input transistor N4. This avoids the third feedback transistor N11 and the fourth feedback transistor N12 from affecting the sensing of the second input signal and the second reference signal by the fourth input transistor N4 and the fifth input transistor N5, thereby improving the accuracy of the comparator output.

[0094] In one embodiment, the ratio of the size of the fourth input transistor N4 to the size of the first input transistor N1 is α, where α < 0.5, so that the size of the fourth input transistor N4 is less than half the size of the first input transistor N1. The ratio of the size of the third feedback transistor N11 to the size of the first feedback transistor N9 is α < 0.5, so that the size of the first feedback transistor N9 is less than half the size of the third feedback transistor N11. The ratio of the size of the sixth input transistor N6 to the size of the third input transistor N3 is α, where α < 0.5, so that the size of the sixth input transistor N6 is less than half the size of the third input transistor N3. With the above configuration, the influence of the second input circuit 102 on the first input circuit 101 can be avoided from being too great, causing the first differential signal to invert. For example, if the first input signal and the first reference signal cause the first terminal voltage of the first input transistor N1 to be greater than the first terminal voltage of the second input transistor N2, the intervention of the second differential signal will cause the first differential signal to invert, that is, make the first terminal voltage of the first input transistor N1 less than the first terminal voltage of the second input transistor N2.

[0095] In one embodiment, the second reference signal and the second input signal at the current moment are determined based on the first input signal and the first reference signal at the previous moment. If the first input signal at the previous moment is greater than the first reference signal, then the second input signal at the current moment is set to be greater than the second reference signal. If the first input signal at the previous moment is less than the first reference signal, then the second input signal at the current moment is set to be less than the second reference signal.

[0096] The following describes the four working stages of a comparator. Figure 4 The working process of the comparator shown is as follows:

[0097] During the reset phase, the clock signal is low, the third input transistor N3 and the sixth input transistor N6 are disconnected, the first input circuit 101 and the second input circuit 102 stop working, the first clocked transistor P5 and the second clocked transistor P6 are turned on, the first reset circuit 1061 is activated, and the voltages at the first and second output terminals of the first input circuit 101 are pulled up to a high level. The third clocked transistor P3 and the fourth clocked transistor P4 are closed, the second reset circuit 1062 and the third reset circuit 1063 are activated, pulling the drain voltages of the third output transistor P1 and the fourth output transistor P2 to a high level.

[0098] During the sampling phase, the clock signal is high, and the first clock-controlled transistor P5, the second clock-controlled transistor P6, the third clock-controlled transistor P3, and the fourth clock-controlled transistor P4 are disconnected, and the first reset circuit 1061 to the third reset circuit 1063 stop working. The third input transistor N3 and the sixth input transistor N6 are closed, and the first input circuit 101 and the second input circuit 102 are working.

[0099] The sampling stage is described below by considering the different values ​​of the first and second input signals.

[0100] In the first scenario: At the current moment, the first input signal is greater than the first reference signal, while at the previous moment, the first input signal was less than the first reference signal. Based on the relationship between the first input signal and the first reference signal at the previous moment, the second input signal is set to be less than the first reference signal. For example: at the previous moment, the first input signal was 0.7V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

[0101] When inter-symbol interference (ISI) is present, meaning the first input signal from the previous moment interferes with the first input signal at the current moment, assuming the amplitude of the first input terminal In1 of the first input circuit 101 is 0.8V, the pull-down capability of the first input transistor N1 is equal to the pull-down capability of the second input transistor N2, and the drain voltages of the first input transistor N1 and the second input transistor N2 are equal, and the pull-down capability of the fourth input transistor N4 is higher than that of the fifth input transistor N5, under the pull of the fourth input transistor N4 and the fifth input transistor N5, and under the pull of the first positive feedback circuit 103 and the second positive feedback circuit 104, the second terminal voltage of the first input transistor N1 is less than the second terminal voltage of the second input transistor N2.

[0102] In the absence of inter-symbol interference (ISI), the first input signal and the first reference signal will cause the voltage at the second terminal of the first input transistor N1 to be lower than the voltage at the second terminal of the second input transistor N2. That is, ISI is eliminated by adjusting the first input circuit 101 through the second input circuit 102. Typically, the pull-down capabilities of the fourth input transistor N4 and the fifth input transistor N5 are relatively small. When a voltage difference appears between the drains of the fourth input transistor N4 and the fifth input transistor N5, two positive feedback circuits accelerate the voltage difference between their drains, which can shorten the sampling time and reduce power consumption.

[0103] In the second scenario, if the first input signal is greater than the first reference signal at the current and previous times, the second input signal is set to be greater than the first reference signal. For example, at the previous time, the first input signal was 0.9V and the first reference signal was 0.8V. At the current time, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

[0104] When inter-symbol interference exists, meaning the first input signal from the previous moment interferes with the first input signal at the current moment, assuming the amplitude of the first input terminal In1 of the first input circuit 101 is still 0.9V, the pull-down capability of the first input transistor N1 is greater than that of the second input transistor N2, and the drain voltage of the first input transistor N1 is less than that of the second input transistor N2. The pull-down capability of the fourth input transistor N4 is less than that of the fifth input transistor N5. The second input circuit 102 will pull the voltages of the first and second input transistors N1 and N2 in a direction that makes the voltage of the first input transistor N1 greater than the voltage of the second input transistor N2. However, the pull-down capability of the transistors in the second input circuit is α times that of the transistors in the first input circuit, where α is less than 0.5. Therefore, the pull-down capability of the transistors in the second input circuit is much weaker than that of the transistors in the first input circuit, and the second terminal voltage of the first input transistor N1 is still less than the second terminal voltage of the second input transistor N2.

[0105] In the third scenario, at the current moment, the first input signal is less than the first reference signal, while at the previous moment, the first input signal was greater than the first reference signal. Therefore, the second input signal is set to be greater than the first reference signal. For example, at the previous moment, the first input signal was 0.9V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

[0106] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal In1 of the first input circuit 101 is 0.8V, the pull-down capability of the first input transistor N1 is equal to that of the second input transistor N2, and the drain voltages of the first input transistor N1 and the second input transistor N2 are equal. However, the pull-down capability of the fourth input transistor N4 is lower than that of the fifth input transistor N5. Under the pull of the fourth input transistor N4 and the fifth input transistor N5, and under the pull of the first positive feedback circuit 103 and the second positive feedback circuit 104, the voltage at the second terminal of the first input transistor N1 is greater than the voltage at the second terminal of the second input transistor N2.

[0107] In the absence of inter-symbol interference (ISI), the first input signal and the first reference signal will cause the voltage at the second terminal of the first input transistor N1 to be greater than the voltage at the second terminal of the second input transistor N2. That is, ISI is eliminated by adjusting the first input circuit 101 through the second input circuit 102. Typically, the pull-down capabilities of the fourth input transistor N4 and the fifth input transistor N5 are relatively small. When a voltage difference appears between the drains of the fourth input transistor N4 and the fifth input transistor N5, two positive feedback circuits accelerate the voltage difference between their drains, which can shorten the sampling time and reduce power consumption.

[0108] In the fourth scenario, at the current moment, the first input signal is less than the first reference signal, and at the previous moment, the first input signal was also less than the first reference signal. Therefore, the second input signal is set to be less than the first reference signal. For example, at the previous moment, the first input signal was 0.7V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

[0109] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal In1 of the first input circuit 101 remains at 0.7V, the pull-down capability of the first input transistor N1 is less than that of the second input transistor N2, and the drain voltage of the first input transistor N1 is greater than that of the second input transistor N2. The pull-down capability of the fourth input transistor N4 is greater than that of the fifth input transistor N5. The second input circuit 102 will pull the voltages of the first and second input transistors N1 and N2 in a direction that makes the voltage of the first input transistor N1 less than the voltage of the second input transistor N2. However, the pull-down capability of the transistors in the second input circuit is α times that of the transistors in the first input circuit, where α is less than 0.5. Therefore, the pull-down capability of the transistors in the second input circuit is much weaker than that of the transistors in the first input circuit, and the second terminal voltage of the first input transistor N1 is still greater than that of the second terminal voltage of the second input transistor N2.

[0110] During the regeneration phase, due to the pull-down effect of the first input transistor N1, the second input transistor N2, the fourth input transistor N4, and the fifth input transistor N5, the drain voltages of the first output transistor N7 and the second output transistor N8 reach the flip voltage. When the drain voltage of the first input transistor N1 is higher than the drain voltage of the second input transistor N2, the first output transistor N7 and the fourth output transistor P2 gradually turn off, while the second output transistor P1 and the third output transistor N8 gradually turn on. The ability to pull down the drain voltage of the fourth output transistor P2 becomes stronger, and the ability to pull up the drain voltage of the third output transistor P1 becomes stronger.

[0111] During the decision-making phase, the first output transistor N7 and the fourth output transistor P2 are turned off, while the second output transistor P1 and the third output transistor N8 are turned on. The drain voltage of the fourth output transistor P2 continues to be pulled down, and the drain voltage of the third output transistor P1 is pulled up. After the drain voltage of the fourth output transistor P2 is pulled to a high level and the drain voltage of the third output transistor P1 is pulled to a low level, the drain voltages of the third output transistor P1 and the fourth output transistor P2 are maintained.

[0112] When the next working cycle arrives, the clock signal goes low, and the drain voltages of the third output transistor P1 and the fourth output transistor P2 are reset to high by the third clock transistor P5 and the fourth clock transistor P6.

[0113] In the above embodiments, setting the second input signal and second reference signal at the current moment based on the first input signal and first reference signal received by the first input circuit at the previous moment can effectively eliminate inter-symbol interference at the first input terminal of the first input circuit and improve the accuracy of the comparator. Due to inter-symbol interference, the difference between the differential signals generated by the first input signal and the second input signal at the two input terminals of the first input circuit becomes smaller. The feedback transistor in the input circuit pulls the voltage at the output terminal of the input circuit at different rates, accelerating the difference between the differential signals at the output terminal, thereby shortening the time the comparator is in the sampling phase and reducing the power consumption of the comparator. In addition, the reset is achieved by the first reset circuit directly pulling the voltage at the output terminal of the input circuit, which can shorten the reset time of the output terminal of the input circuit, thereby improving the response rate of the comparator.

[0114] Figure 5 A circuit diagram of a comparator provided in another embodiment of this application is shown below. Figure 5 As shown, the comparator provided in this application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, an output circuit 105, a first reset circuit 1061, a second reset circuit 1062, and a third reset circuit 1063.

[0115] The first input circuit 101 includes a first input transistor P1, a second input transistor P2, and a third input transistor P3. The second terminal of the first input transistor P1 is connected to the first terminal of the third input transistor P3, the second terminal of the second input transistor P2 is connected to the first terminal of the third input transistor P3, and the second terminal of the third input transistor P3 is connected to the power supply terminal.

[0116] The first feedback unit 1031 includes a first feedback transistor P9, and the second feedback unit 1032 includes a second feedback transistor P10. The control terminal of the first feedback transistor P9 is connected to the first terminal of the first input transistor P1, and the first terminal of the first feedback transistor P9 is connected to the first terminal of the second input transistor P2. The control terminal of the second feedback transistor P10 is connected to the first terminal of the second input transistor P2, and the first terminal of the second feedback transistor P10 is connected to the first terminal of the first input transistor P1. The second terminals of both the first feedback transistor P9 and the second feedback transistor P10 are connected to the first terminal of the third input transistor P3.

[0117] The second input circuit 102 includes a fourth input transistor P4, a fifth input transistor P5, and a sixth input transistor P6. The second terminal of the fourth input transistor P4 is connected to the first terminal of the sixth input transistor P6, the second terminal of the fifth input transistor P5 is connected to the first terminal of the sixth input transistor P6, and the second terminal of the sixth input transistor P6 is connected to the power supply terminal.

[0118] The third feedback unit 1033 includes a third feedback transistor P11, and the fourth feedback unit 1034 includes a fourth feedback transistor P12. The control terminal of the third feedback transistor P11 is connected to the first terminal of the fourth input transistor P4, and the first terminal of the third feedback transistor P11 is connected to the first terminal of the fifth input transistor P5. The control terminal of the fourth feedback transistor P12 is connected to the first terminal of the fifth input transistor P5, and the first terminal of the fourth feedback transistor P12 is connected to the first terminal of the fourth input transistor P4. The second terminals of both the third feedback transistor P11 and the fourth feedback transistor P12 are connected to the first terminal of the sixth input transistor P6.

[0119] The output circuit 105 includes a first output transistor P7, a second output transistor P8, a third output transistor N1, and a fourth output transistor N2. The first terminal of the first output transistor P7 is connected to the second terminal of the third output transistor N1, and the first terminal of the second output transistor P8 is connected to the second terminal of the fourth output transistor N2. The control terminal of the first output transistor P7 is connected to the control terminal of the third output transistor N1, and then to the second terminal of the fourth output transistor N2. Similarly, the control terminal of the second output transistor P8 is connected to the control terminal of the fourth output transistor N2, and then to the second terminal of the third output transistor N1.

[0120] The first reset circuit 1061 includes a first clocked transistor N5 and a second clocked transistor N6. The second terminal of the first clocked transistor N5 is connected to the first output terminal of the first input circuit 101, and the second terminal of the second clocked transistor N6 is connected to the second output terminal of the first input circuit 101. The first terminal of the second clocked transistor N6 is connected to the first terminal of the first clocked transistor N5 and then connected to a power supply. The second reset circuit 1062 includes a third clocked transistor N3, and the second terminal of the third clocked transistor N3 is connected to the first output terminal of the output circuit 105. The third reset circuit 1063 includes a fourth clocked transistor N4, and the second terminal of the fourth clocked transistor N4 is connected to the second output terminal of the output circuit 105.

[0121] In one embodiment, when the first feedback transistor P9, the second feedback transistor P10, the third feedback transistor P11, the fourth feedback transistor P12, and the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0122] In one embodiment, when both the first output transistor P7 and the second output transistor P8 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0123] When the third output transistor N1 and the fourth output transistor N2 are both N-type transistors, and the first clocked transistor N5, the second clocked transistor N6, the third clocked transistor N3 and the fourth clocked transistor N4 are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0124] The following describes the four working stages of a comparator. Figure 5 The working process of the comparator shown is as follows:

[0125] and Figure 4 The difference in the comparator shown is that, during the reset phase, after the clock signal is inverted to a high level, it is input to the control terminals of the third input transistor P3 and the sixth input transistor P6, causing the first input circuit 101 and the second input circuit 102 to stop working. After the clock signal is inverted to a high level, the first clocked transistor N5 and the second clocked transistor N6 are turned on, pulling the voltages at the first and second output terminals of the first input circuit 101 to a low level. After the clock signal is inverted to a high level, the third clocked transistor N3 and the fourth clocked transistor N4 are turned on, pulling the drain voltages of the third output transistor N1 and the fourth output transistor N2 to a low level.

[0126] and Figure 4The difference between the comparators shown is that, during the sampling phase, the clock signal is inverted to a high level and then input to each clock-controlled transistor, as well as the third input transistor P3 and the sixth input transistor P6, causing the first reset circuit 1061 to the third reset circuit 1063 to stop working, and the first input circuit 101 and the second input circuit 102 to work.

[0127] The sampling stage is described below by considering the different values ​​of the first and second input signals.

[0128] In the first scenario: At the current moment, the first input signal is greater than the first reference signal, while at the previous moment, the first input signal was less than the first reference signal. Based on the relationship between the first input signal and the first reference signal at the previous moment, the second input signal is set to be less than the first reference signal. For example: at the previous moment, the first input signal was 0.2V and the first reference signal was 0.3V. At the current moment, the first input signal is 0.4V, the first reference signal is 0.3V, the second input signal is 0V, and the second reference signal is 1.2V.

[0129] When inter-symbol interference (ISI) is present, meaning the first input signal from the previous moment interferes with the first input signal at the current moment, assuming the amplitude of the first input terminal In1 of the first input circuit 101 is 0.3V, the pull-up capability of the first input transistor P1 is equal to the pull-up capability of the second input transistor P2, and the drain voltages of the first and second input transistors are equal. However, the pull-up capability of the fourth input transistor P4 is higher than that of the fifth input transistor P5. Under the pull of the fourth and fifth input transistors P4 and P5, and also under the pull of the first and second positive feedback circuits 103 and 104, the voltage at the second terminal of the first input transistor P1 is higher than the voltage at the second terminal of the second input transistor P2.

[0130] In the absence of inter-symbol interference (ISI), the first input signal and the first reference signal will cause the voltage at the second terminal of the first input transistor P1 to be higher than the voltage at the second terminal of the second input transistor P2. That is, ISI is eliminated by adjusting the first input circuit 101 through the second input circuit 102. Typically, the pull-down capabilities of the fourth input transistor P4 and the fifth input transistor P5 are relatively small. When a voltage difference appears between the drains of the fourth input transistor P4 and the fifth input transistor P5, two positive feedback circuits accelerate the voltage difference between their drains, which can shorten the sampling time and reduce power consumption.

[0131] In the second scenario, if the first input signal is greater than the first reference signal at the current and previous times, the second input signal is set to be greater than the first reference signal. For example, at the previous time, the first input signal was 0.4V and the first reference signal was 0.3V. At the current time, the first input signal is 0.4V, the first reference signal is 0.3V, the second input signal is 1.2V, and the second reference signal is 0V.

[0132] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal IP1 of the first input circuit 101 remains at 0.4V, the pull-up capability of the first input transistor P1 is greater than that of the second input transistor P2, and the drain voltage of the first input transistor P1 is greater than that of the second input transistor P2. However, the pull-up capability of the fourth input transistor P4 is less than that of the fifth input transistor P5. The second input circuit 102 will pull the voltages of the first and second input transistors P1 and P2 in a direction that makes the voltage of the first input transistor P1 less than the voltage of the second input transistor P2. However, the pull-up capability of the transistors in the second input circuit 102 is α times the pull-up capability of the corresponding transistors in the first input circuit 101, where α is less than 0.5. Therefore, the pull-up capability of the transistors in the second input circuit 101 is much weaker than that of the transistors in the first input circuit 102. The voltage at the second terminal of the first input transistor P1 is still greater than the voltage at the second terminal of the second input transistor P2.

[0133] In the third scenario, at the current moment, the first input signal is less than the first reference signal, while at the previous moment, the first input signal was greater than the first reference signal. Therefore, the second input signal is set to be greater than the first reference signal. For example, at the previous moment, the first input signal was 0.4V and the first reference signal was 0.3V. At the current moment, the first input signal is 0.2V, the first reference signal is 0.3V, the second input signal is 1.2V, and the second reference signal is 0V.

[0134] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal In1 of the first input circuit 101 is 0.3V, the pull-up capability of the first input transistor P1 is equal to that of the second input transistor P2, and the drain voltages of the first input transistor P1 and the second input transistor P2 are equal. However, the pull-up capability of the fourth input transistor P4 is lower than that of the fifth input transistor P5. Under the pull of the fourth input transistor P4 and the fifth input transistor P5, and under the pull of the first positive feedback circuit 103 and the second positive feedback circuit 104, the voltage at the second terminal of the first input transistor P1 is less than the voltage at the second terminal of the second input transistor P2.

[0135] In the fourth scenario, at the current moment, the first input signal is less than the first reference signal, and at the previous moment, the first input signal was also less than the first reference signal. Therefore, the second input signal is set to be less than the first reference signal. For example, at the previous moment, the first input signal was 0.2V and the first reference signal was 0.3V. At the current moment, the first input signal is 0.2V, the first reference signal is 0.3V, the second input signal is 0V, and the second reference signal is 1.2V.

[0136] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal In1 of the first input circuit 101 remains at 0.2V, the pull-up capability of the first input transistor P1 is less than that of the second input transistor P2, and the drain voltage of the first input transistor P1 is less than that of the second input transistor P2. The pull-up capability of the fourth input transistor P4 is greater than that of the fifth input transistor P5. The second input circuit 102 will pull the voltages of the first and second input transistors P1 and P2 in a direction that makes the voltage of the first input transistor P1 greater than the voltage of the second input transistor P2. However, the pull-up capability of the transistors in the second input circuit is α times that of the transistors in the first input circuit, where α is less than 0.5. Therefore, the pull-up capability of the transistors in the second input circuit is much weaker than that of the transistors in the first input circuit, and the voltage at the second terminal of the first input transistor P1 is still less than the voltage at the second terminal of the second input transistor P2.

[0137] During the regeneration phase, due to the pull-down effect of the first input transistor P1, the second input transistor P2, the fourth input transistor P4, and the fifth input transistor P5, the drain voltage of the first output transistor P7 and the drain voltage of the second output transistor P8 reach the flip voltage. When the drain voltage of the first input transistor P1 is higher than the drain voltage of the second input transistor P2, the first output transistor P7 and the fourth output transistor N2 gradually turn on, while the second output transistor N1 and the third output transistor N2 gradually turn off. The ability to pull down the drain voltage of the fourth output transistor N2 becomes stronger, and the ability to pull up the drain voltage of the third output transistor N1 becomes stronger.

[0138] During the decision-making phase, the first output transistor N7 and the fourth output transistor N2 are turned on, while the second output transistor N1 and the third output transistor N8 are turned off. The drain voltage of the fourth output transistor N2 continues to be pulled down, and the drain voltage of the third output transistor N1 is pulled up. After the drain voltage of the fourth output transistor N2 is pulled low and the drain voltage of the third output transistor N1 is pulled high, the drain voltages of the third output transistor N1 and the fourth output transistor N2 are maintained.

[0139] When the next working cycle arrives, the clock signal goes low, and the drain voltages of the third output transistor N1 and the fourth output transistor N2 are reset to low by the third clock transistor N3 and the fourth clock transistor N4.

[0140] In the above technical solution, setting the second input signal and the second reference signal at the current moment based on the first input signal and the first reference signal received by the first input circuit at the previous moment can effectively eliminate inter-symbol interference at the first input terminal of the first input circuit and improve the accuracy of the comparator.

[0141] Figure 6 A structural block diagram of a comparator provided in this application, such as... Figure 6 As shown, the comparator includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0142] The second input circuit includes at least one controllable input module. Each input module includes a fourth input transistor, a fifth input transistor, and a sixth input transistor. The control terminal of the fourth input transistor is used to receive a second reference signal, and the control terminal of the fifth input transistor is used to receive a second input signal. The first terminal of the sixth input transistor is connected to the second terminals of the fourth and fifth input transistors. The sixth input transistor is used to receive a clock signal, which can control the operating state of the controllable input module, thereby controlling the number of operating controllable input modules.

[0143] The second positive feedback circuit 104 includes at least one controllable positive feedback module 1040, wherein each controllable positive feedback module includes a third feedback unit 1041, a fourth feedback unit 1042, a first switch 1043, and a second switch 1044. The third feedback unit 1041 and the fourth feedback unit 1042 are each provided with a control terminal and a first terminal.

[0144] The control terminal of the third feedback unit 1041 is connected to the first output terminal of the second input circuit 102 via the first switch 1043, and the first terminal of the third feedback unit 1041 is connected to the second output terminal of the second input circuit 102. The control terminal of the fourth feedback unit 1042 is connected to the second output terminal of the second input circuit 102 via the second switch 1044, and the first terminal of the fourth feedback unit 1042 is connected to the first output terminal of the second input circuit 102.

[0145] The first switch 1043 controls whether the third feedback unit 1041 generates positive feedback, and the second switch 1044 controls whether the fourth feedback unit 1042 generates positive feedback. By controlling the closing and opening of the first switch 1043 and the second switch 1044, the controllable positive feedback module 1040 can be controlled to generate positive feedback. When both the first switch 1043 and the second switch 1044 are closed, the controllable positive feedback module 1040 can accelerate the difference between the second differential signals at the output of the second input circuit through the positive feedback mechanism. When both the first switch 1043 and the second switch 1044 are open, the controllable positive feedback module 1040 is disconnected from the second input circuit and cannot generate positive feedback at the output of the second input circuit.

[0146] When the comparator is operating, the number of controllable positive feedback modules generating positive feedback can be controlled, thereby controlling the ability of the second positive feedback circuit to pull the difference between the second differential signals. This controls, on the one hand, the time the comparator spends in the sampling phase, ensuring the comparator's response rate. On the other hand, it balances the ability of the second positive feedback circuit to pull the voltage at the output of the second input circuit with the ability of the second input signal and the second reference signal to pull the voltage at the output of the second input circuit, preventing the second positive feedback circuit from affecting the polarity of the second differential signal generated at the output of the second input circuit. Furthermore, the number of operating controllable input modules can be controlled, and based on this number, the number of controllable positive feedback modules generating positive feedback can be controlled, ensuring that the polarity of the signal after the first differential signal and the second differential signal are added is the same as the polarity of the first differential signal. The second differential signal only serves to adjust the first differential signal, ensuring that the comparator can accurately output the comparison result based on the first input signal and the first reference signal.

[0147] Figure 7 and Figure 8 For based on Figure 6 One specific circuit diagram of the comparator shown is provided, in which the first input circuit 101, the second input circuit 102, and the output circuit 105 have the same structure. Figure 4 The comparator shown is the same and will not be described again here. The comparator also includes a first reset circuit 1061, a second reset circuit 1064, and a third reset circuit 1065. These three reset circuits are also already... Figure 4 The embodiments shown are described in detail and will not be repeated here.

[0148] The following is combined Figure 7 and Figure 8 Describe the specific circuit structure of each controllable positive feedback module in the positive feedback circuit. The third feedback unit 1041 includes a third feedback transistor N11, the control terminal of the third feedback transistor N11 serves as the control terminal of the third feedback unit 1041, and the first terminal of the third feedback transistor N11 serves as the second terminal of the third feedback unit 1041.

[0149] The control terminal of the third feedback transistor N11 is connected to the first terminal of the third feedback transistor N11 through the first switch 1045. The first switch 1043 includes a first transmission gate G1, which is controlled by a first enable signal EN1. The first enable signal EN1 is generated according to the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

[0150] The fourth feedback unit 1042 includes a fourth feedback transistor N12. The control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 1042, and the first terminal of the fourth feedback transistor N12 is the second terminal of the fourth feedback unit 1042.

[0151] The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fourth feedback transistor N12 through the second switch 1044. The second switch 1044 includes a second transmission gate G2, which is controlled by a second enable signal EN2. The second enable signal EN2 is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

[0152] By controlling the switching states of the first transmission gate G1 and the second transmission gate G2 with the enable signal, the third feedback transistor N11 and the fourth feedback transistor N12 can be controlled to provide a positive feedback mechanism, thereby adjusting the number of controllable positive feedback modules participating in the positive feedback.

[0153] In one embodiment, the second positive feedback circuit 104 further includes a first zero switch K10 and a second zero-zero switch K00. The control terminal of the third feedback unit 1041 is also connected to the ground terminal through the first zero switch K10. The first zero switch K10 is used to conduct when the first transmission gate G1 is closed, so that the transistor in the third feedback unit 1041 is not floating, reducing external interference to the comparator. The control terminal of the fourth feedback unit 1042 is also connected to the ground terminal through the second zero-zero switch K00. The second zero-zero switch K00 is used to conduct when the second transmission gate G2 is closed, so that the transistor in the fourth feedback unit 1042 is not floating, reducing external interference to the comparator.

[0154] In one embodiment, if the third feedback transistor N11, the fourth feedback transistor N12, the first zero switch K10, and the zero-zero switch K00 are N-type transistors, the drain of the N-type transistor is the first terminal, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal. The first terminal of the first zero switch K10 is connected to the control terminal of the third feedback transistor N11, the first terminal of the zero-zero switch K00 is connected to the control terminal of the fourth feedback transistor N12, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are grounded, so as to pull down the third feedback transistor N11 to a low level when the first transmission gate G1 is closed, and pull down the fourth feedback transistor N12 to a low level when the second transmission gate G2 is closed.

[0155] Figure 9 and Figure 10 For based on Figure 6 One specific circuit diagram of the comparator shown is provided, in which the first input circuit 101, the second input circuit 102, and the output circuit 105 have the same structure. Figure 5 The comparators shown are the same and will not be described again here. The connection relationships between the third feedback unit 1041, the fourth feedback unit 1042, the first switch 1043, and the second switch 1044 of each controllable positive feedback module 1040 in the second positive feedback circuit 104 have been described. Figure 8 The structure is described in detail here, and will not be repeated.

[0156] It should be noted here that if the third feedback transistor P11, the fourth feedback transistor P12, the first zero switch K10, and the zero-zero switch K00 are P-type transistors, the drain of the P-type transistor is the first terminal, the source of the P-type transistor is the second terminal, the gate of the P-type transistor is the control terminal, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are connected to the power supply terminal.

[0157] In the above embodiments, the first input circuit includes multiple controllable input modules, and the second positive feedback circuit includes multiple controllable positive feedback modules. By controlling the number of controllable positive feedback modules providing the positive feedback mechanism, the ability of the second positive feedback circuit to pull the voltages at the two output terminals of the second input circuit can be adjusted, thereby controlling the time the comparator is in the sampling phase. It can also balance the pulling power of the positive feedback circuit, the input signal, and the reference signal on the output terminal of the second input circuit, improving the comparator's response rate and accuracy. By controlling the number of controllable input modules, the ability of the second input circuit to pull the voltage at the output terminal of the first input circuit can be adjusted, preventing the second input circuit from having an excessively strong pulling power that could affect the polarity of the differential signal at the output terminal of the first input circuit. Furthermore, by setting the second input signal and the second reference signal at the current moment based on the first input signal and the first reference signal received by the first input circuit at the previous moment, inter-symbol interference at the first input terminal of the first input circuit can be effectively eliminated, thereby improving the comparator's accuracy.

[0158] like Figure 11 As shown, an embodiment of this application provides a decision feedback equalization circuit, including the four comparators described in the above embodiment, which are sequentially labeled as first comparator 100, second comparator 200, third comparator 300 and fourth comparator 400.

[0159] In this configuration, the third input terminal Vref2 of the first comparator 100 is connected to the first output terminal P270B of the fourth comparator 400, and the fourth input terminal In2 of the first comparator 100 is connected to the second output terminal P270 of the fourth comparator 400. The third input terminal Vref2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100, and the fourth input terminal In2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100. The third input terminal Vref2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200, and the fourth input terminal In2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200. The third input terminal Vref2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 400, and the fourth input terminal In2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300.

[0160] The first input terminal In1 of the first comparator 100 to the fourth comparator 400 all receive the first input signal, and the second input terminal Vref1 of the first comparator 100 to the fourth comparator 400 all receive the first reference signal.

[0161] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1", at the current moment, the third input terminal Vref2 of the first register 100 receives a low level, and the fourth input terminal In2 of the first register 100 receives a high level. That is, the signal at the third input terminal Vref2 is less than the signal at the fourth input terminal In2. Assuming that the first input signal is also greater than the first reference signal at the current moment, inter-symbol interference will still make the first input signal greater than the first reference signal, and the first register 100 will still output the number "1".

[0162] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1". At the current moment, the signal at the third input terminal Vref2 of the first register is less than the signal at the fourth input terminal In2. Assuming that the first input signal is less than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly greater than the first reference signal, the first register 100 will still output the number "0" because the signal at the third input terminal Vref2 is less than the signal at the fourth input terminal In2.

[0163] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0", at the current moment, the signal at the third input terminal Vref2 of the first register 100 is greater than the signal at the fourth input terminal In2. Assuming that the first input signal is also less than the first reference signal at the current moment, inter-symbol interference will still cause the first input signal to be less than the first reference signal, and the first register 100 will still output the number "0".

[0164] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal Vref2 at the third input terminal of the first register 100 is greater than the signal at the fourth input terminal In2. Assuming that the first input signal is greater than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly less than the first reference signal, the first register 100 will still output the number "1" because the signal at the third input terminal is greater than the signal at the fourth input terminal.

[0165] The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and will not be repeated here.

[0166] Figure 11 The decision feedback equalization circuit shown is a first-order circuit. To achieve better elimination of inter-symbol interference, multi-order circuits are usually used. Figure 12 This is a schematic diagram of the effect of a fourth-order decision feedback equalizer circuit. Tap1 to tap4 represent the first-order to fourth-order decision feedback equalizer circuits, respectively. Figure 12 As shown in Figure 1, the actual waveform of the first input signal under inter-symbol interference (ISI) is relatively flat when the first input signal switches from high to low level, indicating a possibility of misidentification of the first input signal as high. The fourth-order decision feedback equalization circuit effectively eliminates ISI, resulting in the equivalent waveform of the first input signal input to the equalization circuit, as shown in Figure 2, with a steeper falling edge.

[0167] In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the second clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the second clock signal of the fourth comparator 400.

[0168] In one embodiment, the voltage switching time T at the output terminals of the first comparator 100 to the fourth comparator 400 is... FB Both are less than the time interval 1U1 between the first clock signal and the second clock signal, such as Figure 13As shown, when the switching time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal. This ensures that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0169] In one embodiment, the decision feedback equalization circuit further includes four registers, labeled sequentially as first register 500, second register 600, third register 700, and fourth register 800. The input of first register 500 is connected to the two outputs of first comparator 100, the input of second register 600 is connected to the two outputs of second comparator 200, the input of third register 700 is connected to the two outputs of third comparator 300, and the input of fourth register 800 is connected to the two outputs of fourth comparator 400. The four registers are used to store the comparison results of the four corresponding comparators: D0 is the result output by first register 500, D90 is the result output by second register 600, D180 is the result output by third register 700, and D270 is the result output by fourth register 800.

[0170] In the above technical solution, the two output terminals of the fourth register are connected to the two input terminals of the first register, and the two output terminals of the first register are connected to the two input terminals of the second register, and so on, to form a decision feedback equalization circuit. The other two input terminals of the four registers receive the first input signal and the first reference signal. Under the control of the output terminal signals of the four registers, the inter-symbol interference caused by the continuous input of the first input signal in the register can be effectively eliminated.

[0171] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0172] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A decision feedback equalization circuit, comprising: The comparator comprises four comparators, which are sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator; Each of the comparators is provided with four input ends and two output ends, and comprises: a first input circuit provided with two input ends and two output ends, the two input ends serving as first and second input ends of the comparator, and used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage; a first positive feedback circuit connected with the two output ends of the first input circuit, and used for accelerating a difference between the first differential signals; a second input circuit provided with two input ends and two output ends, the two input ends serving as third and fourth input ends of the comparator, and the two output ends being connected with the two output ends of the first input circuit, and used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage; a second positive feedback circuit connected with the two output ends of the second input circuit, and used for accelerating a difference between the second differential signals; an output circuit provided with two input ends and two output ends, the two output ends serving as output ends of the comparator, and the two input ends being connected with the two output ends of the first input circuit, and used for amplifying and latching a voltage signal of the output end of the first input circuit and a voltage signal of the output end of the second input circuit in a regeneration stage, so as to output a comparison result; the first input end of the first comparator is used for receiving the first input signal, the second input end is used for receiving the first reference signal, the third input end is directly connected with the first output end of the fourth comparator and used for receiving the second input signal, and the fourth input end is directly connected with the second output end of the fourth comparator and used for receiving the second reference signal; the first input end of the second comparator is used for receiving the first input signal, the second input end is used for receiving the first reference signal, the third input end is directly connected with the first output end of the first comparator and used for receiving the second input signal, and the fourth input end is directly connected with the second output end of the first comparator and used for receiving the second reference signal; the first input end of the third comparator is used for receiving the first input signal, the second input end is used for receiving the first reference signal, the third input end is directly connected with the first output end of the second comparator and used for receiving the second input signal, and the fourth input end is directly connected with the second output end of the second comparator and used for receiving the second reference signal; the first input end of the fourth comparator is used for receiving the first input signal, the second input end is used for receiving the first reference signal, the third input end is directly connected with the first output end of the third comparator and used for receiving the second input signal, and the fourth input end is directly connected with the second output end of the third comparator and used for receiving the second reference signal.

2. The decision feedback equalization circuit of claim 1, wherein, The first positive feedback circuit comprises: a first feedback unit, a control end of which is connected with the first output end of the first input circuit, and a first end of which is connected with the second output end of the first input circuit; The second feedback unit has its control terminal connected to the second output terminal of the first input circuit, and its first terminal connected to the first output terminal of the first input circuit.

3. The decision feedback equalization circuit according to claim 2, characterized in that: The first feedback unit includes: a first feedback transistor, whose control terminal is the control terminal of the first feedback unit, and whose first terminal is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, whose control terminal is the control terminal of the second feedback unit, and whose first terminal is the first terminal of the second feedback unit.

4. The decision feedback equalization circuit of claim 3, wherein, The first input circuit includes: The first input transistor has a control terminal for receiving the first input signal, a first terminal for serving as the first output terminal of the first input circuit, and a first terminal connected to the first terminal of the first feedback transistor. The second input transistor has a control terminal for receiving the first reference signal, a first terminal for serving as the second output terminal of the first input circuit, and a first terminal connected to the first terminal of the second feedback transistor. The third input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor, and the second terminal of the second feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

5. The decision feedback equalization circuit of claim 1, wherein, The second positive feedback circuit includes: The third feedback unit has its control terminal connected to the first output terminal of the second input circuit, and its first terminal connected to the second output terminal of the second input circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the second input circuit, and its first terminal connected to the first output terminal of the second input circuit.

6. The decision feedback equalization circuit according to claim 5, characterized in that: The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

7. The decision feedback equalization circuit of claim 6, wherein, The second input circuit includes: The fourth input transistor has a control terminal for receiving the second reference signal, a first terminal for serving as the first output terminal of the second input circuit, and a first terminal for connecting to the first terminal of the third feedback transistor. The fifth input transistor has a control terminal for receiving the second input signal, a first terminal for serving as the second output terminal of the second input circuit, and a first terminal connected to the first terminal of the fourth feedback transistor. The sixth input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the fourth input transistor, the second terminal of the fifth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

8. The decision feedback equalization circuit of claim 7, wherein, The first feedback transistor to the fourth feedback transistor, and the first input transistor to the sixth input transistor are of the same type.

9. The decision feedback equalization circuit according to claim 8, characterized in that: The first feedback transistor and the second feedback transistor are the same size, the first input transistor and the second input transistor are the same size, and the size of the first feedback transistor is less than half the size of the first input transistor. The third feedback transistor and the fourth feedback transistor are the same size, the fourth input transistor and the fifth input transistor are the same size, and the size of the third feedback transistor is less than half the size of the fourth input transistor. The size of the fourth input transistor is less than half the size of the first input transistor.

10. The decision feedback equalization circuit according to claim 9, characterized in that: When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal; When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal.

11. The decision feedback equalization circuit of claim 1, wherein, The comparator further includes: A first reset circuit is connected between the first output terminal and the second output terminal of the first input circuit, and is used to reset the voltage at the first output terminal and the voltage at the second output terminal of the first input circuit. The second reset circuit is connected to the first output terminal of the output circuit and is used to reset the voltage of the first output terminal of the output circuit. The third reset circuit is connected to the second output terminal of the output circuit and is used to reset the voltage at the second output terminal of the output circuit.

12. The decision feedback equalization circuit of claim 11, wherein, The first reset circuit includes: The first clock-controlled transistor has a control terminal that receives a clock signal and a second terminal that is connected to the first output terminal of the first input circuit. The second clock transistor has a control terminal that receives the clock signal, a second terminal that is connected to the second output terminal of the first input circuit, and a first terminal that is connected to the first terminal of the first clock transistor. The second reset circuit includes: a third clock transistor, whose control terminal receives a clock signal, and whose second terminal is connected to the first output terminal of the output circuit; The third reset circuit includes a fourth clock transistor, whose control terminal receives a clock signal and whose second terminal is connected to the second output terminal of the output circuit.

13. The decision feedback equalization circuit of claim 12, wherein, The first, second, third, and fourth clocked transistors are of the same type.

14. The decision feedback equalization circuit of claim 1, wherein, The output circuit includes: The first output transistor has its second terminal being the first input terminal of the output circuit. The second output transistor has its second terminal being the second input terminal of the output circuit. The third output transistor has its control terminal connected to the control terminal of the first output transistor. Its control terminal is also connected to the second terminal of the fourth output transistor. Its second terminal is connected to the first terminal of the first output transistor. Its second terminal serves as the first output terminal of the output circuit. The fourth output transistor has its control terminal connected to the control terminal of the second output transistor, and its control terminal is also connected to the second terminal of the third output transistor. Its second terminal is connected to the first terminal of the second output transistor, and its second terminal serves as the second output terminal of the output circuit.

15. The decision feedback equalization circuit according to claim 14, characterized in that: Both the first output transistor and the second output transistor are N-type transistors, with the drain of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal. The third output transistor and the fourth output transistor are both P-type transistors, and the first to fourth clocked transistors are all P-type transistors. The source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. or Both the first input transistor and the second output transistor are P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. The third and fourth output transistors are both N-type transistors, and the first to fourth clocked transistors are all N-type transistors. The source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

16. The decision feedback equalization circuit of claim 1, wherein, The second positive feedback circuit includes at least one controllable positive feedback module; wherein each controllable positive feedback module includes: The third feedback unit has its control terminal connected to the first output terminal of the second input circuit via a first switch, and its first terminal connected to the second output terminal of the second input circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the second input circuit via a second switch, and its first terminal connected to the first output terminal of the second input circuit.

17. The decision feedback equalization circuit according to claim 16, characterized in that: The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The third feedback unit includes a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit.

18. The decision feedback equalization circuit according to claim 16, characterized in that: The first switch includes a first transmission gate, which is controlled by a first enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and a test mode signal. The second switch includes a second transmission gate, which is controlled by a second enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

19. The decision feedback equalization circuit of claim 16, wherein, The control terminal of the third feedback unit is also connected to the ground terminal or the power supply terminal through the first zero switch; the control terminal of the fourth feedback unit is also connected to the ground terminal or the power supply terminal through the zero zero switch.

20. The decision feedback equalization circuit according to claim 1, characterized in that: The phase of the first clock signal of the first comparator is 90° earlier than the phase of the second clock signal of the second comparator; The phase of the first clock signal of the first comparator is 180° earlier than the phase of the third clock signal of the third comparator; The phase of the first clock signal of the first comparator is 270° earlier than the phase of the fourth clock signal of the fourth comparator.

21. The decision feedback equalization circuit according to claim 20, characterized in that: The voltage flip time at the output of the first comparator and the voltage flip time at the output of the fourth comparator are both less than the time interval between the first clock signal and the second clock signal.

22. The decision feedback equalization circuit of any one of claims 1 to 21, wherein, Also includes: The four registers are labeled as Register 1, Register 2, Register 3, and Register 4, respectively. The input terminal of the first register is connected to the two output terminals of the first comparator; The input of the second register is connected to the two outputs of the second comparator; The input of the third register is connected to the two outputs of the third comparator; The input of the fourth register is connected to the two outputs of the fourth comparator.

Images