A ramp signal generating circuit

Abstract

The application provides a slope signal generating circuit. The slope signal generating circuit comprises: a high-bit weight encoder, which is adapted to receive a main clock signal and generate a driving signal based on the main clock signal; a cascade level trigger, which is adapted to receive the driving signal and generate at least two high-bit weight switch signals under the driving of the driving signal and an inverse signal thereof; and a high-bit weight current steering unit, which comprises at least two high-bit weight current steers connected in parallel in sequence, each of which is adapted to receive one of the at least two high-bit weight switch signals in sequence and turn on or off based on the received one high-bit weight switch signal, so that the high-bit weight current steering unit outputs an increasing or decreasing current to generate a slope signal. By using the application, not only the inter-symbol interference is reduced, but also the complex circuit design is avoided, the occupied area is saved, the power consumption is reduced, and the cost is saved.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a ramp signal generation circuit that can be used in image sensors. Background Technology

[0002] In the process of converting analog signals to digital signals in an image sensor, a ramp signal is required as the comparison level of the comparator.

[0003] In existing technologies, segmented current-controlled digital-to-analog converters are typically used to generate ramp signals to achieve a balance between circuit area, power consumption, and performance. However, an N-bit precision ramp signal requires an N-bit binary code as digital input, and further decoding of the high-order input from binary code to temperature code is necessary. This makes the circuit prone to inter-symbol interference, complex decoding circuitry, difficulty in constraining circuit timing, and severe glitches in the ramp output. Summary of the Invention

[0004] One object of the present invention is to provide an improved ramp signal generation circuit to reduce inter-symbol interference, reduce the difficulty of circuit design, reduce the difficulty of circuit timing constraints, and reduce glitches in the output signal.

[0005] An embodiment of the present invention provides a ramp signal generation circuit, comprising: a high-weight encoder adapted to receive a master clock signal and generate a drive signal based on the master clock signal; a cascaded level trigger adapted to receive the drive signal and generate at least two high-weight switching signals under the drive of the drive signal and its inverted signal; and a high-weight current rudder unit, comprising at least two high-weight current rudders connected in parallel in sequence, each high-weight current rudder adapted to receive one of the at least two high-weight switching signals in sequence, and to turn on or off based on the received high-weight switching signal, so that the high-weight current rudder unit outputs an increasing or decreasing current to generate a ramp signal.

[0006] Optionally, the high-weight encoder is adapted to use the master clock signal as the drive signal.

[0007] Optionally, the ramp signal generation circuit further includes: a low-weight encoder, adapted to receive an input signal and generate M low-weight switching signals based on the input signal, where M is a positive integer greater than or equal to 1; and a low-weight current steering unit connected in parallel with the high-weight current steering unit and located below the high-weight current steering unit; wherein the low-weight current steering unit includes M low-weight current steering units, and the M low-weight current steering units are adapted to receive one of the M low-weight switching signals respectively, and to turn on or off based on the received low-weight switching signal.

[0008] Optionally, the ramp signal generation circuit has an accuracy of N bits, and the high-weight current rudder unit includes 2 N-M -1 high-weight current rudder, 2 N-M -1 The current weight of each high-weight current rudder is 2. M , where N is a positive integer greater than M.

[0009] Optionally, M is greater than or equal to 2, and the current weights of the M low-weight current rudders are sequentially weighted in binary order from the least significant bit to the most significant bit. The current weight of the lowest-weight current rudder among the M low-weight current rudders is 2. 0 .

[0010] Optionally, the input signal includes a master clock signal; the low-weight encoder is adapted to divide the master clock signal M times to generate M low-weight frequency division signals as M low-weight switching signals; the M low-weight current rudders are adapted to receive one of the M low-weight frequency division signals respectively, and to turn on or off based on the received low-weight frequency division signal, so that the low-weight current rudder unit outputs an increasing or decreasing current to generate a ramp signal.

[0011] Optionally, the low-bit weight encoder includes 2 m-1 Frequency divider, 2 m-1 The frequency divider is suitable for dividing the master clock signal to generate M low-order frequency divider signals, where m takes values ​​from 1 to M.

[0012] Optionally, the high-weight encoder includes 2 M-1 Frequency divider or 2 M-2 Frequency divider, 2 M-1 Frequency divider or 2 M-2 A frequency divider is suitable for dividing the master clock signal to generate a high-order frequency-divided signal as a drive signal.

[0013] Optionally, the high-weight encoder is adapted to receive a control signal and, when the control signal is the first control signal, divide the master clock signal to generate a high-weighted frequency divider signal; the input signal includes the control signal; the low-weight encoder is adapted to divide the master clock signal M times to generate M low-weighted frequency divider signals when the control signal is the first control signal.

[0014] Optionally, the high-weight encoder is adapted to receive a control signal and use the master clock signal as a drive signal when the control signal is the second control signal; the input signal includes the control signal; the low-weight encoder is adapted to make all M low-weight switch signals turn off when the control signal is the second control signal; the M low-weight current rudders are adapted to receive the turn-off signal respectively and be completely disconnected based on the turn-off signal so that the low-weight current rudder unit does not output current.

[0015] Optionally, the cascaded level trigger includes at least two cascaded triggers to output at least two high-weighted switching signals, each trigger being adapted to output one of the at least two high-weighted switching signals.

[0016] Optionally, one of two adjacent flip-flops uses the drive signal as its clock signal, and the other uses the inverted signal of the drive signal as its clock signal.

[0017] Optionally, the cascaded level trigger includes an inverter adapted to receive a drive signal and invert it into an inverted signal for output to another.

[0018] Optionally, the trigger in the first stage takes either the power supply level or the ground level as input.

[0019] Optionally, each subsequent flip-flop takes the output of the preceding flip-flop as its input.

[0020] Optionally, the trigger includes a D trigger.

[0021] Compared with the prior art, the technical solutions of the embodiments of the present invention have beneficial effects.

[0022] For example, the ramp signal generation circuit provided in this embodiment of the invention can generate multiple switching signals based solely on the master clock signal, causing the corresponding multiple current sources to sequentially turn on or off from low to high bits, thereby generating a rising or falling ramp signal. This not only reduces inter-symbol interference, helping to improve image quality when applied to image sensors, but also avoids complex circuit design, saves space, reduces power consumption, and contributes to cost savings.

[0023] For example, the ramp signal generation circuit provided in this embodiment of the invention can also combine a high-weight current rudder unit and a low-weight current rudder unit to generate a ramp signal. In this case, the ramp signal generation circuit can also serve as a segmented current rudder type digital-to-analog converter, wherein the first current rudder unit serves as the temperature code unit of the segmented current rudder type digital-to-analog converter, and the second current rudder unit serves as the binary code unit of the segmented current rudder type digital-to-analog converter.

[0024] For example, compared to traditional segmented current-rudder type digital-to-analog converters, the ramp signal generation circuit provided in this embodiment of the invention only uses the master clock signal as input data for ramp signals with N-bit precision (traditional segmented current-rudder type digital-to-analog converters require N-bit data input). This effectively reduces the use of data input lines and reduces inter-symbol interference, thereby saving costs and improving the image quality of the image sensor.

[0025] For example, compared to the traditional segmented current-rudder type digital-to-analog converter where the temperature code unit generates the temperature code through a decoding circuit, the embodiments of the present invention use cascaded level triggers to generate high-weight switching signals. Each high-weight switching signal has the same path and delay, which not only simplifies the timing of constraining the high-weight current rudder unit and the low-weight current rudder unit, but also allows the circuit to operate at a higher clock frequency. At the same time, since decoding is not required, the glitches of the ramp signal are reduced, thereby improving the image quality of the image sensor.

[0026] For example, the ramp signal generation circuit provided in this embodiment of the invention can also determine, based on the control signal, whether to generate the ramp signal by the high-weight current rudder unit alone or by combining the high-weight current rudder unit and the low-weight current rudder unit, making it convenient and flexible to use.

[0027] For example, when the ramp signal is generated solely by the high-weight current rudder unit, the generation time of the ramp signal can be greatly shortened, making it applicable to scenarios that require rapid generation of ramp signals. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the ramp signal generation circuit in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a low-weight encoder in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a cascaded level trigger in an embodiment of the present invention;

[0031] Figure 4 This is a timing diagram of the high-weighted switching signal generated by the cascaded level flip-flops in this embodiment of the invention. The RST (RESET) signal is the reset signal for the flip-flops in the cascaded level flip-flops, the TCLK signal is the drive signal (clock signal) for the cascaded level flip-flops, and QT... <1> Signals, QT <2> Signal...QT Signals, QT<i+1> QT<i+2> ...QT<2 N-M -2> and QT<2 N-M -1> The signals are respectively the first high-weight switch signal, the second high-weight switch signal, ... the i-th high-weight switch signal, the (i+1)-th high-weight switch signal, the (i+2)-th high-weight switch signal, ... the 2nd high-weight switch signal. N -M -2 high-weighted switch signals and the 2nd N-M -1 high-weighted switch signal;

[0032] Figure 5 This is a schematic diagram of the ramp signal generated by the ramp signal generation circuit in an embodiment of the present invention. In this diagram, the RST (i.e., RESET) signal is the reset signal of the flip-flop in the cascaded level flip-flop, MCLK is the main clock signal, vramp is the ramp voltage signal generated by the ramp signal generation circuit, and state is the control signal. Detailed Implementation

[0033] To make the objectives, features, and beneficial effects of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described below are merely illustrative of the present invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the present invention are shown in the accompanying drawings, not all of the structures.

[0034] Figure 1 This is a schematic diagram of the ramp signal generation circuit in an embodiment of the present invention.

[0035] Specifically, the ramp signal generation circuit 10 provided in this embodiment of the invention may include a high-weight encoder 100, a cascaded level trigger 200, and a high-weight current steering unit 300.

[0036] In a specific implementation, the high-weight encoder 100 is adapted to receive the master clock signal MCLK and generate a drive signal TCLK based on the master clock signal MCLK.

[0037] In practice, the master clock signal MCLK can be generated by a phase-locked loop (PLL) or provided by digital circuitry.

[0038] In a specific implementation, the cascaded level trigger 200 is adapted to receive the drive signal TCLK and generate at least two high-weighted switching signals under the drive of the drive signal TCLK and its inverted signal.

[0039] In a specific implementation, the high-weight current rudder unit 300 includes at least two high-weight current rudders 310 connected in parallel in sequence. Each high-weight current rudder 310 is adapted to receive one of the high-weight switching signals from at least two high-weight switching signals in sequence, and to turn on or off based on the received high-weight switching signal, so that the high-weight current rudder unit 300 outputs an increasing or decreasing current to generate a ramp signal.

[0040] Specifically, each high-weight current rudder 310 includes a high-weight current source 311 and a high-weight current source switch 312. The high-weight current source switch 312 in each high-weight current rudder 310 is connected to the cascaded level trigger 200 and the high-weight current source 311 in the high-weight current rudder 310, respectively. It is adapted to receive a high-weight switch signal from the cascaded level trigger 200 and, based on the received high-weight switch signal, turn on or off the high-weight current source 311 in the high-weight current rudder 310, so that the high-weight current rudder unit 300 outputs an increasing or decreasing current to generate a ramp signal.

[0041] In some embodiments, at least two high-weight current rudders 310 in the high-weight current rudder unit 300 have the same current weight. That is, at least two high-weight current sources 311 in the at least two high-weight current rudders 310 have the same current weight (wherein, each high-weight current rudder 310 includes one high-weight current source 311).

[0042] Reference Figure 1 In some embodiments, the ramp signal generation circuit 10 may further include a low-weight encoder 400 and a low-weight current steering unit 500. The low-weight current steering unit 500 is connected in parallel with the high-weight current steering unit 300 and is located at the lower position of the high-weight current steering unit 300.

[0043] Specifically, the low-weight encoder 400 is adapted to receive an input signal and generate at least one low-weight switching signal based on the input signal. The low-weight current steering unit 500 includes at least one low-weight current steering 510, which is adapted to receive one of the at least one low-weight switching signals and to turn on or off based on the received low-weight switching signal.

[0044] In a specific implementation, the low-weight encoder 400 can generate M low-weight switching signals based on the input signal. The low-weight current steering unit 500 can include M low-weight current steering wheels 510. Each low-weight current steering wheel 510 is adapted to receive one of the M low-weight switching signals and to turn on or off based on the received low-weight switching signal. Here, M is a positive integer greater than or equal to 1.

[0045] In some embodiments, the low-weight current steering unit 500 may include at least two low-weight current steering units 510, and the at least two low-weight current steering units 510 are connected in parallel sequentially. That is, the low-weight current steering unit 500 includes M low-weight current steering units 510, and the M low-weight current steering units 510 are connected in parallel sequentially, wherein M is greater than or equal to 2.

[0046] In specific implementation, each low-weight current rudder 510 includes a low-weight current source 511 and a low-weight current source switch 512. The low-weight current source switch 512 in each low-weight current rudder 510 is adapted to receive a low-weight switch signal and, based on the received low-weight switch signal, turn on or off the low-weight current source 511 in the low-weight current rudder 510.

[0047] In some embodiments, the current weights of at least two low-weight current rudders 510 are sequentially increased in binary weight from low to high. That is, the current weights of at least two low-weight current sources 511 (one low-weight current rudder 510 includes one low-weight current source 511) among the at least two low-weight current rudders 510 are sequentially increased in binary weight from low to high.

[0048] In specific implementation, the current weight of the lowest-weighted current source 511 among at least two low-weighted current sources 511 can be 2. 0 Then, the current weights of at least two low-weight current sources 511 in the low-weight current steering unit 510, in order from low to high, can be expressed as 2. 0 2 1 2 2 ……2 M-1 , where M is greater than or equal to 2.

[0049] In practical implementation, the current source value of the least significant low-weight current source 511 can be represented as I0. Then, the current source values ​​of at least two low-weight current sources 511 in the low-weight current steering unit 510 can be represented sequentially as 2 in order from the least significant bit to the most significant bit. 0 I0, 2 1 I0, 2 2 I0……2 M-1 I0.

[0050] As previously described, the low-weight current source switch 512 in each low-weight current rudder 510 is adapted to receive a low-weight switch signal and, based on the received low-weight switch signal, to turn on or off the low-weight current source 511 in that low-weight current rudder 510. Corresponding to the case where the low-weight current rudder unit 500 includes at least two low-weight current rudders 510, the low-weight encoder 400 can generate at least two low-weight switch signals based on the input signal, to be output to at least two low-weight current source switches 512 in the at least two low-weight current rudders 510, wherein one low-weight current rudder 510 includes one low-weight current source switch 512.

[0051] In some embodiments, the input signal may include the master clock signal MCLK.

[0052] Accordingly, the low-weight encoder 400 is adapted to divide the master clock signal MCLK at least twice to generate at least two low-weight divider signals as at least two low-weight switching signals, wherein the low-weight switching signals and the low-weight divider signals correspond one-to-one. Each low-weight current rudder 510 is adapted to receive one of the at least two low-weight divider signals and to turn on or off based on the received low-weight divider signal, so that the low-weight current rudder unit 500 outputs an increasing or decreasing current to generate a ramp signal.

[0053] In some embodiments, the low-bit weight encoder 400 may include 2 m-1 Frequency divider. 2 m-1 The frequency divider is suitable for dividing the master clock signal MCLK at least twice to generate at least two low-order divided signals. That is, 2 m-1 The frequency divider is suitable for dividing the master clock signal MCLK by M times to generate M low-order frequency divider signals, where m takes values ​​from 1 to M, and M is greater than or equal to 2.

[0054] Figure 2 This is a schematic diagram of a low-weight encoder in an embodiment of the present invention.

[0055] Reference Figure 2 The low-weight encoder 400 can be based on 2 m-1 A frequency divider divides an input signal, such as the master clock signal MCLK, by 0, 2, 4, ..., and so on. M-1 Frequency division is performed to obtain M low-order frequency division signals QB respectively. <0> QB <1> QB <2> ...and QB <m-1>.

[0056] In practical implementation, M low-order frequency division signals QB <0> QB <1> QB <2> ...and QB <m-1>It is suitable for outputting to M low-weight current source switches 512 respectively. Among them, the low-weight current source switches 512 correspond one-to-one with the low-weight frequency divider signal.

[0057] Specifically, in order from low to high, the M low-weight current sources 511 can be referred to as the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511, ... and the Mth low-weight current source 511.

[0058] Accordingly, the M low-weight current source switches 512 corresponding to the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511, ... and the Mth low-weight current source 511 can be respectively called the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512, ... and the Mth low-weight current source switch 512.

[0059] Accordingly, M low-order frequency division signals QB <0> QB <1> QB <2> ...and QB <m-1>These can be referred to as the first low-order frequency division signal QB. <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> ...and the Mth low-order frequency division signal QB <m-1>.

[0060] In specific implementation, the first low-order frequency division signal QB <0> Suitable for outputting to the first low-weight current source switch 512, and the second low-weight frequency divider signal QB. <1> Suitable for outputting to the second low-weight current source switch 512, and the third low-weight frequency divider signal QB. <2> Suitable for output to the third low-weight current source switch 512, and so on, to the Mth low-weight frequency divider signal QB <m-1>Suitable for outputting to the Mth low-weight current source switch 512.

[0061] In practice, each low-weight current source switch 512 is adapted to control the corresponding low-weight current source 512 to be turned on or off based on a low-frequency division signal it receives.

[0062] As mentioned earlier, the M low-order frequency divider signals can be based on dividing the master clock signal MCLK by 0, 2, 4, ... and 2. M-1 It is generated by frequency division.

[0063] Specifically, the first low-order frequency division signal QB <0> The second low-order frequency divider signal QB is generated by dividing the master clock signal MCLK by 0. <1> The third low-order frequency divider signal QB is generated by dividing the master clock signal MCLK by 2. <2> Based on dividing the master clock signal MCLK by 4, the Mth low-order frequency division signal QB is generated similarly. <m-1>Based on the 2... M-1 It is generated by frequency division.

[0064] Assuming that, in order from low to high, the low-weight current steering unit 500 includes a first low-weight current source 511, a second low-weight current source 511, a third low-weight current source 511, and a fourth low-weight current source 511 connected in parallel, and a first low-weight current source switch 512, a second low-weight current source switch 512, a third low-weight current source switch 512, and a fourth low-weight current source switch 512, respectively, corresponding to the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511, and the fourth low-weight current source 511.

[0065] Accordingly, the low-order weight encoder 400 can generate the first low-order frequency division signal QB by dividing the master clock signal MCLK by 0, 2, 4, and 8, respectively. <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> .

[0066] In some embodiments, the master clock signal MCLK can be 1010101010101010…….

[0067] Accordingly, the first low-order frequency division signal QB <0> The second low-order frequency division signal QB is 1010101010101010……. <1> The third low-order frequency division signal QB is 1100110011001100……. <2> The fourth low-order frequency division signal QB is 1111000011110000……. <3> It is 1111111100000000…….

[0068] Therefore, in chronological order, at the first moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 1111 respectively; at the second moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 0111 respectively; at the third moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 1011 respectively; at the fourth moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> The values ​​are 0011 respectively; and so on, the first low-order frequency division signal QB at each time point can be obtained respectively. <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> .

[0069] In some embodiments, each low-weight current source switch 512 can control the corresponding low-weight current source 511 to turn on when the low-weight frequency divider signal it receives is 1, and control the corresponding low-weight current source 511 to turn off when the low-weight frequency divider signal it receives is 0.

[0070] Therefore, at the first moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control all of the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on based on the signal 1111.

[0071] At the second moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 to be disconnected and the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on based on the signal 0111.

[0072] At the third moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 to be turned on, control the second low-weight current source 511 to be turned off, and control the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on based on the signal 1011.

[0073] At the fourth moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 and the second low-weight current source 511 to be disconnected, and control the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on, based on the signal 0011.

[0074] Similarly, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on or off based on the signals at each time.

[0075] When the states (including on or off) of the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511, and the fourth low-weight current source 511 at each time are determined, the current value output by the low-weight current steering unit 500 at each time can be calculated based on the current source values ​​of the first low-weight current source 511, the second low-weight current source 511, and the third low-weight current source 511.

[0076] Specifically, at the first moment, the current value I1 output by the low-weight current steering unit 500 is 2. 0 *I0+2 1 *I0+2 2 *I0+2 3 *I0=15I0; At the second moment, the current value I2 output by the low-weight current steering unit 500 is 2. 1 *I0+2 2 *I0+2 3 *I0=14I0; At the third moment, the current value I3 output by the low-weight current steering unit 500 is 2. 0 *I0+2 2 *I0+2 3 *I0=13I0; At the fourth moment, the current value I4 output by the low-weight current steering unit 500 is 2. 2 *I0+2 3 *I0=12I0.

[0077] Similarly, the low-weighted current rudder unit 500 outputs current values ​​of 11I0, 10I0, 9I0, 8I0, etc. at the fifth, sixth, seventh, eighth, etc. times, respectively, until the output current value is 0 (in this case, the first low-weighted current source 511, the second low-weighted current source 511, the third low-weighted current source 511, and the fourth low-weighted current source 511 are all disconnected).

[0078] Therefore, it can be seen that the low-weight current steering unit 500 can output a continuously decreasing current to generate a descending ramp signal.

[0079] In other embodiments, the master clock signal MCLK can also be 0101010101010101...

[0080] Accordingly, the first low-order frequency division signal QB <0> The second low-order frequency division signal QB is 0101010101010101……. <1> The third low-order frequency division signal is QB, which is 0011001100110011……. <2> The fourth low-order frequency division signal is QB, which is 0000111100001111……. <3> It is 0000000011111111…….

[0081] Therefore, in chronological order, at the first moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 0000 respectively; at the second moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 1000 respectively; at the third moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> They are 0100 respectively; at the fourth moment, the first low-order frequency division signal QB <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> The values ​​are 1100 respectively; and so on, the first low-order frequency division signal QB at each time point can be obtained respectively. <0> Second low-order frequency division signal QB <1> The third low-order frequency division signal QB <2> and the fourth low-order frequency division signal QB <3> .

[0082] In some embodiments, each low-weight current source switch 512 can control the corresponding low-weight current source 511 to turn on when the low-weight frequency divider signal it receives is 1, and control the corresponding low-weight current source 511 to turn off when the low-weight frequency divider signal it receives is 0.

[0083] Therefore, at the first moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be completely disconnected based on the signal 0000.

[0084] At the second moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 to be turned on and the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be turned off based on the signal 1000.

[0085] At the third moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 to turn off, control the second low-weight current source 511 to turn on, and control the third low-weight current source 511 and the fourth low-weight current source 511 to turn off based on the signal 0100.

[0086] At the fourth moment, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511 and the second low-weight current source 511 to be turned on, and control the third low-weight current source 511 and the fourth low-weight current source 511 to be turned off, based on the signal 1100.

[0087] Similarly, the first low-weight current source switch 512, the second low-weight current source switch 512, the third low-weight current source switch 512 and the fourth low-weight current source switch 512 can control the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511 and the fourth low-weight current source 511 to be turned on or off based on the signal at each time.

[0088] When the states (including on or off) of the first low-weight current source 511, the second low-weight current source 511, the third low-weight current source 511, and the fourth low-weight current source 511 at each time are determined, the current value output by the low-weight current steering unit 500 at each time can be calculated based on the current source values ​​of the first low-weight current source 511, the second low-weight current source 511, and the third low-weight current source 511.

[0089] Specifically, at the first moment, the current value I1 output by the low-weight current steering unit 500 is 0; at the second moment, the current value I2 output by the low-weight current steering unit 500 is 2. 0 *I0=I0; At the third moment, the current value I3 output by the low-weight current steering unit 500 is 2. 1 *I0=2I0; At the fourth moment, the current value I4 output by the low-weight current steering unit 500 is 2 0 *I0+2 1 *I0=3I0.

[0090] Similarly, the low-weighted current steering unit 500 outputs current values ​​of 4I0, 5I0, 6I0, 7I0, ... at the fifth, sixth, seventh, and eighth moments, respectively, until the output current value is 15I0 (in this case, the first low-weighted current source 511, the second low-weighted current source 511, the third low-weighted current source 511, and the fourth low-weighted current source 511 are all turned on).

[0091] Therefore, it can be seen that the low-weight current steering unit 500 can output a continuously increasing current to generate a rising ramp signal.

[0092] The above describes an implementation of the low-weighted current steering unit 500 generating a ramp signal when there are four (i.e., M is 4) low-weighted current steering units 510. Implementations of the low-weighted current steering unit 500 generating a ramp signal when there are other numbers of low-weighted current steering units 510 can refer to the above implementation and will not be repeated here.

[0093] In a specific implementation, the precision of the ramp signal generation circuit 10 can be expressed as N bits. Furthermore, the high-weight current steering unit 300 in the ramp signal generation circuit 10 includes 2... N-M -1 high-weighted current rudder 310. Where N is a positive integer greater than M.

[0094] In specific implementation, the 2 in the high-weight current steering unit 300 N-M -1 The current weights of the high-weight current rudders 310 are the same. That is, 2 N-M -1 high-weight current rudder 310 in 2 N-M -1 The current weights of the high-weight current sources 311 are the same.

[0095] In practical implementation, it can be made 2 N-M -1 The current weight of each high-weighted current source 311 is 2. M And make 2 N -M -1 The current source value of the high-weighted current source 311 is 2. M I0.

[0096] As previously described, the high-weight current source switch 312 in each high-weight current rudder 310 is adapted to receive a high-weight switch signal from the cascaded level trigger 200 and, based on the received high-weight switch signal, turn on or off the high-weight current source 311 in the high-weight current rudder 310, so that the high-weight current rudder unit 300 outputs an increasing or decreasing current to generate a ramp signal.

[0097] Therefore, corresponding to 2 N-M -1 high-weighted current rudder 310, cascaded level trigger 200 needs to generate 2 N-M -1 high-weighted switch signal.

[0098] Figure 3 This is a schematic diagram of a cascaded level trigger in an embodiment of the present invention.

[0099] Reference Figure 3 The cascaded level trigger 200 may include 2 N-M -1 cascaded flip-flops 210. 2 N-M -1 cascaded flip-flops 210 are suitable for outputting 2 respectively based on the drive signal TCLK. N-M -1 high-weighted switching signal. Each flip-flop 210 is adapted to output 2 N-M -1 is one of the high-weighted switch signals.

[0100] Specifically, they are cascaded sequentially from front to back (where the first one is the first stage flip-flop 210, and the last one is the second stage flip-flop 210). N-M The -1 level flip-flop 210), and each flip-flop 210 in the cascaded level flip-flop 200 are adapted to sequentially output the first high-order weighted switching signal QT. <1> The second high-level weighting switch signal QT <2> ...the i-th high-order weighting switch signal QT ...and the 2nd N-M -1 high-weighted switching signal QT<2 N-M -1>.

[0101] In some embodiments, trigger 210 may include a D trigger.

[0102] In practical implementation, each subsequent stage of the flip-flop 210 uses the output of the preceding stage's flip-flop 210 as its input. Furthermore, the first stage of the flip-flop 210 uses either the power supply level VDD or ground level as its input.

[0103] In this embodiment of the invention, the driving signal TCLK and its inverted signal are used as the clock signals for each flip-flop 210 in the cascaded level flip-flop 200.

[0104] Specifically, one of the two adjacent flip-flops 210 uses the drive signal TCLK as its clock signal, and the other uses the inverted signal of the drive signal TCLK as its clock signal.

[0105] In some embodiments, the high-weight encoder 100 is adapted to output the master clock signal MCLK as a drive signal TCLK to the cascaded level flip-flop 200 as a clock signal.

[0106] In other embodiments, the high-weight encoder 100 is also adapted to divide the master clock signal MCLK and output the divided signal as a drive signal TCLK to the cascaded level flip-flop 200 as a clock signal.

[0107] Specifically, the high-weight encoder 100 may include 2 M-1 Frequency divider or 2 M-2 Frequency divider. 2 M-1 Frequency divider or 2 M-2 A frequency divider is suitable for dividing the master clock signal MCLK to generate 2. M-1 Frequency division or 2 M-2 The high-order frequency division signal is used as the drive signal TCLK. In this case, the high-order weighted current steering unit 300 and the low-order weighted current steering unit 500 can be linked to make the ramp signal generation circuit 10 output a stable ramp signal.

[0108] In practice, if the drive signal TCLK is a high-level signal, then the inverted signal of the drive signal TCLK is a low-level signal; if the drive signal TCLK is a low-level signal, then the inverted signal of the drive signal TCLK is a high-level signal.

[0109] For example, if the drive signal TCLK is 1, then its inverted signal is 0; or, if the drive signal TCLK is 0, then its inverted signal is 1.

[0110] In a specific implementation, the cascaded level trigger 200 also includes an inverter 220.

[0111] Specifically, the inverter 220 is connected to the odd-numbered or even-numbered flip-flop 210 in the cascaded level flip-flop 200 (i.e., the other of two adjacent flip-flops 210 in the cascaded level flip-flop 200), and is adapted to receive the drive signal TCLK and output the inverted signal of the drive signal TCLK to the odd-numbered or even-numbered flip-flop 210 connected to it (i.e., the other of two adjacent flip-flops 210 in the cascaded level flip-flop 200).

[0112] Reference Figure 3 In some embodiments, the inverter 220 is connected to the even-numbered flip-flop 210 in the cascaded level flip-flop 200, and is adapted to receive the drive signal TCLK and output the inverted signal of the drive signal TCLK to the even-numbered flip-flop 210.

[0113] Figure 4 This is a timing diagram of the high-weighted switching signal generated by the cascaded level triggers in an embodiment of the present invention.

[0114] Reference Figure 4 In some embodiments, when the reset signal RST of all the flip-flops 210 in the cascaded level flip-flops 200 is a low level signal, each flip-flop 210 in the cascaded level flip-flops 200 sequentially outputs the first high-order weighted switching signal QT. <1> The second high-level weighting switch signal QT <2> ...the i-th high-order weighting switch signal QT ...and the 2nd N-M -1 high-weighted switching signal QT<2 N-M -1> can all be 0.

[0115] The cascaded level trigger 200 begins operation when the reset signal RST of all triggers 210 in the cascaded level trigger 200 is high. In this case, all triggers 210 in the cascaded level trigger 200 are active high. Furthermore, each trigger 210 in the cascaded level trigger 200 outputs its first high-weighted switching signal QT sequentially according to time order. <1> The second high-level weighting switch signal QT <2> ...the i-th high-order weighting switch signal QT ...and the 2nd N-M -1 high-weighted switching signal QT<2 N-M -1> can all be 1.

[0116] In practical implementation, the duration of the high-level reset signal RST can be determined according to the specific application scenario. For example, the duration of the high-level reset signal RST can be twice the duration of the clock signal of the ramp signal generation circuit 10. N -1 times.

[0117] As mentioned above, in this embodiment of the invention, the drive signal TCLK is used as the clock signal for each of the flip-flops 210 in the cascaded level flip-flops 200.

[0118] Continue to refer to Figure 3 In some embodiments, the odd-numbered flip-flop 210 in the cascaded level flip-flop 200 uses the drive signal TCLK as the clock signal, and the even-numbered flip-flop 210 in the cascaded level flip-flop 200 uses the inverted signal of the drive signal TCLK as the clock signal.

[0119] By inverting the clocks of two adjacent flip-flops 210 in the cascaded level flip-flop 200, a high-weighted switching signal can be output on both the rising and falling edges of the drive signal TCLK.

[0120] Continue to refer to Figure 4 When the first toggling edge (rising edge) of the drive signal TCLK arrives, the first stage flip-flop 210 (refer to...) Figure 3 Its input is the power supply level VDD, and its output is the first high-order weighted switching signal QT. <1> =1, and with the first high-weighted switching signal QT <1> This serves as the input to the second-stage flip-flop 210. When the second toggling edge (falling edge) of the drive signal TCLK arrives, the second-stage flip-flop 210 outputs the second high-weighted switching signal QT. <2> =1, and with the second high-weighted switching signal QT <2> This is used as the input to the third-stage flip-flop 210. Similarly, the (i-1)th high-order weighted switching signal QT output from the (i-1)th stage flip-flop 210 is used. <i-1>As the input of the i-th stage flip-flop 210, when the i-th toggling edge of the drive signal TCLK arrives, the i-th stage flip-flop 210 outputs the i-th high-order weighted switching signal QT. =1, until the 2nd N-M -1 level trigger 210 output 2nd N-M -1 high-weighted switching signal QT<2 N-M -1>=1.

[0121] In other embodiments, the first toggle edge of the drive signal TCLK may also be a falling edge. Correspondingly, the second toggle edge of the drive signal TCLK may be a rising edge. And so on.

[0122] In practical implementation, following the order from low to high, the 2 high-weight current steering units 300 can be sequentially configured. N-M The -1 high-weight current sources 311 are respectively represented as the first high-weight current source 311, the second high-weight current source 311, ..., the i-th high-weight current source 311, ... and the 2nd high-weight current source 311. N-M -1 High-weighted current source 311.

[0123] Accordingly, following the order from least significant bit to most significant bit, we can sequentially assign the bits that are respectively related to 2. N-M -1 high-weighted current source 311 corresponds to 2 N-M The -1 high-weight current source switches 312 are respectively represented as the first high-weight current source switch 312, the second high-weight current source switch 312, ..., the i-th high-weight current source switch 312, ... and the 2nd high-weight current source switch 312. N-M -1 High-weight current source switch 312.

[0124] When the first toggling edge of the drive signal TCLK arrives, the first stage flip-flop 210 outputs the first high-weighted switching signal QT. <1> =1, the first high-weight current source switch 312 receives the first high-weight switch signal QT. <1> =1, and based on the first received high-weighted switching signal QT <1> =1, which turns on the first high-level weighted current source 311 until the high-level signal of the reset signal RST ends.

[0125] When the second toggling edge of the drive signal TCLK arrives, the second stage flip-flop 210 outputs the second high-weighted switching signal QT. <2> =1, the second high-weight current source switch 312 receives the second high-weight switch signal QT. <2> =1, and based on the received second high-weighted switching signal QT <2> =1, which turns on the second high-level weighted current source 311 until the high-level signal of the reset signal RST ends.

[0126] Similarly, when the i-th toggling edge of the drive signal TCLK arrives, the i-th stage flip-flop 210 outputs the i-th high-order weighted switching signal QT. =1, the i-th high-weight current source switch 312 receives the i-th high-weight switch signal QT. =1, and based on the received i-th high-order weighted switching signal QT =1, which turns on the i-th high-order weighted current source 311 until the high-level signal of the reset signal RST ends.

[0127] Until the second time of the drive signal TCLK N-M When the -1st flip edge arrives, the 2nd N-M -1 level trigger 210 output 2nd N-M -1 high-weighted switching signal QT<2 N-M -1>=1, 2nd N-M -1 High-weight current source switch 312 receives the 2nd... N-M -1 high-weighted switching signal QT<2 N-M -1>=1, and based on the received second... N-M -1 high-weighted switching signal QT<2 N-M -1>=1 and thus the 2nd N-M -1 The high-weighted current source 311 is turned on until the high-level signal of the reset signal RST ends.

[0128] In some embodiments, the toggle period of the drive signal TCLK can be twice the clock signal of the ramp signal generation circuit 10. M times.

[0129] Therefore, it can be seen that the 2 in the high-weight current rudder unit 300 N-M -1 high-weighted current source 311 can be turned on sequentially from low to high. And as mentioned earlier, 2 of the high-weighted current rudder units 300... N-M The current weights of the -1 high-weight current sources 311 are the same. Therefore, the high-weight current rudder unit 300 can output an increasing current as a rising ramp signal.

[0130] In other embodiments, the 2 in the high-weighted current steering unit 300 N-M -1 The high-weight current source 311 can also be disconnected sequentially from low to high. For example, in the initial state, 2 of the high-weight current rudder units 300 can be disconnected sequentially. N-M With all one high-weighted current source 311 turned on, and ground level used as the input to the first stage flip-flop 210 in the cascaded level flip-flop 200, and all flip-flops 210 in the cascaded level flip-flop 200 being active high-level, the first high-weighted switching signal QT is output sequentially by each flip-flop 210 in the cascaded level flip-flop 200 in chronological order. <1> The second high-level weighting switch signal QT <2> ...the i-th high-order weighting switch signal QT =1...and the 2nd N-M -1 high-weighted switching signal QT<2 N-M -1> can all be 0. Therefore, the 2 in the high-weight current steering unit 300 can be... N-M -1 high-weighted current source 311 can be disconnected sequentially from low to high. Correspondingly, the high-weighted current rudder unit 300 can output a decreasing current as a descending ramp signal.

[0131] In this embodiment of the invention, the ramp signal generation circuit 10 can generate a ramp signal based on the high-weight current steering unit 300. In this case, the master clock signal MCLK is used as the drive signal TCLK.

[0132] In this embodiment of the invention, the ramp signal generation circuit 10 can also combine the high-weight current steering unit 300 and the low-weight current steering unit 500 to generate a ramp signal. In this case, the master clock signal MCLK is divided by 0 to 2. M-1 The frequency-divided signal obtained by frequency division is used as the low-weight switching signal, and is used to perform 2-step switching on the master clock signal MCLK. M-1 Frequency division or 2 M-2 The frequency-divided signal obtained by frequency division is used as the driving signal TCLK.

[0133] When the ramp signal generation circuit 10 generates a ramp signal by combining the high-weight current rudder unit 300 and the low-weight current rudder unit 500, the ramp signal generation circuit 10 can function as a segmented current rudder type digital-to-analog converter. Specifically, the high-weight current rudder unit 300 serves as the temperature code unit of the segmented current rudder type digital-to-analog converter, and the low-weight current rudder unit 500 serves as the binary code unit of the segmented current rudder type digital-to-analog converter.

[0134] In this embodiment of the invention, the ramp signal generation circuit 10 can also determine how to generate the ramp signal based on the control signal.

[0135] In practice, the control signal may include a first control signal and a second control signal.

[0136] Specifically, the first control signal can be a high-level signal 1, and the second control signal can be a low-level signal 0.

[0137] In some embodiments, the high-weight encoder 100 is adapted to receive a control signal and, when the control signal is a first control signal, divide the main clock signal MCLK (i.e., divide the main clock signal MCLK by 2). M-1 Frequency division or 2 M-2 The high-order frequency division signal is generated by frequency division. The cascaded level trigger 200 uses this high-order frequency division signal as the drive signal TCLK to generate at least two high-order weighted switching signals. The high-order weighted current steering unit 300 generates a first ramp signal based on the at least two high-order weighted switching signals.

[0138] Accordingly, the input signal received by the low-weight encoder 400 may include a control signal. Furthermore, the low-weight encoder 400 is adapted to perform at least two frequency divisions on the master clock signal MCLK when the control signal is the first control signal (i.e., perform 2-fold frequency division on the master clock signal MCLK). m-1 Frequency division (m takes values ​​from 1 to M) generates at least two low-order frequency division signals. The low-order weighted current steering unit 500 generates a second ramp signal based on at least two low-order weighted switching signals.

[0139] In this case, the ramp signal generation circuit 10 can use the signal obtained by adding the first ramp signal and the second ramp signal as the output ramp signal.

[0140] In practice, both the first and second ramp signals are either rising ramp signals or both are falling ramp signals.

[0141] In other embodiments, the high-weight encoder 100 is adapted to receive a control signal and, when the control signal is a second control signal, use the master clock signal MCLK as the drive signal TCLK. The cascaded level trigger 200 generates at least two high-weight switching signals using the master clock signal MCLK as the drive signal TCLK. The high-weight current steering unit 300 generates a third ramp signal based on the at least two high-weight switching signals.

[0142] Accordingly, the input signal received by the low-weight encoder 400 may include a control signal. Furthermore, the low-weight encoder 400 is adapted to ensure that all low-weight switch signals are off when the control signal is a second control signal. The low-weight current steering unit 500 does not output current based on the off signal.

[0143] In this case, the ramp signal generation circuit 10 uses only the third ramp signal as the output ramp signal.

[0144] Continue to refer to Figure 1 In some embodiments, the ramp signal generation circuit 10 further includes a load resistor R.

[0145] When the increasing or decreasing current generated by the ramp signal generation circuit 10 flows through the load resistor R, the ramp signal generation circuit 10 can generate an increasing or decreasing voltage as a rising or falling ramp voltage signal and output it.

[0146] Figure 5 This is a schematic diagram of the ramp signal generated by the ramp signal generation circuit in an embodiment of the present invention.

[0147] Reference Figure 5 For the waveform of the ramp voltage signal vramp output by the ramp signal generation circuit 10, its slope is greater when the control signal is the second control signal (i.e., state = 0) than when the control signal is the first control signal (i.e., state = 1).

[0148] Therefore, it can be seen that the time for the ramp signal generation circuit 10 to output the ramp signal when the control signal is the second control signal (i.e., state = 0) is greatly shortened. This is because the frequency of the drive signal TCLK of the cascaded level trigger 200 when the control signal is the second control signal (i.e., state = 0) is twice the frequency of the drive signal TCLK when the control signal is the first control signal (i.e., state = 1). M-1 Or 2 M-2 The cascaded level trigger 200, when the control signal is the first control signal (i.e., state = 1), generates a drive signal TCLK by dividing the main clock signal MCLK by 2. M-1 Frequency division or 2 M-2 The high-order frequency divider signal of the cascaded level trigger 200, when the control signal is the second control signal (i.e., state = 0), drives the main clock signal TCLK.

[0149] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the invention, even when only a single embodiment is described with respect to a particular feature. The feature examples provided in this disclosure are intended to be illustrative and not limiting, unless otherwise stated. In practice, one or more technical features of the dependent claims may be combined with the technical features of the independent claims as needed and where technically feasible, and the technical features from the respective independent claims may be combined in any suitable manner rather than solely by the specific combinations listed in the claims.

[0150] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A ramp signal generation circuit, characterized in that, include: A high-weight encoder, adapted to receive a master clock signal and generate a drive signal based on the master clock signal; A cascaded level trigger is adapted to receive the drive signal and generate at least two high-weighted switching signals under the drive signal and its inverted signal. A high-weight current rudder unit includes at least two high-weight current rudders connected in parallel in sequence. Each of the high-weight current rudders is adapted to receive one of the at least two high-weight switching signals in sequence, and to turn on or off based on the received high-weight switching signal, so that the high-weight current rudder unit outputs an increasing or decreasing current to generate a ramp signal. A low-weight encoder is adapted to receive an input signal and generate M low-weight switching signals based on the input signal, where M is a positive integer greater than or equal to 1; A low-weight current rudder unit connected in parallel with the high-weight current rudder unit and located at a lower position than the high-weight current rudder unit; wherein, the low-weight current rudder unit includes M low-weight current rudders, the M low-weight current rudders being adapted to receive one of the M low-weight switch signals respectively, and to turn on or off based on the received low-weight switch signal. The input signal includes the master clock signal; the low-weight encoder is adapted to divide the master clock signal M times to generate M low-weight frequency division signals as the M low-weight switching signals; the M low-weight current rudders are adapted to receive one of the M low-weight frequency division signals respectively, and to turn on or off based on the received low-weight frequency division signal, so that the low-weight current rudder unit outputs an increasing or decreasing current to generate a ramp signal.

2. The ramp signal generation circuit according to claim 1, characterized in that, The high-weight encoder is adapted to use the master clock signal as the drive signal.

3. The ramp signal generation circuit according to claim 1, characterized in that, The ramp signal generation circuit has an accuracy of N bits, and the high-weight current steering unit includes 2 N-M -1 high-weighted current rudder, the 2 N-M -1 The current weight of each high-weight current rudder is 2. M Where N is a positive integer greater than M.

4. The ramp signal generation circuit according to claim 1, characterized in that, M is greater than or equal to 2, and the current weights of the M low-weight current rudders increase sequentially from the least significant bit to the most significant bit in a binary weighted manner. The current weight of the lowest-weight current rudder among the M low-weight current rudders is 2. 0 .

5. The ramp signal generation circuit according to claim 1, characterized in that, The low-weight encoder includes 2 m -1 Frequency divider, the 2 m-1 The frequency divider is adapted to divide the master clock signal to generate the M low-order frequency divider signals, wherein m takes values ​​from 1 to M.

6. The ramp signal generation circuit according to claim 5, characterized in that, The high-weight encoder includes 2 M -1 Frequency divider or 2 M-2 Frequency divider, the 2 M-1 Frequency divider or the 2 M-2 The frequency divider is adapted to divide the master clock signal to generate a high-order frequency-divided signal as the driving signal.

7. The ramp signal generation circuit according to claim 6, characterized in that, The high-weight encoder is adapted to receive a control signal and, when the control signal is a first control signal, divide the master clock signal to generate the high-weight divider signal; the input signal includes the control signal; the low-weight encoder is adapted to divide the master clock signal M times when the control signal is the first control signal to generate the M low-weight divider signals.

8. The ramp signal generation circuit according to claim 3 or 4, characterized in that, The high-weight encoder is adapted to receive a control signal and, when the control signal is a second control signal, use the master clock signal as the drive signal; the input signal includes the control signal; the low-weight encoder is adapted to make all M low-weight switch signals turn off when the control signal is the second control signal; the M low-weight current rudders are adapted to receive the turn-off signal respectively and, based on the turn-off signal, all turn off so that the low-weight current rudder unit does not output current.

9. The ramp signal generation circuit according to claim 1, characterized in that, The cascaded level trigger includes at least two cascaded triggers to output the at least two high-weight switch signals respectively, and each trigger is adapted to output one of the at least two high-weight switch signals.

10. The ramp signal generation circuit according to claim 9, characterized in that, One of two adjacent flip-flops uses the drive signal as its clock signal, and the other uses the inverted signal of the drive signal as its clock signal.

11. The ramp signal generation circuit according to claim 10, characterized in that, The cascaded level trigger includes an inverter adapted to receive the drive signal and invert it into the inverted signal for output to the other.

12. The ramp signal generation circuit according to any one of claims 9 to 11, characterized in that, The trigger located in the first stage takes either a power supply level or a ground level as input.

13. The ramp signal generation circuit according to claim 12, characterized in that, Each of the subsequent triggers takes the output of the trigger in the preceding stage as its input.

14. The ramp signal generation circuit according to claim 13, characterized in that, The triggers include D triggers.

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