Comparator

Abstract

The present application provides a comparator, which includes a first-stage circuit connected to a power supply terminal and a ground terminal, and is provided with a first pair of tubes and a second pair of tubes. The first pair of tubes and the second pair of tubes are of different types. The first pair of tubes and the second pair of tubes are used to receive an input signal and a reference signal, and generate a differential signal based on the input signal and the reference signal during a sampling phase. A positive feedback circuit is connected to the output terminal of the first-stage circuit and is used to accelerate the difference between the differential signals. A second-stage circuit is connected to the power supply terminal and the ground terminal and is connected to the output terminal of the first-stage circuit and is used to amplify and latch the voltage signal at the output terminal of the first-stage circuit during a regeneration phase to output a comparison result. The comparator provided by this solution has a high response rate, low power consumption, and low operating voltage.

Description

Technical Field

[0001] The present application relates to an integrated circuit, and in particular to a comparator. Background Art

[0002] Nowadays, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which has greatly enriched our daily life and work.

[0003] However, limited battery life places higher demands on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, and therefore, DRAM urgently needs to achieve lower operating voltages and lower energy consumption. Among them, comparators are key components for reading and writing DRAM data, and existing comparators no longer meet current usage requirements. Summary of the Invention

[0004] The present application provides a comparator, which aims to improve the response rate of the comparator and reduce the power consumption and operating voltage of the comparator.

[0005] In a first aspect, the present application provides a comparator, comprising:

[0006] The first stage circuit is connected to the power supply terminal and the ground terminal, and is provided with a first pair of transistors and a second pair of transistors. The first pair of transistors and the second pair of transistors are of different types. The first pair of transistors and the second pair of transistors are used to receive an input signal and a reference signal, and generate a differential signal according to the input signal and the reference signal during a sampling phase;

[0007] a positive feedback circuit connected to the output terminal of the first stage circuit and configured to accelerate the difference between the differential signals;

[0008] The second stage circuit is connected to the power supply terminal and the ground terminal and is connected to the output terminal of the first stage circuit. It is used to amplify and latch the voltage signal of the output terminal of the first stage circuit in the regeneration stage to output a comparison result.

[0009] In a second aspect, the present application provides a comparator, comprising:

[0010] A first-stage circuit having an output terminal for generating a differential signal according to an input signal and a reference signal during a sampling phase;

[0011] a positive feedback circuit connected to the output terminal of the first stage circuit and configured to accelerate the difference between the differential signals;

[0012] The second stage circuit is connected to the output end of the first stage circuit and is used to amplify and latch the voltage signal of the output end of the first stage circuit in the regeneration stage to output a comparison result.

[0013] The present application provides a comparator comprising a first-stage circuit, a positive feedback circuit, and a second-stage circuit. The first-stage circuit comprises a first pair of transistors and a second pair of transistors, each of which receives an input signal and a reference signal. The first and second pairs of transistors are further configured to generate a differential signal based on the input signal and the reference signal during a sampling phase. The positive feedback circuit accelerates the difference between the differential signals. The second-stage circuit amplifies and latches the voltage signal at the output of the input circuit during a regeneration phase to output a comparison result. Because the first and second pairs of transistors are of different types, i.e., their voltage-pulling capabilities are opposite, when the input signal and the reference signal cause the voltage-pulling capabilities of the first and second pairs of transistors to be unbalanced, the two pairs of transistors can accurately sense even a very small difference between the input signal and the reference signal, thereby improving the sensing accuracy of the comparator. Furthermore, the positive feedback circuit accelerates the difference between the differential signals, shortening the sampling phase of the comparator, thereby improving the response efficiency of the comparator and reducing its power consumption. Because the first-stage circuit contains two sets of different transistor pairs, both pairs receive the input signal and the reference signal. This allows for a wide range of reference signal options, for example, ranging from 0.3V to 0.9V. This allows for the generation of differential signals between the two pairs, expanding the comparator's operating range. This two-stage circuit setup, with the first stage generating the differential signal and the second stage generating the comparison result based on the differential signal, reduces the number of transistors in the same circuit path, thereby reducing the comparator's operating voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0015] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0016] Figure 2 The working timing diagram of the comparator provided in this application;

[0017] Figure 3 A structural block diagram of a comparator provided in this application;

[0018] Figure 4 Based on Figure 3 A specific circuit diagram of the provided comparator;

[0019] Figure 5 Based on Figure 3 Another specific circuit diagram of the provided comparator;

[0020] Figure 6A structural block diagram of a comparator provided in this application;

[0021] Figure 7 Based on Figure 6 A specific circuit diagram of the provided comparator;

[0022] Figure 8 Based on Figure 7 The specific circuit diagram of the positive feedback circuit in the provided comparator;

[0023] Figure 9 Based on Figure 6 A specific circuit diagram of the provided comparator;

[0024] Figure 10 Based on Figure 9 The specific circuit diagram of the positive feedback circuit in the provided comparator;

[0025] Figure 11 A specific circuit diagram of a comparator provided in this application;

[0026] Figure 12 Based on Figure 11 The specific circuit diagram of the positive feedback circuit in the provided comparator;

[0027] Figure 13 A specific circuit diagram of a comparator provided in this application;

[0028] Figure 14 Based on Figure 13 The specific circuit diagram of the positive feedback circuit in the provided comparator.

[0029] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0030] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0031] like Figure 1As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output end of the input circuit 101 is connected to the input end of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0032] The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3. The transistor N1 and the transistor N2 constitute a differential transistor pair. The gate of the transistor N1 and the gate of the transistor N2 constitute a first input terminal IP and a second input terminal IN of the input circuit. The drain of the transistor N1 and the drain of the transistor N2 constitute two output terminals of the input circuit.

[0033] Output circuit 102 includes transistors P1, P2, N4, and N5. These four transistors form a cross-coupled transistor pair. The drains of transistors P1 and N4 form a first output terminal ON of output circuit 102, and the drains of transistors P2 and N5 form a second output terminal OP of output circuit 102. Reset circuit 103 includes transistors P3 and P4.

[0034] The working process of the comparator is divided into four stages: reset stage, sampling stage, regeneration stage and decision stage. Figure 2 describe Figure 1 The working process of the comparator shown is:

[0035] In the reset phase, that is, from time t0 to time t1, the clock signal is at a low level, transistor N3 is disconnected, the input circuit and the output circuit stop working, transistor P3 and transistor P4 are closed, and the reset circuit works, pulling the drain voltage of transistor N4 and the drain voltage of transistor N5 to a high level.

[0036] During the sampling phase, from time t1 to time t2, the clock signal is high, transistors P3 and P4 are disconnected, and the reset circuit stops operating. Transistor N3 is closed, and the input circuit collects the input signal through the first input terminal IP. The input circuit collects the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the input signal pulls up the drain voltage of transistor N1 at a faster rate, causing the drain voltage of transistor N4 to be lower than the drain voltage of transistor N5.

[0037] In the regeneration stage, that is, from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the flip voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually disconnected, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N5.

[0038] During the decision phase, that is, from time t3 to time t4, transistor P2 and transistor N4 are turned on, and transistor P1 and transistor N5 are turned off, continuing to pull up the drain voltage of transistor N5 and continuing to pull down the drain voltage of transistor N4. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0039] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the transistors N4 and N5 are reset to a high level by the transistors P1 and P2.

[0040] However, when the reference signal is not properly selected, the time it takes for the input signal and the reference signal to generate a differential signal at the output of the input circuit is relatively long, which reduces the response rate of the comparator and increases the power consumption of the comparator. Figure 2 In the comparator shown, when the reference signal is relatively small, transistors N1 and N2 need to be turned on for a longer time, causing the charging currents of nodes VP and VN to decrease. Transistors N1 and N2 pull transistors N5 and N4 to decrease in speed, resulting in a decrease in the response speed of the comparator and an increase in the power consumption of the comparator.

[0041] like Figure 3 As shown, an embodiment of the present application provides a comparator, which includes a first-stage circuit 201, a second-stage circuit 203, and a positive feedback circuit 203. The first-stage circuit 201 has an output terminal, and the second-stage circuit 203 and the positive feedback circuit 203 are both connected to the output terminal of the first-stage circuit 201.

[0042] The first-stage circuit 201 is connected to the power supply and ground, so that the transistors in the first-stage circuit 201 form one current path. The second-stage circuit 203 is connected to the power supply and ground, so that the transistors in the second-stage circuit 203 form another current path. Compared to a comparator structure that only includes one stage of circuitry, this arrangement can reduce the number of transistors in each current path, thereby lowering the comparator's operating voltage.

[0043] The first-stage circuit 201 includes a first pair of transistors and a second pair of transistors, which are used to receive an input signal and a reference signal. Specifically, the first transistor in the first pair of transistors is used to receive the input signal, and the second transistor in the first pair of transistors is used to receive the reference signal. The first transistor in the second pair of transistors is used to receive the input signal, and the second transistor in the second pair of transistors is used to receive the reference signal. The first and second pairs of transistors are also used to generate a differential signal based on the input signal and the reference signal during the sampling phase.

[0044] Because the first and second pairs of transistors use different transistor types, they pull voltage in different directions. The input signal and reference signal are used to control the voltage pulling capabilities of the first and second pairs of transistors. If the input signal and reference signal cause an imbalance in the voltage pulling capabilities of the first and second pairs of transistors, a differential signal can be generated between the first and second pairs of transistors, even if the difference between the input signal and the reference signal is very small, thereby improving the accuracy of the comparator.

[0045] For example, a first pair of transistors includes a first input transistor P1 and a second input transistor P2, and a second pair of transistors includes a third input transistor N1 and a fourth input transistor N2. A reference signal balances the voltage-pulling capability of the second input transistor P2 with the voltage-pulling capability of the fourth input transistor N2. When the input signal is slightly greater than the reference signal, the input signal causes an imbalance between the voltage-pulling capability of the first input transistor P1 and the voltage-pulling capability of the third input transistor N1, resulting in a differential signal across the first and second pairs of transistors.

[0046] When the input signal and the reference signal generate differential signals across the two pairs of transistors, positive feedback circuit 203 is used to accelerate the difference between the differential signals. First-stage circuit 201 is also used to output the accelerated differential signal. Second-stage circuit 202 is used to amplify and latch the voltage signal at the output of first-stage circuit 201 during the regeneration phase.

[0047] It should also be noted that since the first pair of tubes and the second pair of tubes of different types are used to receive the input signal and the reference signal, the value of the reference signal can vary from 0.3V to 0.9V, and differential signals can be generated on the first pair of tubes and the second pair of tubes, thereby expanding the selection range of the reference voltage of the comparator.

[0048] Because first-stage circuit 201 uses two pairs of transistors to receive input signals and reference signals, and the two pairs of transistors have different voltage-pulling capabilities, it takes a long time for first-stage circuit 201 to present a relatively large differential signal at its output. This increases the response time of first-stage circuit 201. Positive feedback circuit 203 accelerates the difference between the differential signals through a positive feedback mechanism, thereby shortening the time that first-stage circuit 201 presents a relatively large differential signal at its output. This shortens the time the comparator spends in the sampling phase, thereby improving the comparator's response speed and reducing its power consumption.

[0049] In one embodiment, the first-stage circuit 201 and the second-stage circuit 202 have the same number of transistors in their respective current paths, so that the operating voltages of the first-stage circuit 201 and the second-stage circuit 202 are the same, reducing the number of power supply terminals required by the comparator and simplifying the circuit of the comparator.

[0050] In one embodiment, the positive feedback circuit 203 includes a first positive feedback module and a second positive feedback module. Both the first and second positive feedback modules are connected to the output terminal of the first-stage circuit. The first and second feedback modules are configured to pull the voltage at the output terminal of the first-stage circuit to accelerate the difference between the differential signals. The direction in which the first feedback module pulls the voltage at the output terminal of the first-stage circuit is different from the direction in which the second feedback module pulls the voltage at the output terminal of the first-stage circuit. By using two feedback modules with opposite pulling directions to pull the difference of the differential signals, the amplitude of the larger voltage signal in the differential signal can be increased, while the amplitude of the smaller voltage signal in the differential signal can be decreased, further accelerating the difference of the differential signals.

[0051] In one embodiment, the first stage circuit has two output terminals, which are labeled as a first output terminal and a second output terminal. The first feedback module includes a first feedback unit 2031 and a second feedback unit 2032, each of which has a control terminal and a first terminal.

[0052] The control end of the first feedback unit 2031 is connected to the first output end of the first stage circuit, and the first end of the first feedback unit 2031 is connected to the second output end of the first stage circuit to pull the voltage of the second output end of the first stage circuit according to the voltage of the first output end of the first stage circuit.

[0053] The control end of the second feedback unit 2032 is connected to the second output end of the first-stage circuit, and the first end of the second feedback unit 2032 is connected to the first output end of the first-stage circuit to pull the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit.

[0054] The first feedback unit 2031 and the second feedback unit 2032 have the same pulling direction for voltage. If both pull upward, the larger the voltage at the control terminal of the first feedback unit, the weaker the upward pulling ability. If both pull downward, the larger the voltage at the control terminal of the first feedback unit, the stronger the downward pulling ability.

[0055] Taking the first feedback unit 2031 and the second feedback unit 2032 pulling the voltage upward as an example, when the voltage at the first output terminal of the first-stage circuit is greater than the voltage at the second output terminal of the first-stage circuit, the ability of the first feedback unit 2031 to pull the voltage at the second output terminal upward is less than the ability of the second feedback unit 2032 to pull the voltage at the first output terminal upward, so that the difference between the voltage at the first output terminal and the voltage at the second output terminal of the first-stage circuit becomes larger and larger, realizing positive feedback.

[0056] In one embodiment, the second feedback module includes a third feedback unit 2033 and a fourth feedback unit 2034 , and both the third feedback unit 2033 and the fourth feedback unit 2034 are provided with a control end and a first end.

[0057] The control end of the third feedback unit 2033 is connected to the first output end of the first-stage circuit, and the first end of the third feedback unit 2033 is connected to the second output end of the first-stage circuit. The third feedback unit 2033 is used to pull down the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit.

[0058] The control end of the fourth feedback unit 2034 is connected to the second output end of the first-stage circuit, and the first end of the fourth feedback unit 2034 is connected to the first output end of the first-stage circuit. The fourth feedback unit 2034 is used to pull down the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit.

[0059] The direction and capability of the voltage pulling of the third feedback unit 2033 and the fourth feedback unit 2034 are the same as those of the first feedback unit 2031 and the second feedback unit 2032 , and are not described again here.

[0060] Taking the example where both the third feedback unit 2033 and the fourth feedback unit 2034 pull the voltage downward, through the above setting, when the voltage at the first output terminal of the first-stage circuit is greater than the voltage at the second output terminal of the first-stage circuit, the ability of the fourth feedback unit 2034 to pull the voltage at the second output terminal downward is greater than the ability of the second feedback unit 2032 to pull the voltage at the first output terminal upward, so that the difference between the voltage at the first output terminal and the voltage at the second output terminal of the first-stage circuit becomes larger and larger, thereby realizing positive feedback.

[0061] In the above technical solution, the first feedback unit 2031 and the second feedback unit 2032 are used to jointly control the two output ends of the first-stage circuit, and the third feedback unit 2033 and the fourth feedback unit 2034 are used to jointly control the two output ends of the first-stage circuit, thereby realizing a positive feedback mechanism, accelerating the difference of the differential signal at the first-stage output end, shortening the time that the comparator is in the sampling stage, thereby improving the response rate of the comparison and reducing the power consumption of the comparator.

[0062] like Figure 4 As shown, an embodiment of the present application provides a specific circuit of a comparator, which includes a first-stage circuit, a second-stage circuit, and a positive feedback circuit.

[0063] The first stage circuit includes a first input transistor P1 and a second input transistor P2, which form a first pair of transistors.

[0064] The control end of the first input transistor P1 is used to receive the input signal In, the first end of the first input transistor P1 is connected to the power supply end, and the second end of the first input transistor P1 serves as the first output end of the first stage circuit.

[0065] The control end of the second input transistor P2 is used to receive the reference signal Vr, the first end of the second input transistor P2 is connected to the power supply end, and the second end of the second input transistor P2 serves as the second output end of the first stage circuit.

[0066] The first stage circuit further includes a third input transistor N1, a fourth input transistor N2 and a fifth input transistor N3. The second input transistor N1 and the second input transistor N2 form a second pair of transistors.

[0067] The control end of the third input transistor N1 is used to receive an input signal. The first end of the third input transistor N1 is connected to the second end of the first input transistor P1 to form a first output end of the first stage circuit.

[0068] The control end of the fourth input transistor N2 is used to receive a reference signal. The first end of the fourth input transistor N2 is connected to the second end of the second input transistor P2 to form the second output end of the first stage circuit.

[0069] The control end of the fifth input transistor N3 is used to receive the clock signal. The first end of the fifth input transistor N3 is connected to the second end of the third input transistor N1 and the second end of the fourth input transistor N2. The second end of the fifth input transistor N3 is connected to the ground end.

[0070] The fifth input transistor N3 controls the operating state of the first-stage circuit. During the reset phase, the fifth input transistor N3 is disconnected, halting operation of the first-stage circuit. The first-stage circuit operates during the sampling, regeneration, and decision phases. During the sampling phase, the first, second, third, and fourth input transistors P1, P2, N1, and N2 generate a differential signal under the control of the input signal and the reference signal.

[0071] The second stage circuit includes a first output transistor N4, a second output transistor N5, a third output transistor N6, a fourth output transistor N7, a fifth output transistor P5, a sixth output transistor P6 and a seventh output transistor P7.

[0072] The control terminal of the first output transistor N4 is the first input terminal of the second stage circuit and is connected to the second terminal of the first input transistor P1 in the first stage circuit. The first terminal of the first output transistor N4 is the first output terminal of the second stage circuit. The second terminal of the first output transistor N4 is connected to the ground terminal.

[0073] The control terminal of the second output transistor N5 is the second input terminal of the second stage circuit and is connected to the second terminal of the second input transistor P2 in the first stage circuit. The first terminal of the second output transistor N5 is the first output terminal of the second stage circuit. The second terminal of the second output transistor N5 is connected to the ground terminal.

[0074] A first end of the third output transistor N6 is connected to the first end of the first output transistor N4 , and a second end of the third output transistor N6 is connected to the second end of the first output transistor N4 .

[0075] A first end of the fourth output transistor N7 is connected to the first end of the second output transistor N5 , and a second end of the fourth output transistor N7 is connected to the second end of the second output transistor N5 .

[0076] The second end of the fifth output transistor P5 is connected to the first end of the third output transistor N6 . The control end of the fifth output transistor P5 is connected to the control end of the third output transistor N6 and then to the first end of the fourth output transistor N7 .

[0077] The second end of the sixth output transistor P6 is connected to the first end of the fourth output transistor N7 . The control end of the sixth output transistor P6 is connected to the control end of the fourth output transistor N7 , and then connected to the first end of the third output transistor.

[0078] The control end of the seventh output transistor P7 is used to receive a clock signal. The first end of the seventh output transistor P7 is connected to the power end. The second end of the seventh output transistor P7 is connected to the first end of the fifth output transistor and the first end of the sixth output transistor.

[0079] The seventh output transistor P7 is used to control the working state of the second stage circuit. In the reset phase, the seventh output transistor P7 is turned off and the second stage circuit stops working. In the sampling phase, the regeneration phase and the decision phase, the seventh output transistor P7 is working.

[0080] In the regeneration stage and the decision stage, the first output transistor N4 and the second output transistor N5 are used to amplify the differential signal of the first-stage circuit, and the third output transistor N6, the fourth output transistor N7, the fifth output transistor P5 and the sixth output transistor P6 constitute a latch, which is used to amplify and latch the signals at the first ends of the first output transistor N4 and the second output transistor N5 to output the comparison result.

[0081] The first-stage circuit is connected to the ground terminal via the fifth input transistor N3 and to the power supply terminal via the first input transistor P1 and the second input transistor P2. Each current path in the first-stage circuit includes three transistors, for example, the current path formed by the first input transistor P1, the third input transistor N1, and the fifth input transistor N3.

[0082] The second-stage circuit is connected to the ground terminal through any one of the first output transistor N4 to the fourth output transistor N7. The second-stage circuit is also connected to the power supply terminal through the seventh output transistor P7. Each current path in the second-stage circuit includes three transistors, for example, the current path formed by the first output transistor N4, the fifth input transistor P5, and the seventh input transistor P7.

[0083] The comparator adopts the structure of the first-stage circuit and the second-stage circuit, and has a lower operating voltage and a wider range of applications compared to the comparator adopting the first-stage structure.

[0084] In one embodiment, the first feedback unit includes a first feedback transistor P8 , a control terminal of the first feedback transistor P8 connected to the second terminal of the first input transistor P1 , and a second terminal of the first feedback transistor P8 connected to the second terminal of the second input transistor P2 .

[0085] The second feedback unit includes a second feedback transistor P9 , a control end of the second feedback transistor P9 is connected to the second end of the second input transistor P2 , and a second end of the second feedback transistor P9 is connected to the second end of the first input transistor P1 .

[0086] The third feedback unit includes a third feedback transistor N8 , a control terminal of the third feedback transistor N8 is connected to the second terminal of the third input transistor N1 , and a first terminal of the third feedback transistor N8 is connected to the first terminal of the fourth input transistor N2 .

[0087] The fourth feedback unit includes a fourth feedback transistor N9 . The control terminal of the third feedback transistor N9 is connected to the first terminal of the fourth input transistor N2 . The first terminal of the third feedback transistor N9 is connected to the second terminal of the third input transistor N1 .

[0088] If the first feedback transistor P8 and the second feedback transistor P9 are P-type transistors, both feedback transistors pull up the voltage of the output terminal of the first-stage circuit, and the greater the control terminal voltage of the feedback transistor, the smaller the ability of the feedback transistor to pull down the voltage of the output terminal of the first-stage circuit.

[0089] If the third feedback transistor N8 and the fourth feedback transistor N9 are N-type transistors, both feedback transistors pull down the voltage of the output terminal of the first-stage circuit, and the greater the voltage of the control terminal of the feedback transistor, the greater the ability of the feedback transistor to pull down the voltage of the output terminal of the first-stage circuit.

[0090] In one embodiment, the first feedback transistor P8, the second feedback transistor P9, the first input transistor P1, and the second input transistor P2 are of the same type; the third feedback transistor N8, the fourth feedback transistor N9, the third input transistor N1, the fourth input transistor N2, and the fifth input transistor N3 are of the same type.

[0091] If the first feedback transistor P8, the second feedback transistor P9, the first input transistor P1 and the second input transistor P2 are all P-type transistors, the drain of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

[0092] If the third feedback transistor N8 , the fourth feedback transistor N9 , the third input transistor N1 , the fourth input transistor N2 and the fifth input transistor N3 are all N-type transistors, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0093] The second stage circuit includes the first output transistor N4, the second output transistor N5, the third output transistor N6, and the fourth output transistor N7 of the same type, and the fifth output transistor P5, the sixth output transistor P6, and the seventh output transistor P7 of the same type.

[0094] If the first output transistor N4 , the second output transistor N5 , the third output transistor N6 , and the fourth output transistor N7 are all N-type transistors, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0095] If the fifth output transistor P5 , the sixth output transistor P6 , and the seventh output transistor P7 are all P-type transistors, the drain of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

[0096] In one embodiment, the first feedback transistor P8 and the second feedback transistor P9 have the same size, the first input transistor P1 and the second input transistor P2 have the same size, and the size of the first feedback transistor P8 is less than half of the size of the first input transistor P1.

[0097] In one embodiment, the third feedback transistor N8 and the fourth feedback transistor N9 have the same size, the third input transistor N1 and the fourth input transistor N2 have the same size, and the size of the third feedback transistor N8 is less than half of the size of the fifth input transistor N1.

[0098] The above-mentioned size setting can prevent the feedback transistor from having an excessively strong voltage pulling capability, thereby preventing the input transistor from sensing the input signal and the reference signal. This improves the response rate of the comparator while also ensuring the accuracy of the comparator output result.

[0099] Table 1 below illustrates that the comparator can implement rail-to-rail detection, that is, the reference voltage has a wide range of variation. For example, taking the power supply voltage VDD as 1.2V, the reference signal can range from 0.3V to 0.9V.

[0100] Table 1 Working principle of the sampling phase of the comparator

[0101]

[0102]

[0103] In the third case, the first input transistor P1, the second input transistor P2 and the third input transistor N1 are all turned on. The pull-up capability of the first input transistor P1 is smaller than that of the second input transistor P2, and the third input transistor N1 also pulls down the voltage of the first input transistor P1, so VP1<VP2.

[0104] In the sixth case, the first input transistor P1, the second input transistor P2, the third input transistor N1, and the fourth input transistor N2 are all turned on. The pull-up capability of the first input transistor P1 is greater than that of the second input transistor P2, and the ability of the third input transistor N1 to pull down the voltage of the first input transistor P1 is less than the ability of the fourth input transistor N2 to pull down the voltage of the second input transistor P2, so VP1>VP2.

[0105] For analysis of other situations, please refer to the analysis of situations 3 and 6, which will not be repeated here.

[0106] That is, when the reference voltage changes from 0V to 0.9V, a differential signal can be generated on the first input transistor P1 and the second input transistor P2. The first feedback transistor P8, the second feedback transistor P9, the third feedback transistor N8 and the fourth feedback transistor N9 accelerate the difference of the differential signal through a positive feedback mechanism, thereby shortening the sampling time.

[0107] In one embodiment, the comparator further includes a reset circuit for resetting the voltage at the output terminal of the first-stage circuit. More specifically, the reset circuit includes a first reset transistor P3 and a second reset transistor P4, wherein the second terminal of the first reset transistor P3 is connected to the second terminal of the first input transistor P1, and the second terminal of the second reset transistor P4 is connected to the second terminal of the second input transistor P2.

[0108] The first reset transistor P3 and the second reset transistor P4 are of the same transistor type as the first input transistor P1. When the first reset transistor P3 and the second reset transistor P4 are P-type transistors, the drain of the P-type transistor is the second terminal. During the reset phase, the first reset transistor P3 and the second reset transistor P4 are turned on, pulling the voltage of the first input transistor P1 and the second input transistor P2 to a high level.

[0109] like Figure 5 As shown, an embodiment of the present application provides a specific circuit of a comparator, which includes a first-stage circuit, a second-stage circuit, and a positive feedback circuit.

[0110] The first stage circuit includes a first input transistor N1 and a second input transistor N2, which form a first transistor pair.

[0111] The control end of the first input transistor N1 is used to receive the input signal In, the first end of the first input transistor N1 is connected to the ground end, and the second end of the first input transistor N1 serves as the first output end of the first stage circuit.

[0112] The control terminal of the second input transistor N2 is used to receive the reference signal Vr, the first terminal of the second input transistor N2 is connected to the ground, and the second terminal of the second input transistor N2 serves as the second output terminal of the first stage circuit.

[0113] The first stage circuit further includes a third input transistor P1, a fourth input transistor P2, and a fifth input transistor P3. The second input transistor P1 and the second input transistor P2 form a second pair of transistors.

[0114] The control end of the third input transistor P1 is used to receive the input signal In. The first end of the third input transistor P1 is connected to the second end of the first input transistor N1 to form the first output end of the first stage circuit.

[0115] The control end of the fourth input transistor P2 is used to receive the reference signal Vr. The first end of the fourth input transistor P2 is connected to the second end of the second input transistor N2 to form the second output end of the first stage circuit.

[0116] The control end of the fifth input transistor P3 is used to receive the clock signal CLKB, where CLKB represents the inverted clock signal. That is, the inverted clock signal is input to the fifth input transistor P3. The first end of the fifth input transistor P3 is connected to the second end of the third input transistor P1 and the second end of the fourth input transistor P2. The second end of the fifth input transistor P3 is connected to the power supply end.

[0117] The fifth input transistor P3 controls the operating state of the first-stage circuit. During the reset phase, the fifth input transistor P3 is disconnected, halting the first-stage circuit. The first-stage circuit operates during the sampling, regeneration, and decision phases. During the sampling phase, the first, second, third, and fourth input transistors N1, N2, P1, and P2 generate a differential signal under the control of the input signal and the reference signal.

[0118] The second stage circuit includes a first output transistor P4, a second output transistor P5, a third output transistor P6, a fourth output transistor P7, a fifth output transistor N5, a sixth output transistor N6 and a seventh output transistor N7.

[0119] The control terminal of the first output transistor P4 is the first input terminal of the second stage circuit and is connected to the second terminal of the first input transistor N1 in the first stage circuit. The first terminal of the first output transistor P4 is the first output terminal of the second stage circuit. The second terminal of the first output transistor P4 is connected to the power supply terminal.

[0120] The control terminal of the second output transistor P5 is the second input terminal of the second stage circuit and is connected to the second terminal of the second input transistor N2 in the first stage circuit. The first terminal of the second output transistor P5 is the first output terminal of the second stage circuit. The second terminal of the second output transistor P5 is connected to the power supply terminal.

[0121] A first end of the third output transistor P6 is connected to the first end of the first output transistor P4 , and a second end of the third output transistor P6 is connected to the second end of the first output transistor P4 .

[0122] A first end of the fourth output transistor P7 is connected to the first end of the second output transistor P5 , and a second end of the fourth output transistor P7 is connected to the second end of the second output transistor P5 .

[0123] The second end of the fifth output transistor N5 is connected to the first end of the third output transistor P6 . The control end of the fifth output transistor N5 is connected to the control end of the third output transistor P6 and then to the first end of the fourth output transistor P7 .

[0124] The second end of the sixth output transistor N6 is connected to the first end of the fourth output transistor P7 . The control end of the sixth output transistor N6 is connected to the control end of the fourth output transistor P7 and then to the first end of the third output transistor P6 .

[0125] The control end of the seventh output transistor N7 is used to receive the clock signal CLK. The first end of the seventh output transistor N7 is connected to the ground end. The second end of the seventh output transistor N7 is connected to the first end of the fifth output transistor N5 and the first end of the sixth output transistor N6.

[0126] The seventh output transistor N7 is used to control the working state of the second stage circuit. In the reset phase, the seventh output transistor N7 is turned off and the second stage circuit stops working. In the sampling phase, the regeneration phase and the decision phase, the seventh output transistor N7 is working.

[0127] The functions of the transistors in the second-stage circuit have been described in the above embodiments and will not be repeated here.

[0128] The current paths of the first-stage circuit and the second-stage circuit have been described in the above embodiments and will not be repeated here.

[0129] In one embodiment, the first feedback unit includes a first feedback transistor N8 , a control terminal of the first feedback transistor N8 connected to the second terminal of the first input transistor N1 , and a second terminal of the first feedback transistor N8 connected to the second terminal of the second input transistor N2 .

[0130] The second feedback unit includes a second feedback transistor N9 , a control terminal of the second feedback transistor N9 is connected to the second terminal of the second input transistor N2 , and a second terminal of the second feedback transistor N9 is connected to the second terminal of the first input transistor N1 .

[0131] The third feedback unit includes a third feedback transistor P8 , a control terminal of the third feedback transistor P8 is connected to the second terminal of the third input transistor P1 , and a first terminal of the third feedback transistor P8 is connected to the first terminal of the fourth input transistor P2 .

[0132] The fourth feedback unit includes a fourth feedback transistor P9 , a control terminal of the third feedback transistor P9 is connected to the first terminal of the fourth input transistor P2 , and a first terminal of the third feedback transistor P9 is connected to the second terminal of the third input transistor P1 .

[0133] In one embodiment, if the first feedback transistor N8 , the second feedback transistor N9 , the first input transistor N1 and the second input transistor N2 are all N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0134] If the third feedback transistor P8 , the fourth feedback transistor P9 , the third input transistor P1 , the fourth input transistor P2 , and the fifth input transistor P3 are all P-type transistors, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

[0135] In one embodiment, if the first output transistor P4 , the second output transistor P5 , the third output transistor P6 , and the fourth output transistor P7 are all P-type transistors, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

[0136] If the fifth output transistor N5 , the sixth output transistor N6 and the seventh output transistor N7 are all N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0137] In one embodiment, the comparator further includes a first reset transistor N3 and a second reset transistor N4. The second terminal of the first reset transistor N3 is connected to the second terminal of the first input transistor N1, and the second terminal of the second reset transistor N4 is connected to the second terminal of the second input transistor N2. When the first reset transistor N3 and the second reset transistor N4 are N-type transistors, the drain of the N-type transistor is the second terminal. During the reset phase, the first reset transistor N3 and the second reset transistor N4 are turned on, pulling the voltage of the first input transistor N1 and the second input transistor N2 to a low level.

[0138] Figure 6 A structural block diagram of a comparator provided in this application is shown in FIG. Figure 6 As shown, the comparator includes a first-stage circuit 201 , a second-stage circuit 202 and a positive feedback circuit 203 .

[0139] The first-stage circuit 201 has two output terminals, which are denoted as a first output terminal and a second output terminal. The positive feedback circuit 203 includes a first controllable feedback module 21 and a second controllable feedback module 22 .

[0140] The first controllable feedback module 21 includes at least one first controllable feedback submodule 23, wherein each first controllable feedback submodule 23 includes a first feedback unit 2031, a second feedback unit 2032, a first switch 1001, and a second switch 1002. The first feedback unit 2031 and the second feedback unit 2032 are each provided with a control terminal and a first terminal.

[0141] The control end of the first feedback unit 2031 is connected to the first output end of the first-stage circuit 201 via the first switch 1001, and the first end of the first feedback unit 2031 is connected to the second output end of the first-stage circuit 201. The control end of the second feedback unit 2032 is connected to the second output end of the first-stage circuit 201 via the second switch 1002, and the first end of the second feedback unit 2032 is connected to the first output end of the first-stage circuit 201.

[0142] The first feedback unit 2031 is configured to pull the voltage of the second output terminal of the first-stage circuit based on the voltage of the first output terminal of the first-stage circuit under the control of the first switch 1001. The second feedback unit 2032 is configured to pull the voltage of the first output terminal of the first-stage circuit based on the voltage of the second output terminal of the first-stage circuit under the control of the second switch 1002. By controlling the closing and opening of the first switch 1001 and the second switch 1002, it is possible to control whether the first controllable feedback submodule generates feedback. When both the first switch 1001 and the second switch 1002 are closed, the first controllable feedback submodule 23 can accelerate the difference between the differential signals at the output terminals of the first-stage circuit 201 through a feedback mechanism. When both the first switch 1001 and the second switch 1002 are open, the first controllable feedback submodule 23 is disconnected from the first-stage circuit 201, and the feedback mechanism cannot be generated at the output terminal of the first-stage circuit 201.

[0143] The second controllable feedback module 22 includes at least one second controllable feedback submodule 24, wherein each second controllable feedback submodule 24 includes a third feedback unit 2033, a fourth feedback unit 2034, a third switch 1003, and a fourth switch 1004. The third feedback unit 2033 and the fourth feedback unit 2034 each have a control terminal and a first terminal.

[0144] The control end of the third feedback unit 2033 is connected to the first output end of the first-stage circuit 201 via the third switch 1003, and the first end of the third feedback unit 2033 is connected to the second output end of the first-stage circuit 201. The control end of the fourth feedback unit 2034 is connected to the second output end of the first-stage circuit 201 via the third switch 1004, and the first end of the fourth feedback unit 2034 is connected to the first output end of the first-stage circuit 201.

[0145] The third feedback unit 2033 is configured to pull the voltage of the second output terminal of the first-stage circuit according to the voltage of the first output terminal of the first-stage circuit under the control of the third switch 1003. The fourth feedback unit 2034 is configured to pull the voltage of the first output terminal of the first-stage circuit according to the voltage of the second output terminal of the first-stage circuit under the control of the fourth switch 1004. By controlling the closing and opening of the third switch 1003 and the fourth switch 1004, it is possible to control whether the second controllable feedback submodule 23 generates feedback. When both the third switch 1003 and the fourth switch 1004 are closed, the second controllable feedback submodule 23 can accelerate the difference between the differential signals at the output terminals of the first-stage circuit 201 through a feedback mechanism. When both the third switch 1003 and the fourth switch 1004 are open, the second controllable feedback submodule 23 is disconnected from the first-stage circuit 201, and the feedback mechanism cannot be generated at the output terminal of the first-stage circuit 201.

[0146] When the comparator is operating, the number of the first controllable feedback submodule 23 and the second controllable feedback submodule 24 generating feedback can be controlled, thereby controlling the ability of the first controllable feedback module 21 and the second controllable feedback module 22 to increase the difference between the differential signals. This, on the one hand, controls the time the comparator is in the sampling phase, ensuring the comparator's response rate. On the other hand, it can also balance the ability of the feedback circuit 203 to increase the voltage at the output of the first-stage circuit 201 with the ability of the input signal and the reference signal to increase the voltage at the output of the first-stage circuit 201, ensuring that the comparator can accurately output a comparison result based on the input signal and the reference signal.

[0147] Figure 7 and Figure 8 Based on Figure 6 FIG4 is a specific circuit diagram of a comparator shown in FIG4 , wherein the structures of the first-stage circuit 201 and the second-stage circuit 202 are the same as those of the comparator shown in FIG4 , and are not described again here.

[0148] The following combination Figure 8 The specific circuit structures of the first controllable feedback submodule 23 and the second controllable feedback submodule 24 of the feedback circuit 203 are described.

[0149] The first feedback unit 2031 includes a first feedback transistor P8, a control terminal of which is connected to the second terminal of the first input transistor P1 via the first switch 1001. The second terminal of the first feedback transistor P8 is connected to the second terminal of the second input transistor P2.

[0150] The second feedback unit 2032 includes a second feedback transistor P9, whose control terminal is connected to the second terminal of the second input transistor P2 via the second switch 1002. The second terminal of the first feedback transistor P8 is connected to the second terminal of the first input transistor P1.

[0151] The third feedback unit 2033 includes a third feedback transistor N8, a control terminal of which is connected to the first terminal of the third input transistor N1 via the third switch 1003. The first terminal of the third feedback transistor N8 is connected to the first terminal of the fourth input transistor N2.

[0152] The fourth feedback unit 2034 includes a fourth feedback transistor N9, a control terminal of which is connected to the first terminal of the fourth input transistor N2 via the fourth switch 1004. The first terminal of the fourth feedback transistor N9 is connected to the first terminal of the third input transistor N1.

[0153] The first switch 1001 includes a first transmission gate G1 , which is controlled by a first enable signal EN1 .

[0154] The second switch 1002 includes a second transmission gate G2 controlled by a second enable signal EN2 .

[0155] The third switch 1003 includes a third transmission gate G3 , which is controlled by a third enable signal EN3 .

[0156] The fourth switch 1004 includes a fourth transmission gate G4 controlled by a fourth enable signal EN4 .

[0157] The first to fourth enable signals E1 to EN4 are all generated according to the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0158] When the first transmission gate G1 and the second transmission gate G2 are turned on, the first feedback transistor N8 and the second feedback transistor N9 work together to generate positive feedback. When the first transmission gate G1 and the second transmission gate G2 are turned off, the first feedback transistor N8 and the second feedback transistor N9 stop working.

[0159] In one embodiment, the first controllable feedback submodule 23 further includes a first zero switch K10 and a zero-zero switch K00. The control terminal of the first feedback transistor P8 is connected to the power supply terminal via the first zero switch 201. When the first transmission gate G1 is closed, the first zero switch K10 is turned on to prevent the first feedback transistor P8 from floating, thereby reducing external interference. The control terminal of the second feedback transistor P9 is connected to the power supply terminal via the zero-zero switch K00. When the second transmission gate G2 is closed, the zero-zero switch K00 is turned on to prevent the second feedback transistor P9 from floating, thereby reducing external interference.

[0160] In one embodiment, the second controllable feedback submodule 24 further includes a zero-first switch K01 and a first-first switch K11. The control terminal of the third feedback transistor N8 is connected to the ground terminal via the zero-first switch K01. When the third transmission gate G3 is closed, the zero-first switch K11 is turned on, preventing the third feedback transistor N8 from floating, thereby reducing external interference. The control terminal of the fourth feedback transistor N9 is connected to the ground terminal via the first-first switch K11. When the fourth transmission gate G4 is closed, the first-first switch K11 is turned on, preventing the fourth feedback transistor N9 from floating, thereby reducing external interference.

[0161] In one embodiment, the first zero switch K10 and the zeroth zero switch K00 are P-type transistors. The drain of the first zero switch K10 is connected to the gate of the first feedback transistor P8, the drain of the zeroth zero switch K00 is connected to the control terminal of the second feedback transistor P9, and the sources of the first zero switch 201 and the zeroth zero switch 202 are connected to the power supply terminal. When the first transmission gate G1 and the second transmission gate G2 are closed, the first feedback transistor P8 and the second feedback transistor P9 are pulled to a high level.

[0162] In one embodiment, the zeroth switch K01 and the first-first switch K11 are N-type transistors. The drain of the zeroth switch K01 is connected to the gate of the third feedback transistor N8, the drain of the first-first switch K11 is connected to the gate of the fourth feedback transistor N9, and the sources of the zeroth switch K01 and the first-first switch K11 are connected to the ground. When the third transmission gate G3 and the fourth transmission gate G4 are closed, the third feedback transistor N8 and the fourth feedback transistor N9 are pulled to a low level.

[0163] Figure 9 and Figure 10 Based on one of the specific circuit diagrams of the comparator shown in the figure, the structures of the first stage circuit 201, the second stage circuit 202 and the reset circuit are the same as Figure 4 The comparator shown is the same as the one shown in the figure, so it will not be described here in detail. Figure 8 Similar, no further description is given here.

[0164] In the above embodiment, the positive feedback circuit 203 includes multiple first controllable feedback sub-modules and multiple second controllable positive feedback sub-modules. By controlling the number of controllable positive feedback sub-modules that provide the positive feedback mechanism, the ability of the positive feedback circuit 203 to pull the voltage of the two output terminals of the first-stage circuit 201 is adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the positive feedback circuit 203 and the input signal and the reference signal on the output terminal of the first-stage circuit 201, thereby improving the response rate and accuracy of the comparator.

[0165] An embodiment of the present application provides a comparator, comprising a first-stage circuit, a second-stage circuit, and a positive feedback circuit, wherein the first-stage circuit has an output terminal, and the second-stage circuit and the positive feedback circuit are both connected to the output terminal of the first-stage circuit.

[0166] The first-stage circuit connects the power supply and ground terminals, causing the transistors in the first-stage circuit to form one current path. The second-stage circuit connects the power supply and ground terminals, causing the transistors in the second-stage circuit to form another current path. Compared to a comparator structure consisting of only one-stage circuit, this arrangement reduces the number of transistors in each current path, thereby lowering the comparator's operating voltage.

[0167] When the input signal and the reference signal generate a differential signal in the first-stage circuit, the positive feedback circuit is used to accelerate the difference between the differential signals. The first-stage circuit is also used to output the accelerated differential signal. The second-stage circuit is used to amplify and latch the voltage signal at the output of the first-stage circuit during the regeneration phase.

[0168] When the reference signal is not properly selected, the first-stage circuit takes a long time to present a differential signal with a large difference at the output, which increases the response time of the first-stage circuit. The positive feedback circuit accelerates the difference between the differential signals through the positive feedback mechanism, thereby shortening the time the first-stage circuit presents a differential signal with a large difference at the output. In other words, it shortens the time the comparator is in the sampling phase, thereby improving the comparator's response speed and reducing its power consumption.

[0169] In one embodiment, the first-stage circuit and the second-stage circuit have the same number of transistors in their respective current paths, so that the operating voltages of the first-stage circuit and the second-stage circuit are the same, reducing the number of power supply terminals required by the comparator and simplifying the circuit of the comparator.

[0170] In one embodiment, the first-stage circuit has two output terminals, which are labeled as a first output terminal and a second output terminal. The positive feedback circuit includes at least one controllable feedback submodule, wherein each controllable feedback submodule includes a third feedback unit, a fourth feedback unit, a third switch, and a fourth switch. The third feedback unit and the fourth feedback unit each have a control terminal and a first terminal.

[0171] The control end of the third feedback unit is connected to the first output end of the first-stage circuit via a third switch, and the first end of the third feedback unit is connected to the second output end of the first-stage circuit. The control end of the fourth feedback unit is connected to the second output end of the first-stage circuit via a fourth switch, and the first end of the fourth feedback unit is connected to the first output end of the first-stage circuit.

[0172] The third feedback unit is configured to, under the control of the third switch, pull the voltage of the second output terminal of the first-stage circuit based on the voltage of the first output terminal of the first-stage circuit. The fourth feedback unit is configured to, under the control of the fourth switch, pull the voltage of the first output terminal of the first-stage circuit based on the voltage of the second output terminal of the first-stage circuit. By controlling the closing and opening of the third and fourth switches, it is possible to control whether the first controllable feedback submodule generates feedback. When both the third and fourth switches are closed, the first controllable feedback submodule can accelerate the difference between the differential signals at the output terminals of the first-stage circuit through a feedback mechanism. When both the third and fourth switches are open, the first controllable feedback submodule is disconnected from the first-stage circuit, and the feedback mechanism cannot be generated at the output terminal of the first-stage circuit.

[0173] Figure 11 and Figure 12 A specific circuit diagram of a comparator provided in this application, Figure 13 and Figure 14 This is a specific circuit diagram of another comparator provided in this application. Figure 11 and Figure 12 The second stage circuit and reset circuit of the comparator shown are the same Figure 4 The second stage circuit and reset circuit in the comparator shown are the same and will not be described again here.

[0174] refer to Figure 11 and Figure 12 The first-stage circuit includes a third input transistor N1, a fourth input transistor N2 and a fifth input transistor N3. The three input transistors are N-type transistors, the gate of the N-type transistor is the control terminal, and the drain of the N-type transistor is the first terminal.

[0175] The control end of the third input transistor N1 is used to receive an input signal, the control end of the fourth input transistor N2 is used to receive a reference signal, the first end of the third input transistor N1 serves as the first output end of the first-stage circuit, the first end of the fourth input transistor N2 serves as the second output end of the first-stage circuit, the second end of the third input transistor N1 and the second end of the fourth input transistor N2 are connected to the first end of the fifth input transistor N3, and the second end of the fifth input transistor N3 is connected to the ground end.

[0176] The fifth input transistor N3 is used to control the operating state of the first-stage circuit. When the fifth input transistor N3 is turned on, the first-stage circuit operates. When the fifth input transistor N3 is turned off, the first-stage circuit stops operating. The third input transistor N1 and the fourth input transistor N2 are used to generate a differential signal based on the input signal and the reference signal.

[0177] Figure 12 The structure of the controllable feedback submodule in the positive feedback circuit shown is the same as Figure 8 The structure of the second controllable feedback submodule shown is the same and will not be repeated here.

[0178] refer to Figure 13 and Figure 14 When the third input transistor P1, the fourth input transistor P2 and the fifth input transistor P3 are P-type transistors, the gate of the P-type transistor is the control terminal, and the drain of the P-type transistor is the first terminal. Figure 14 The structure of the controllable feedback submodule in the positive feedback circuit shown is the same as Figure 10 The structure of the second controllable feedback submodule shown is the same and will not be repeated here.

[0179] In the above embodiment, the positive feedback circuit includes multiple controllable feedback sub-modules. By controlling the number of controllable positive feedback sub-modules that provide the positive feedback mechanism, the ability of the positive feedback circuit to pull the voltage of the two output terminals of the first-stage circuit is adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the positive feedback circuit and the input signal and reference signal on the output terminal of the first-stage circuit, thereby improving the response rate and accuracy of the comparator.

[0180] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0181] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A comparator, characterized in that: include: A first-stage circuit is connected to a power supply terminal and a ground terminal, and includes a first pair of transistors and a second pair of transistors. The first pair of transistors and the second pair of transistors are of different types. The first pair of transistors and the second pair of transistors are used to receive an input signal and a reference signal, and generate a differential signal according to the input signal and the reference signal during a sampling phase. a positive feedback circuit connected to the output terminal of the first stage circuit, for accelerating the difference between the differential signals; a second-stage circuit connected to a power supply terminal and a ground terminal, and connected to the output terminal of the first-stage circuit, and configured to amplify and latch the voltage signal at the output terminal of the first-stage circuit during a regeneration phase to output a comparison result; The positive feedback circuit comprises: a first feedback module connected to the output end of the first-stage circuit, configured to pull the voltage of the output end of the first-stage circuit to accelerate the difference between the differential signals; a second feedback module connected to the output end of the first stage circuit, and configured to pull the voltage of the output end of the first stage circuit to accelerate the difference between the differential signals; The first feedback module includes at least one first controllable feedback submodule, and each first controllable feedback submodule includes: a first feedback unit, having a control end connected to the first output end of the first-stage circuit via a first switch, and a first end connected to the second output end of the first-stage circuit, for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the first switch; a second feedback unit, having a control end connected to the second output end of the first-stage circuit via a second switch, and a first end connected to the first output end of the first-stage circuit, and configured to pull the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the second switch; The second feedback module includes at least one second controllable feedback submodule, and each first controllable feedback submodule includes: a third feedback unit, having a control end connected to the first output end of the first-stage circuit via a third switch, and a first end connected to the second output end of the first-stage circuit, for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the third switch; A fourth feedback unit, whose control end is connected to the second output end of the first-stage circuit through a fourth switch, and whose first end is connected to the first output end of the first-stage circuit, is used to pull the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the fourth switch.

2. The comparator according to claim 1, wherein: The first-stage circuit and the second-stage circuit have the same number of transistors on their respective current paths.

3. The comparator according to claim 1, wherein: The first feedback unit includes: a first feedback transistor, a control terminal of which is the control terminal of the first feedback unit, and a second terminal of which is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, a control terminal of which is the control terminal of the second feedback unit, and a second terminal of which is the first terminal of the second feedback unit; The third feedback unit includes: a third feedback transistor, a control terminal of which is the control terminal of the third feedback unit, and a first terminal of which is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, a control end of which is the control end of the fourth feedback unit, and a first end of which is the first end of the fourth feedback unit.

4. The comparator according to claim 3, wherein: The first stage circuit includes: a first input transistor, having a control terminal for receiving the input signal, a second terminal serving as a first output terminal of the first-stage circuit, a second terminal connected to the second terminal of the first feedback transistor, a first terminal connected to the first terminal of the first feedback transistor, and a first terminal further connected to a first power supply terminal or a ground terminal; a second input transistor, whose control end is used to receive the reference signal, whose second end serves as the second output end of the first-stage circuit, whose second end is connected to the second end of the second feedback transistor, whose first end is connected to the first end of the second feedback transistor, and whose first end is also connected to the first power supply end or the ground end.

5. The comparator according to claim 4, wherein: The first stage circuit further includes: a third input transistor, whose control terminal is used to receive the input signal, whose first terminal is connected to the second terminal of the first input transistor, and whose first terminal is connected to the first terminal of the third feedback transistor; a fourth input transistor, having a control terminal for receiving the reference signal, a first terminal connected to the second terminal of the second input transistor, and a first terminal connected to the first terminal of the fourth feedback transistor; a fifth input transistor, whose control end is used to receive a clock signal, whose first end is connected to the second end of the third input transistor, the second end of the fourth input transistor, the second end of the third feedback transistor, and the second end of the fourth feedback transistor, and whose second end is connected to the ground end or the power supply end.

6. The comparator according to claim 5, wherein: The first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are of the same type; The third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor, and the fifth input transistor are of the same type.

7. The comparator according to claim 6, wherein: When the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are all P-type transistors, the drain of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal; The third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor, and the fifth input transistor are all N-type transistors, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal; or When the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are all N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal; The third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor, and the fifth input transistor are all P-type transistors, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

8. The comparator according to claim 6, wherein: The first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is less than half of the size of the first input transistor; The third feedback transistor and the fourth feedback transistor have the same size, the third input transistor and the fourth input transistor have the same size, and the size of the third feedback transistor is less than half of the size of the fifth input transistor.

9. The comparator according to claim 1, wherein: The second stage circuit includes: a first output transistor, a control terminal of which is the first input terminal of the second stage circuit, a first terminal of which is the first output terminal of the second stage circuit, and a second terminal of which is connected to a ground terminal or a power supply terminal; a second output transistor, a control terminal of which is the second input terminal of the second stage circuit, a first terminal of which is the second output terminal of the second stage circuit, and a second terminal of which is connected to the ground terminal or the power supply terminal; a third output transistor, a first end of which is connected to the first end of the first output transistor, and a second end of which is connected to the second end of the first output transistor; a fourth output transistor, a first end of which is connected to the first end of the second output transistor, and a second end of which is connected to the second end of the second output transistor; a fifth output transistor, a second end of which is connected to the first end of the third output transistor, a control end of which is connected to the control end of the third output transistor, and a control end of which is further connected to the first end of the fourth output transistor; a sixth output transistor, a second end of which is connected to the first end of the fourth output transistor, a control end of which is connected to the control end of the fourth output transistor, and a control end of which is further connected to the first end of the third output transistor; The seventh output transistor has a control end for receiving a clock signal, a first end connected to a power supply end or a ground end, and a second end connected to the first end of the fifth output transistor and the first end of the sixth output transistor.

10. The comparator according to claim 9, wherein: The first output transistor to the fourth output transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; The fifth output transistor to the seventh output transistor are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; or The first output transistor to the fourth output transistor are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; The fifth output transistor to the seventh output transistor are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

11. The comparator according to claim 1, wherein: The first switch includes a first transmission gate controlled by a first enable signal; The second switch includes a second transmission gate controlled by a second enable signal; The third switch includes a third transmission gate, and the third transmission gate is controlled by a third enable signal; The fourth switch includes a fourth transmission gate, and the fourth transmission gate is controlled by a fourth enable signal; The first to fourth enable signals are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

12. The comparator according to claim 1, wherein: The control end of the first feedback unit is further connected to the power supply end via a first zero switch; The control end of the second feedback unit is further connected to the power supply end through the zeroth zero switch; The control end of the third feedback unit is further connected to the ground end through the zero-first switch; The control end of the fourth feedback unit is further connected to the ground end through the first switch.

13. A comparator, characterized in that: include: The first stage circuit is connected to the power supply terminal and the ground terminal, and is provided with an output terminal for generating a differential signal according to the input signal and the reference signal during a sampling phase; a positive feedback circuit connected to the output terminal of the first stage circuit, for accelerating the difference between the differential signals; a second-stage circuit connected to a power supply terminal and a ground terminal, and connected to the output terminal of the first-stage circuit, and configured to amplify and latch the voltage signal at the output terminal of the first-stage circuit during a regeneration phase to output a comparison result; The first-stage circuit has two output terminals. The positive feedback circuit includes at least one controllable feedback submodule, and each controllable feedback submodule includes: a third feedback unit, having a control end connected to the first output end of the first-stage circuit via a third switch, and a first end connected to the second output end of the first-stage circuit, for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the third switch; A fourth feedback unit, whose control end is connected to the second output end of the first-stage circuit through a fourth switch, and whose first end is connected to the first output end of the first-stage circuit, is used to pull the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the fourth switch.

14. The comparator according to claim 13, wherein: The first-stage circuit and the second-stage circuit have the same number of transistors on their respective current paths.

15. The comparator according to claim 13, wherein: The third feedback unit includes: a third feedback transistor, a control terminal of which is the control terminal of the third feedback unit, and a first terminal of which is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, a control end of which is the control end of the fourth feedback unit, and a first end of which is the first end of the fourth feedback unit.

16. The comparator according to claim 13, wherein: The third switch includes a third transmission gate, and the third transmission gate is controlled by a third enable signal; The fourth switch includes a fourth transmission gate, and the fourth transmission gate is controlled by a fourth enable signal; The third enable signal and the fourth enable signal are generated according to the operating frequency of the comparator, the input common mode range of the comparator and a test mode signal.

17. The comparator according to claim 13, wherein: The control end of the third feedback unit is further connected to the ground end through the zero-first switch; The control end of the fourth feedback unit is further connected to the ground end through the first switch.

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