Comparator

Abstract

The present application provides a comparator, comprising an input circuit, comprising a first pair of transistors and a second pair of transistors, each of which receives an input signal and a reference signal, and is configured to generate a differential signal based on the input signal and the reference signal during a sampling phase, wherein the first pair of transistors and the second pair of transistors have different transistor types; and an output circuit, connected to the output end of the input circuit, configured to amplify and latch the voltage signal at the output end of the input circuit during a regeneration phase to output a comparison result. In this comparator, since the two pairs of transistors pull voltage in opposite directions, even a slight difference between the input signal and the reference signal can cause an imbalance in the pulling capacity of the transistors in the two pairs of transistors, thereby generating a differential signal at the two output ends of the input circuit, thereby improving the comparison accuracy of the comparator.

Description

Technical Field

[0001] The present application relates to an integrated circuit, and in particular to a comparator. Background Art

[0002] Nowadays, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which has greatly enriched our daily life and work.

[0003] However, limited battery life places higher demands on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, and therefore, DRAM urgently needs to achieve lower operating voltages and lower energy consumption. Among them, comparators are crucial for reading and writing DRAM data, and existing comparators cannot meet current usage requirements. Summary of the Invention

[0004] The present application provides a comparator, which aims to improve the comparison accuracy and response rate of the comparator, reduce the power consumption of the comparator, and expand the amplitude range of the reference signal of the comparator.

[0005] In one aspect, the present application provides a comparator, comprising:

[0006] an input circuit, comprising a first pair of transistors and a second pair of transistors, wherein the first pair of transistors and the second pair of transistors both receive an input signal and a reference signal, and are configured to generate a differential signal according to the input signal and the reference signal during a sampling phase, wherein the first pair of transistors and the second pair of transistors have different transistor types;

[0007] The output circuit is connected to the output end of the input circuit and is used to amplify and latch the voltage signal of the output end of the input circuit in the regeneration phase to output a comparison result.

[0008] Optionally, the comparator further includes:

[0009] The positive feedback circuit is connected to the output terminal of the input circuit and is used to speed up the difference between the differential signals.

[0010] Optionally, the positive feedback circuit includes:

[0011] A first positive feedback module is connected to the output terminal of the input circuit and is used to accelerate the difference between the differential signals by pulling the voltage of the output terminal of the input circuit;

[0012] The second positive feedback module is connected to the output terminal of the input circuit and is used to accelerate the difference between the differential signals by pulling the voltage of the output terminal of the input circuit.

[0013] Optionally, the input circuit has two output terminals, and the first positive feedback module includes:

[0014] a first positive feedback unit, having a control end connected to the first output end of the input circuit and a first end connected to the second output end of the input circuit, for pulling the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit;

[0015] The second positive feedback unit has a control end connected to the second output end of the input circuit and a first end connected to the first output end of the input circuit, and is used to pull the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit.

[0016] Optionally, the first positive feedback unit includes: a first positive feedback transistor, a control end of which is the control end of the first positive feedback unit, and a second end of which is the first end of the first positive feedback unit;

[0017] The second positive feedback unit includes: a second positive feedback transistor, a control end of which is the control end of the second positive feedback unit, and a second end of which is the first end of the second positive feedback unit.

[0018] Optionally, the input circuit has two output terminals, and the second positive feedback module includes:

[0019] a third positive feedback unit, whose control end is connected to the first output end of the input circuit, and whose first end is connected to the second output end of the input circuit, and is used to pull the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit;

[0020] The fourth positive feedback unit has a control end connected to the second output end of the input circuit and a first end connected to the first output end of the input circuit, and is used to pull the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit.

[0021] Optionally, the third positive feedback unit includes: a third positive feedback transistor, a control end of which is the control end of the third positive feedback unit, and a first end of which is the first end of the third positive feedback unit;

[0022] The fourth positive feedback unit includes: a fourth positive feedback transistor, a control end of which is the control end of the fourth positive feedback unit, and a first end of which is the first end of the fourth positive feedback unit.

[0023] Optionally, the input circuit includes:

[0024] A first input transistor, whose control terminal is used to receive an input signal, whose second terminal serves as a first output terminal of the input circuit, and whose first terminal is connected to the first terminal of the first positive feedback transistor;

[0025] a second input transistor, whose control terminal is used to receive a reference signal, whose second terminal serves as a second output terminal of the input circuit, and whose first terminal is connected to the first terminal of the second positive feedback transistor;

[0026] a third input transistor, whose control terminal is used to receive an input signal, whose first terminal serves as a first output terminal of the input circuit, and whose second terminal is connected to the second terminal of the third positive feedback transistor;

[0027] The fourth input transistor has a control terminal for receiving a reference signal, a first terminal serving as the second output terminal of the input circuit, and a second terminal connected to the second terminal of the fourth positive feedback transistor.

[0028] Optionally, the input circuit further includes:

[0029] a fifth input transistor, having a control end for receiving a clock signal, a second end connected to the first end of the first input transistor, the first end of the second input transistor, the first end of the first positive feedback transistor, and the first end of the second positive feedback transistor, and a first end connected to the power supply end;

[0030] The sixth input transistor has a control end for receiving a clock signal, a first end connected to the second end of the third input transistor, the second end of the fourth input transistor, the second end of the third positive feedback transistor, and the second end of the fourth positive feedback transistor, and a second end connected to the ground end.

[0031] Optionally, the first positive feedback transistor, the second positive feedback transistor, the first input transistor, and the second input transistor are of the same type;

[0032] The third positive feedback transistor, the fourth positive feedback transistor, the third input transistor, and the fourth input transistor are of the same type.

[0033] Optionally, the first positive feedback transistor, the second positive feedback transistor, the first input transistor and the second input transistor are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal;

[0034] The third positive feedback transistor, the fourth positive feedback transistor, the third input transistor and the fourth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0035] Optionally, the comparator further includes:

[0036] The first reset circuit is connected between the first output terminal of the input circuit and the second output terminal of the input circuit, and is used for resetting the voltage of the first output terminal of the input circuit and the voltage of the second output terminal of the input circuit.

[0037] Optionally, the comparator further includes:

[0038] a second reset circuit connected to the first output terminal of the output circuit, for resetting the voltage of the first output terminal of the output circuit;

[0039] The third reset circuit is connected to the second output terminal of the output circuit and is used for resetting the voltage of the second output terminal of the output circuit.

[0040] Optionally, the first reset circuit includes:

[0041] a first clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to a first output terminal of the input circuit;

[0042] The second clock-controlled transistor has a control end receiving a clock signal, a second end connected to the second output end of the input circuit, and a first end connected to the first end of the first clock-controlled transistor.

[0043] Optionally, the second reset circuit includes: a third clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the first output terminal of the output circuit;

[0044] The third reset circuit includes: a fourth clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the second output terminal of the output circuit.

[0045] Optionally, the first clock-controlled transistor, the second clock-controlled transistor, the third clock-controlled transistor and the fourth clock-controlled transistor are of the same type.

[0046] Optionally, the output circuit includes:

[0047] a first output transistor, a second terminal of which is a first input terminal of the output circuit;

[0048] a second output transistor, a second terminal of which is a second input terminal of the output circuit;

[0049] a third output transistor, a control terminal of which is connected to the control terminal of the first output transistor, and a control terminal of which is further connected to the second terminal of the fourth output transistor, and a second terminal of which is connected to the first terminal of an output transistor, the second terminal of the third output transistor serving as the first output terminal of the output circuit;

[0050] The fourth output transistor has its control end connected to the control end of the second output transistor, and its control end is also connected to the second end of the third output transistor, and its second end is connected to the first end of the second output transistor. The second end of the fourth output transistor serves as the second output end of the output circuit.

[0051] Optionally, the first output transistor and the second output transistor are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal;

[0052] The third output transistor and the fourth output transistor are both P-type transistors, the first to fourth clock-controlled transistors are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0053] Optionally, the first input transistor and the second output transistor are both P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal;

[0054] The third output transistor and the fourth output transistor are both N-type transistors, the first to fourth clock-controlled transistors are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0055] Optionally, the first positive feedback transistor and the second positive feedback transistor have the same size, the first input transistor, the second input transistor and the fifth input transistor have the same size, and the size of the first positive feedback transistor is less than half of the size of the first input transistor;

[0056] The third positive feedback transistor and the fourth positive feedback transistor have the same size, the third input transistor, the fourth input transistor and the sixth input transistor have the same size, and the size of the third positive feedback transistor is less than half of the size of the third input transistor.

[0057] Optionally, the first positive feedback module includes at least one first controllable positive feedback submodule, and each first controllable positive feedback submodule includes:

[0058] a first positive feedback unit, having a control end connected to the first output end of the input circuit via a first switch, and a first end connected to the second output end of the input circuit, for pulling the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit under the control of the first switch;

[0059] a second positive feedback unit, a control end of which is connected to the second output end of the input circuit via a second switch, and a first end of which is connected to the first output end of the input circuit, for pulling the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit under the control of the second switch;

[0060] The second positive feedback module includes at least one second controllable positive feedback submodule, and each first controllable positive feedback submodule includes:

[0061] a third positive feedback unit, having a control end connected to the first output end of the input circuit via a third switch, and a first end connected to the second output end of the input circuit, for pulling the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit under the control of the third switch;

[0062] A fourth positive feedback unit, whose control end is connected to the second output end of the input circuit through a fourth switch, and whose first end is connected to the first output end of the input circuit, is used to pull the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit under the control of the fourth switch.

[0063] Optionally, the first positive feedback unit includes: a first positive feedback transistor, a control terminal of which is the input terminal of the first positive feedback unit, and a second terminal of which is the first terminal of the first positive feedback unit;

[0064] The second positive feedback unit includes: a second positive feedback transistor, a control terminal of which is the input terminal of the second positive feedback unit, and a second terminal of which is the first terminal of the second positive feedback unit;

[0065] The third positive feedback unit includes: a third positive feedback transistor, a control end of which is the input end of the third positive feedback unit, and a first end of which is the first end of the third positive feedback unit;

[0066] The fourth positive feedback unit includes: a fourth positive feedback transistor, a control end of which is the input end of the fourth positive feedback unit, and a first end of which is the first end of the fourth positive feedback unit.

[0067] Optionally, the first switch includes a first transmission gate, and the first transmission gate is controlled by a first enable signal;

[0068] The second switch includes a second transmission gate controlled by a second enable signal;

[0069] The third switch includes a third transmission gate controlled by a third enable signal;

[0070] The fourth switch includes a fourth transmission gate controlled by a fourth enable signal;

[0071] The first to fourth enable signals are generated according to the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0072] Optionally, the control end of the first positive feedback unit is further connected to the power supply end via a first zero switch;

[0073] The control end of the second positive feedback unit is also connected to the power supply end through the zeroth zero switch;

[0074] The control terminal of the third positive feedback unit is also connected to the ground terminal through the zero-first switch;

[0075] The control end of the fourth positive feedback unit is further connected to the ground end through the first switch.

[0076] In the above technical solution, two sets of transistors of different types receive the input signal and the reference signal. Because the two sets of transistors pull voltage in opposite directions, even a slight difference between the input signal and the reference signal can lead to an imbalance in the pulling capacity of the transistors in the two sets of transistors. This generates a differential signal at the two output terminals of the input circuit. The output circuit amplifies and latches the differential signal and outputs the comparison result, thereby improving the comparison accuracy of the comparator. Because the input circuit uses two sets of transistors to receive the input signal and the reference signal, the different pulling capacities of the two sets of transistors in different directions increase the response time of the input circuit. After the two sets of transistors generate a differential signal based on the input signal and the reference signal, a positive feedback circuit accelerates the difference between the differential signals, shortening the sampling phase, thereby improving the response speed of the comparator and reducing its power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0078] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0079] Figure 2 The working timing diagram of the comparator provided in this application;

[0080] Figure 3 A structural block diagram of a comparator provided in this application;

[0081] Figure 4 A structural block diagram of another comparator provided in this application;

[0082] Figure 5 Based on Figure 4 A specific circuit diagram of one of the provided comparators;

[0083] Figure 6 Based on Figure 4 A specific circuit diagram of another comparator provided;

[0084] Figure 7 A structural block diagram of another comparator provided in this application;

[0085] Figure 8 Based on Figure 7 A specific circuit diagram of one of the provided comparators;

[0086] Figure 9 for Figure 8 A specific circuit diagram of the first controllable positive feedback submodule in the provided comparator;

[0087] Figure 10 for Figure 8 A specific circuit diagram of the second controllable positive feedback submodule in the provided comparator;

[0088] Figure 11 Based on Figure 7 Another specific circuit diagram of a comparator is provided.

[0089] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0090] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0091] First combine Figure 1 The comparator shown describes the working process of the comparator.

[0092] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output end of the input circuit 101 is connected to the input end of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0093] The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3. The transistor N1 and the transistor N2 constitute a differential transistor pair. The gate of the transistor N1 and the gate of the transistor N2 constitute a first input terminal IP and a second input terminal IN of the input circuit. The drain of the transistor N1 and the drain of the transistor N2 constitute two output terminals of the input circuit.

[0094] Output circuit 102 includes transistors P1, P2, N4, and N5. These four transistors form a cross-coupled transistor pair. The drains of transistors P1 and N4 form a first output terminal ON of output circuit 102, and the drains of transistors P2 and N5 form a second output terminal OP of output circuit 102. Reset circuit 103 includes transistors P3 and P4.

[0095] The working process of the comparator is divided into four stages: reset stage, sampling stage, regeneration stage and decision stage. Figure 2 describe Figure 1The working process of the comparator shown is:

[0096] In the reset phase, that is, from time t0 to time t1, the clock signal is at a low level, transistor N3 is disconnected, the input circuit and the output circuit stop working, transistor P3 and transistor P4 are closed, and the reset circuit works, pulling the drain voltage of transistor N4 and the drain voltage of transistor N5 to a high level.

[0097] During the sampling phase, from time t1 to time t2, the clock signal is high, transistors P3 and P4 are disconnected, and the reset circuit stops operating. Transistor N3 is closed, and the input circuit collects the input signal through the first input terminal IP. The input circuit collects the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the input signal pulls up the drain voltage of transistor N1 at a faster rate, causing the drain voltage of transistor N4 to be lower than the drain voltage of transistor N5.

[0098] In the regeneration stage, that is, from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the flip voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually disconnected, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N5.

[0099] During the decision phase, that is, from time t3 to time t4, transistor P2 and transistor N4 are turned on, and transistor P1 and transistor N5 are turned off, continuing to pull up the drain voltage of transistor N5 and continuing to pull down the drain voltage of transistor N4. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0100] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the transistors N4 and N5 are reset to a high level by the transistors P1 and P2.

[0101] like Figure 3 As shown, an embodiment of the present application provides a comparator, which includes an input circuit 101 and an output circuit 102. The input circuit 101 and the output circuit 102 are both provided with an input terminal and an output terminal, and the output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102.

[0102] Input circuit 101 includes a first pair of transistors and a second pair of transistors. The first pair of transistors and the second pair of transistors have different transistor types. For example, when the first pair of transistors are N-type transistors, the second pair of transistors are P-type transistors. When the first pair of transistors are P-type transistors, the second pair of transistors are N-type transistors.

[0103] Both the first pair of transistors and the second pair of transistors receive an input signal and a reference signal. Specifically, the first transistor in the first pair of transistors is used to receive the input signal, and the second transistor in the first pair of transistors is used to receive the reference signal. The first transistor in the second pair of transistors is used to receive the input signal, and the second transistor in the second pair of transistors is used to receive the reference signal. After receiving the input signal and the reference signal, the first pair of transistors and the second pair of transistors are used to generate a differential signal based on the input signal and the reference signal during a sampling phase, and output the differential signal as the output signal of input circuit 101.

[0104] Because the first and second pairs of transistors are of different transistor types, they pull voltage in different directions. If the first pair of transistors are N-type transistors and the second pair of transistors are P-type transistors, the first pair of transistors has the ability to pull down the voltage, while the second pair of transistors has the ability to pull up the voltage. If the first pair of transistors are P-type transistors and the second pair of transistors are N-type transistors, the first pair of transistors has the ability to pull up the voltage, while the second pair of transistors has the ability to pull down the voltage.

[0105] The input signal and reference signal are used to control the voltage-pulling capabilities of the first and second pairs of transistors. By pulling the voltage in different directions, the two pairs of transistors can detect slight differences between the input and reference signals. These differences are reflected in the output voltages of the two pairs of transistors, forming a differential signal. The inclusion of two pairs of transistors in input circuit 101 allows for the detection of relatively small differences, thereby improving the accuracy of the comparator.

[0106] For example, if the first pair of transistors are P-type transistors and the second pair are N-type transistors, the reference signal balances the ability of the second transistor in the first pair to pull up the voltage and the ability of the second transistor in the second pair to pull down the voltage. When the input signal is slightly greater than the reference signal, the ability of the first transistor in the second pair to pull down the voltage is greater than the ability of the first transistor in the first pair to pull up the voltage, causing the output voltage of the first transistor in the two pairs of transistors to be lower than the output voltage of the second transistor in the two pairs of transistors.

[0107] The output circuit 102 is used to amplify and latch the voltage signal at the output end of the input circuit 101 in the regeneration phase to output a comparison result.

[0108] In the above technical solution, two groups of transistor pairs of different types receive the input signal and the reference signal. Since the two groups of transistor pairs pull the voltage in opposite directions, even a slight difference between the input signal and the reference signal will cause the pulling capabilities of the transistors in the two groups of transistor pairs to be unbalanced. A differential signal can be generated at the two output ends of the input circuit. The output circuit 102 amplifies and latches the differential signal and then outputs a comparison result, thereby improving the comparison accuracy of the comparator.

[0109] like Figure 4 As shown, an embodiment of the present application provides a comparator, which includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104. The input circuit 101 and the output circuit 102 are both provided with an input terminal and an output terminal, the output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102, and the positive feedback circuit 104 is connected to the output terminal of the input circuit 101.

[0110] The input circuit 101 and the output circuit 102 have been described in detail in the above embodiments and will not be described again in detail.

[0111] When there's a difference between the input signal and the reference signal, generating a differential signal across the two transistor pairs, positive feedback circuit 104 accelerates the difference between the differential signals. Input circuit 101 also outputs the accelerated differential signal. Output circuit 102 amplifies and latches the voltage signal at the output of input circuit 101 during the regeneration phase. The voltage signal at the output of input circuit 101 is then amplified and latched and output as the comparison result.

[0112] Because input circuit 101 uses two pairs of transistors to receive input and reference signals, and the two pairs of transistors have different voltage-pulling capabilities, it takes longer for input circuit 101 to present a significantly different differential signal at its output. This increases the response time of input circuit 101. The positive feedback circuit accelerates the difference between the differential signals through a positive feedback mechanism, thereby shortening the time that input circuit 101 presents a significantly different differential signal at its output. This shortens the time the comparator spends in the sampling phase, thereby increasing the comparator's response speed and reducing its power consumption.

[0113] In one embodiment, the positive feedback circuit 104 includes a first positive feedback module 1040 and a second positive feedback module 1049. The first positive feedback module 1040 is connected to the output terminal of the input circuit 101 and is configured to pull the voltage at the output terminal of the input circuit 101 to accelerate the difference between the differential signals. The second positive feedback module 1049 is also connected to the output terminal of the input circuit 101 and is configured to pull the voltage at the output terminal of the input circuit 101 to accelerate the difference between the differential signals. The voltage pulling direction of the first positive feedback module is different from that of the second positive feedback module.

[0114] Two positive feedback modules are used to pull the output voltage of the input circuit 101 in different directions respectively, so as to speed up the difference between the differential signals, thereby shortening the time of the comparator in the sampling phase and improving the response rate of the comparator.

[0115] More specifically, the input circuit 101 has two output terminals, labeled as a first output terminal VN and a second output terminal VP. The first positive feedback module 1040 includes a first positive feedback unit 1041 and a second positive feedback unit 1042. The first positive feedback unit 1041 and the second positive feedback unit 1042 each have a control terminal and a first terminal.

[0116] The control terminal of the first positive feedback unit 1041 is connected to the first output terminal VN of the input circuit 101 , and the first terminal of the first positive feedback unit 1041 is connected to the second output terminal VP of the input circuit 101 .

[0117] A control terminal of the second positive feedback unit 1042 is connected to the second output terminal VP of the input circuit 101 , and a first terminal of the second positive feedback unit 1042 is connected to the first output terminal VN of the input circuit 101 .

[0118] The first positive feedback unit 1041 is used to pull up the voltage of the second output terminal VP of the input circuit 101 according to the voltage of the first output terminal VN of the input circuit 101 during the sampling phase.

[0119] The second positive feedback unit 1402 is used to pull up the voltage of the first output terminal VN of the input circuit 101 according to the voltage of the second output terminal VP of the input circuit 101 during the sampling phase.

[0120] When the voltage of the first output terminal VN of the input circuit 101 is higher than the voltage of the second output terminal VP of the input circuit 101, the first positive feedback unit 1041 has a weaker ability to pull up the voltage of the second output terminal VP of the input circuit 101, and the second positive feedback unit 1042 has a stronger ability to pull up the voltage of the first output terminal VN of the input circuit 101, that is, the voltage rising rate of the first output terminal VN is higher than the rising rate of the second output terminal VP, thereby making the voltage difference between the first output terminal voltage VN and the second output terminal VP larger and larger, realizing positive positive feedback.

[0121] When the voltage of the first output terminal VN of the input circuit 101 is lower than the voltage of the second output terminal VP of the input circuit 101, the first positive feedback unit 1041 has a stronger ability to pull up the voltage of the second output terminal VP of the input circuit 101, and the second positive feedback unit 1042 has a weaker ability to pull up the voltage of the first output terminal VN of the input circuit 101, that is, the voltage rising rate of the first output terminal VP is lower than the rising rate of the second output terminal VN, thereby making the voltage difference between the first output terminal voltage VP and the second output terminal VN larger and larger, realizing positive positive feedback.

[0122] More specifically, the second positive feedback module 1049 includes a third positive feedback unit 1043 and a fourth positive feedback unit 1044. The third positive feedback unit 1043 and the fourth positive feedback unit 1044 are both provided with a control terminal and a first terminal.

[0123] The control terminal of the third positive feedback unit 1043 is connected to the first output terminal VN of the input circuit 101 , and the first terminal of the third positive feedback unit 1043 is connected to the second output terminal VP of the input circuit 101 .

[0124] A control terminal of the fourth positive feedback unit 1044 is connected to the second output terminal VP of the input circuit 101 , and a first terminal of the fourth positive feedback unit 1044 is connected to the first output terminal VN of the input circuit 101 .

[0125] The third positive feedback unit 1043 is configured to pull down the voltage of the second output terminal VP of the input circuit 101 according to the voltage of the first output terminal VN of the input circuit 101 during the sampling phase.

[0126] The fourth positive feedback unit 1044 is configured to pull down the voltage of the first output terminal VN of the input circuit 101 according to the voltage of the second output terminal VP of the input circuit 101 during the sampling phase.

[0127] When the voltage of the first output terminal VN of the input circuit 101 is higher than the voltage of the second output terminal VP of the input circuit 101, the third positive feedback unit 1043 has a stronger ability to pull down the voltage of the second output terminal VP of the input circuit 101, and the fourth positive feedback unit 1044 has a weaker ability to pull down the voltage of the first output terminal VN of the input circuit 101, that is, the voltage drop rate of the first output terminal VN is lower than the voltage drop rate of the second output terminal VP, thereby making the voltage difference between the first output terminal voltage VN and the second output terminal VP larger and larger, realizing positive positive feedback.

[0128] When the voltage of the first output terminal VN of the input circuit 101 is lower than the voltage of the second output terminal VP of the input circuit 101, the third positive feedback unit 1043 has a weaker ability to pull down the voltage of the second output terminal VP of the input circuit 101, and the fourth positive feedback unit 1044 has a stronger ability to pull down the voltage of the first output terminal VN of the input circuit 101, that is, the voltage drop rate of the first output terminal VN is higher than the voltage drop rate of the second output terminal VP, thereby making the voltage difference between the first output terminal voltage VN and the second output terminal VP larger and larger, realizing positive positive feedback.

[0129] In the above technical solution, two pairs of transistors of different types receive the input signal and the reference signal. Because the two pairs of transistors pull the voltage in opposite directions, a differential signal can be generated even with a slight difference between the input signal and the reference signal, thereby improving the comparison accuracy of the comparator. Since input circuit 101 uses two pairs of transistors to receive the input signal and the reference signal, the different voltage pulling capabilities of the two pairs of transistors increase the response time of input circuit 101. After the two pairs of transistors generate the differential signal based on the input signal and the reference signal, the positive feedback circuit 104 accelerates the difference between the differential signals, shortening the sampling phase, thereby improving the response speed of the comparator and reducing the power consumption of the comparator.

[0130] Figure 5 A schematic diagram of a circuit structure of a comparator provided in another embodiment of the present application is shown in FIG. Figure 5 As shown, the comparator provided in this application includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0131] The input circuit 101 includes a first input transistor 1011, a second input transistor 1012, a third input transistor 1013, a fourth input transistor 1014, a fifth input transistor 1015, and a sixth input transistor 1016. Each input transistor has a control terminal, a first terminal, and a second terminal.

[0132] The second terminal of the first input transistor 1011 and the first terminal of the third input transistor 1013 are connected. The control terminal of the first input transistor 1011 and the control terminal of the third input transistor 1013 serve as the first input terminal IP of the input circuit 101 for receiving an input signal. The second terminal of the first input transistor 1011 and the first terminal of the third input transistor 1013 serve as the first output terminal VN of the input circuit 101.

[0133] The second terminal of the second input transistor 1012 is connected to the first terminal of the fourth input transistor 1014. The control terminal of the second input transistor 1012 and the control terminal of the fourth input transistor 1014 serve as the second input terminal IN of the input circuit 101 for receiving a reference signal. The second terminal of the second input transistor 1012 and the first terminal of the fourth input transistor 1014 serve as the second output terminal VP of the input circuit 101.

[0134] A second terminal of the fifth input transistor 1015 is connected to the first terminal of the first input transistor 1011 and the first terminal of the second input transistor 1012, and a first terminal of the fifth input transistor 1015 is connected to the power supply terminal. A first terminal of the sixth input transistor 1016 is connected to the second terminal of the third input transistor 1013 and the second terminal of the fourth input transistor 1014, and a second terminal of the sixth input transistor 1016 is connected to the ground terminal.

[0135] The control terminal of the fifth input transistor 1015 is used to receive a clock signal. The fifth input transistor 1015 is used to control the operating states of the first input transistor 1011 and the second input transistor 1012. When the fifth input transistor 1015 is closed, the first input transistor 1011 and the second input transistor 1012 are in operation. When the fifth input transistor 1015 is opened, the first input transistor 1011 and the second input transistor 1012 stop operating.

[0136] The control terminal of the sixth input transistor 1016 is used to receive a clock signal. The sixth input transistor 1016 is used to control the operating states of the third input transistor 1013 and the fourth input transistor 1014, and is also used to control the operating state of the output circuit 102. When the sixth input transistor 1016 is closed, the third input transistor 1013 and the fourth input transistor 1014 are in operation, and the output circuit 102 is also in operation. When the sixth input transistor 1016 is opened, the third input transistor 1013 and the fourth input transistor 1014 are deactivated, and the output circuit 102 is also deactivated.

[0137] The control terminals of the first input transistor 1011 and the third input transistor 1013 are used to receive an input signal, while the control terminals of the second input transistor 1012 and the fourth input transistor 1014 are used to receive a reference signal. The input signal controls the conduction or cutoff of the first input transistor 1011 and the third input transistor 1013. The reference signal turns the second input transistor 1012 and the fourth input transistor 1014 on or off. The input signal is amplified by the first input transistor 1011 and / or the third input transistor 1013, and the reference signal is amplified by the second input transistor 1012 and / or the fourth input transistor 1014, generating a differential signal between the second terminal of the first input transistor 1011 and the second terminal of the second input transistor 1012.

[0138] The output circuit 102 includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023, and a fourth output transistor 1024, forming a cross-coupled circuit. The first terminal of the first output transistor 1021 is connected to the second terminal of the third output transistor 1023, and the first terminal of the second output transistor 1022 is connected to the second terminal of the fourth output transistor 1024. The control terminal of the first output transistor 1021 is connected to the control terminal of the third output transistor 1023, and then to the second terminal of the fourth output transistor 1024. The control terminal of the second output transistor 1022 is connected to the control terminal of the fourth output transistor 1024, and then to the second terminal of the third output transistor 1023.

[0139] The second end of the first output transistor 1021 serves as the first input end of the output circuit 102, and the second end of the second output transistor 1022 serves as the second input end of the output circuit 102. The second end of the first output transistor 1021 is connected to the second end of the first input transistor 1011, and the second end of the second output transistor 1022 is connected to the second end of the second input transistor 1012. The second end of the third output transistor 1023 serves as the first output end ON of the output circuit 102, and the second end of the fourth output transistor 1024 serves as the second output end OP of the output circuit 102.

[0140] After the first input transistor 1011 and / or the third input transistor 1013 are turned on, and the second input transistor 1012 and / or the fourth input transistor 1014 are turned on, the voltage at the first terminal of the first output transistor 1021 and the first terminal of the second output transistor 1022 are pulled down. When the voltage is pulled down to the flip-flop voltage, the transistors are turned on. That is, the first output transistor 1021 and the fourth output transistor 1024 are turned on, or the second output transistor 1022 and the third output transistor 1023 are turned on. If the first output transistor 1021 and the fourth output transistor 1024 are turned on, the voltage at the second terminal of the fourth output transistor 1024 is pulled up, and the voltage at the second terminal of the third output transistor 1023 is pulled down. If the second output transistor 1022 and the third output transistor 1023 are turned on, the voltage at the second terminal of the fourth output transistor 1024 is pulled down, and the voltage at the second terminal of the third output transistor 1023 is pulled up, thereby amplifying and latching the voltage signal output by the input circuit 101.

[0141] In one embodiment, the first positive feedback unit 1041 includes a first positive feedback transistor 1045. The control terminal of the first positive feedback transistor 1045 serves as the control terminal of the first positive feedback unit 1041, and the second terminal of the first positive feedback transistor 1045 serves as the first terminal of the first positive feedback unit 1041. The control terminal of the first positive feedback transistor 1045 is connected to the second terminal of the first input transistor 1011, the first terminal of the first positive feedback transistor 1045 is connected to the first terminal of the second input transistor 1012, and the second terminal of the first positive feedback transistor 1045 is connected to the second terminal of the second input transistor 1012. The first terminal of the first positive feedback transistor 1045 is also connected to the second terminal of the fifth input transistor 1015.

[0142] The control terminal of the second positive feedback transistor 1046 serves as the control terminal of the second positive feedback unit 1042, and the second terminal of the second positive feedback transistor 1046 serves as the first terminal of the second positive feedback unit 1042. The control terminal of the second positive feedback transistor 1046 is connected to the second terminal of the second input transistor 1012, the second terminal of the second positive feedback transistor 1046 is connected to the second terminal of the first input transistor 1011, and the first terminal of the second positive feedback transistor 1046 is connected to the first terminal of the first input transistor 1011. The first terminal of the second positive feedback transistor 1046 is also connected to the second terminal of the fifth input transistor 1015.

[0143] In one embodiment, the third positive feedback unit 1043 includes a third positive feedback transistor 1047. The control terminal of the third positive feedback transistor 1047 serves as the control terminal of the third positive feedback unit 1043, and the first terminal of the third positive feedback transistor 1047 serves as the first terminal of the third positive feedback unit 1043. The control terminal of the third positive feedback transistor 1047 is connected to the first terminal of the third input transistor 1013, the first terminal of the third positive feedback transistor 1047 is connected to the first terminal of the fourth input transistor 1014, and the second terminal of the third positive feedback transistor 1047 is connected to the second terminal of the fourth input transistor 1014. The second terminal of the third positive feedback transistor 1047 is also connected to the first terminal of the sixth input transistor 1016.

[0144] The control terminal of the fourth positive feedback transistor 1048 serves as the control terminal of the fourth positive feedback unit 1044, and the first terminal of the fourth positive feedback transistor 1048 serves as the first terminal of the fourth positive feedback unit 1044. The control terminal of the fourth positive feedback transistor 1048 is connected to the first terminal of the fourth input transistor 1014, and the first terminal of the fourth positive feedback transistor 1048 is connected to the first terminal of the third input transistor 1013. The second terminal of the fourth positive feedback transistor 1048 is connected to the second terminal of the third input transistor 1013, and the second terminal of the fourth positive feedback transistor 1048 is also connected to the first terminal of the sixth input transistor 1016.

[0145] In one embodiment, the first positive feedback transistor 1045, the second positive feedback transistor 1046, the first input transistor 1011, and the second input transistor 1012 are of the same type, ensuring that the voltage at the output end of the input circuit 101 pulled by the two positive feedback transistors and the voltage at the output end of the input circuit 101 pulled by the two input transistors are in the same direction, thereby achieving positive feedback.

[0146] When the voltage at the first end of the first input transistor 1011 is larger, the ability of the first positive feedback transistor 1045 to pull up the voltage at the first end of the second input transistor 1012 is smaller, and the voltage at the first end of the second input transistor 1012 rises more slowly, thereby realizing a positive feedback mechanism and accelerating the difference in the differential voltage between the first input transistor 1011 and the second input transistor 1012.

[0147] In one embodiment, the third positive feedback transistor 1047, the fourth positive feedback transistor 1048, the third input transistor 1013, and the fourth input transistor 1014 are of the same type, ensuring that the voltage at the output end of the input circuit 101 pulled by the two positive feedback transistors and the voltage at the output end of the input circuit 101 pulled by the two input transistors are in the same direction, thereby achieving positive feedback.

[0148] The greater the voltage at the first end of the first input transistor 1011, the greater the ability of the third positive feedback transistor 1047 to pull down the voltage at the first end of the second input transistor 1012, and the faster the voltage at the first end of the second input transistor 1012 drops, thereby realizing a positive feedback mechanism and accelerating the difference in the differential voltage between the first input transistor 1011 and the second input transistor 1012.

[0149] In one embodiment, the comparator further includes a first reset circuit 1031, which is connected between the first output terminal VN of the input circuit 101 and the second output terminal VP of the input circuit 101. The first reset circuit 1031 is used to reset the voltage of the first output terminal VN of the input circuit 101 and the voltage of the second output terminal VP of the input circuit 101.

[0150] Among them, the first reset circuit 1031 includes a first clocked transistor 1034 and a second clocked transistor 1035, the second end of the first clocked transistor 1034 is connected to the first output end VN of the input circuit 101, the second end of the second clocked transistor 1035 is connected to the second output end VP of the input circuit 101, and the first end of the second clocked transistor 1035 is connected to the first end of the first clocked transistor 1034 and then connected to the power supply.

[0151] The control terminals of the first clock-controlled transistor 1034 and the second clock-controlled transistor 1035 are both used to receive a clock signal, and are turned on when the clock signal is at a low level, pulling the first output terminal VN and the second output terminal VP of the input circuit 101 to a high level.

[0152] In one embodiment, the comparator further includes a second reset circuit 1032 and a third reset circuit 1033. The second reset circuit 1032 is connected to the first output terminal ON of the output circuit 102, and the third reset circuit 1033 is connected to the second output terminal OP of the output circuit 102. The second reset circuit 1032 is used to reset the voltage of the first output terminal ON of the output circuit 102. The third reset circuit 1033 is used to reset the voltage of the second output terminal OP of the output circuit 102.

[0153] The second reset circuit 1032 includes a third clock-controlled transistor 1036, wherein a second terminal of the third clock-controlled transistor 1036 is connected to the first output terminal ON of the output circuit 102. A control terminal of the third clock-controlled transistor 1036 is configured to receive a clock signal and to pull the first output terminal ON of the output circuit 102 to a high level when the clock signal is at a low level.

[0154] The third reset circuit 1033 includes a fourth clocked transistor 1037, a second terminal of which is connected to the second output terminal OP of the output circuit 102. A control terminal of the fourth clocked transistor 1037 is used to receive a clock signal and to pull the second output terminal OP of the output circuit 102 to a high level when the clock signal is at a low level.

[0155] Compared with the reset achieved by the second reset circuit 1032 and the third reset circuit 1033 pulling the voltage of the two output terminals of the input circuit 101 through the output circuit 102, the reset is achieved by setting the first reset circuit 1031 to directly pull the voltage of the two output terminals of the input circuit 101, and the reset time is shorter, thereby improving the response rate of the comparator.

[0156] In one embodiment, the first clocked transistor 1034 , the second clocked transistor 1035 , the third clocked transistor 1036 and the fourth clocked transistor 1037 are of the same type to pull the two output terminals of the input circuit 101 and the two output terminals of the output circuit 102 to the same level.

[0157] In one embodiment, when the first positive feedback transistor 1045 , the second positive feedback transistor 1046 , the first input transistor 1011 and the second input transistor 1012 are all P-type transistors, the source of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal.

[0158] In one embodiment, when the third positive feedback transistor 1047 , the fourth positive feedback transistor 1048 , the third input transistor 1013 and the fourth input transistor 1014 are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal.

[0159] In one embodiment, when the first output transistor 1021 and the second output transistor 1022 are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0160] When the third output transistor 1023 and the fourth output transistor 1024 are both P-type transistors, and the first to fourth clocked transistors 1034 to 103 are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0161] In one embodiment, the first positive feedback transistor 1045 and the second positive feedback transistor 1046 have the same size, the first input transistor 1011 and the second input transistor 1012 have the same size, and the size of the first positive feedback transistor 1045 is less than half the size of the first input transistor 1011, so as to prevent the first positive feedback transistor 1045 and the second positive feedback transistor 1046 from affecting the first input transistor 1011 and the second input transistor 1012 in sensing the input signal and the reference signal, thereby improving the accuracy of the comparator output result.

[0162] In one embodiment, the third positive feedback transistor 1047 and the fourth positive feedback transistor 1048 have the same size, the third input transistor 1013 and the fourth input transistor 1014 have the same size, and the size of the third positive feedback transistor 1047 is less than half the size of the third input transistor 1013, so as to prevent the third positive feedback transistor 1047 and the fourth positive feedback transistor 1048 from affecting the sensing of the input signal and the reference signal by the third input transistor 1013 and the fourth input transistor 1014, thereby improving the accuracy of the comparator output result.

[0163] The following describes the four working stages of the comparator. Figure 5 The working process of the comparator shown is:

[0164] During the reset phase, the clock signal is at a low level, the fifth input transistor P3 and the sixth input transistor N3 are turned off, the input circuit 101 and the output circuit 102 stop operating, the first clocked transistor P10 and the second clocked transistor P11 are turned on, the first reset circuit 1031 operates, and the voltages at the first output terminal ON and the second output terminal OP of the input circuit 101 are pulled up to a high level. The third clocked transistor P6 and the fourth clocked transistor P7 are turned on, the second reset circuit 1032 and the third reset circuit 1033 operate, pulling the drain voltages of the third output transistor P4 and the drain voltage of the fourth output transistor P4 to a high level.

[0165] During the sampling phase, the clock signal is at a high level, the first clocked transistor P10, the second clocked transistor P11, the third clocked transistor P6, and the fourth clocked transistor P7 are turned off, and the first reset circuit 1031 to the third reset circuit 1033 stop operating. The fifth input transistor P3 and the sixth input transistor N3 are turned on, and the input circuit 101 and the output circuit 102 operate.

[0166] The reference signal can vary from 0 to VDD, where VDD represents the voltage at the power supply terminal. The second input transistor P2 and / or the fourth input transistor N2 are controlled to be turned on by setting the magnitude of the reference signal. The following description uses reference signals of 0.3V, 0.5V, and 0.8V.

[0167] In the first case, the reference signal can only turn on the second input transistor P2 , for example, the power supply terminal is 1.2V and the reference signal is 0.3V.

[0168] When the input signal can only turn on the first input transistor P1, for example, the input signal is 0.1V, the input signal is smaller than the reference signal, the pull-up capability of the first input transistor P1 is higher than the pull-up capability of the second input transistor P2, and the voltage at the first output terminal VN of the input circuit is slightly higher than the voltage at the second output terminal VP of the input circuit.

[0169] When the input signal can only turn on the first input transistor P1, for example, the input signal is 0.4V, the input signal is greater than the reference signal, the pull-up capability of the first input transistor P1 is lower than the pull-up capability of the second input transistor P2, and the voltage at the first output terminal VN of the input circuit is slightly lower than the voltage at the second output terminal VP of the input circuit.

[0170] When the input signal can turn on both the first input transistor P1 and the third input transistor N1, for example, the input signal is 0.6V and is greater than the reference signal, the pull-up capability of the first input transistor P1 is lower than the pull-up capability of the second input transistor P2, and the third input transistor N1 is also pulled down. The voltage at the first output terminal VN of the input circuit is lower than the voltage at the second output terminal VP of the input circuit.

[0171] When the input signal turns on only the third input transistor N1, for example, the input signal is 0.8V and is greater than the reference signal, the third input transistor N1 pulls down the voltage of the first output terminal VN of the input circuit, and the second input transistor P2 pulls up the voltage of the second output terminal VP of the input circuit, and the voltage of the first output terminal VN of the input circuit is less than the voltage of the second output terminal VP of the input circuit.

[0172] When the voltage of the first output terminal VN of the input circuit is less than the voltage of the second output terminal VP of the input circuit, under the control of the first output terminal VN, the ability of the first positive feedback transistor P8 to pull up the voltage of the second output terminal of the input circuit 101 is higher than the ability of the second positive feedback transistor P9 to pull up the voltage of the first output terminal of the input circuit 101, that is, the voltage rise rate of the first output terminal of the input circuit 101 is lower than the voltage fall rate of the second output terminal of the input circuit 101.

[0173] Under the control of the first output terminal VN, the ability of the third positive feedback transistor N6 to pull down the voltage of the second output terminal of the input circuit 101 is lower than the ability of the fourth positive feedback transistor N7 to pull down the voltage of the first output terminal of the input circuit 101, that is, the voltage drop rate of the first output terminal of the input circuit 101 is higher than the voltage drop rate of the second output terminal of the input circuit 101.

[0174] When the voltage of the first output terminal VN of the input circuit is greater than the voltage of the second output terminal VP of the input circuit, under the control of the first output terminal VN, the ability of the first positive feedback transistor P8 to pull up the voltage of the second output terminal of the input circuit 101 is lower than the ability of the second positive feedback transistor P9 to pull up the voltage of the first output terminal of the input circuit 101, that is, the voltage rise rate of the first output terminal of the input circuit 101 is higher than the voltage fall rate of the second output terminal of the input circuit 101.

[0175] Under the control of the first output terminal VN, the ability of the third positive feedback transistor N6 to pull down the voltage of the second output terminal of the input circuit 101 is higher than the ability of the fourth positive feedback transistor N7 to pull down the voltage of the first output terminal of the input circuit 101, that is, the voltage drop rate of the first output terminal of the input circuit 101 is lower than the voltage drop rate of the second output terminal of the input circuit 101.

[0176] In the second case, the reference signal turns on the second input transistor P2 and the fourth input transistor N2, and balances the pull-up capability of the second input transistor P2 and the pull-down capability of the fourth input transistor N2. For example, the power supply terminal is 1.2V and the reference signal is 0.5V.

[0177] When the input signal turns on only the first input transistor P1, for example, the input signal is 0.2V and is smaller than the reference signal, the pull-up capability of the first input transistor P1 is greater than that of the second input transistor P2, and the fourth input transistor N2 also pulls down, causing the voltage at the first output terminal VN of the input circuit to be greater than the voltage at the second output terminal VP of the input circuit.

[0178] When the input signal turns on both the first input transistor P1 and the third input transistor N1, for example, the input signal is 0.4V and is smaller than the reference signal, the pull-down capabilities of the first input transistor P1 and the third input transistor N1 are unbalanced, and the pull-up capability of the first input transistor P1 is stronger than the pull-down capability of the third input transistor N1, causing the voltage at the first output terminal VN of the input circuit to be slightly higher than the voltage at the second output terminal VP of the input circuit.

[0179] When the input signal turns on both the first input transistor P1 and the third input transistor N1, for example, the input signal is 0.6V and is greater than the reference signal, the pull-down capabilities of the first input transistor P1 and the third input transistor N1 are unbalanced, and the pull-up capability of the first input transistor P1 is weaker than the pull-down capability of the third input transistor N1, causing the voltage at the first output terminal VN of the input circuit to be slightly lower than the voltage at the second output terminal VP of the input circuit.

[0180] When the input signal can only turn on the third input transistor N1, for example, the input signal is 0.8V and is greater than the reference signal, the pull-down capability of the third input transistor N1 is greater than that of the fourth input transistor N2. The second input transistor P2 also pulls up the voltage of the second output terminal of the input circuit, causing the voltage of the first output terminal VN of the input circuit to be lower than the voltage of the second output terminal VP of the input circuit.

[0181] The positive feedback process has been explained in the first case and will not be repeated here.

[0182] In the third case, the reference signal can only turn on the fourth input transistor N2 , for example, the power supply terminal is 1.2V and the reference signal is 0.8V.

[0183] When the input signal can only turn on the first input transistor P1, for example: the input signal is 0.1V, the input signal is less than the reference signal, the first input transistor P1 pulls up the voltage of the first output terminal VN of the input circuit, and the fourth input transistor N2 pulls down the voltage of the second output terminal VP of the input circuit, and the voltage of the first output terminal VN of the input circuit is greater than the voltage of the second output terminal VP of the input circuit.

[0184] When the input signal can turn on both the first input transistor P1 and the third input transistor N1, for example, the input signal is 0.6V and is less than the reference signal, the pull-down capability of the third input transistor N1 is lower than that of the fourth input transistor N2. The first input transistor P1 also pulls up the voltage of the first output terminal of the input circuit, and the voltage of the first output terminal VN of the input circuit is greater than the voltage of the second output terminal VP of the input circuit.

[0185] When the input signal turns on only the third input transistor N1, for example, the input signal is 0.7 V and is smaller than the reference signal, the ability of the third input transistor N1 to pull down the voltage of the first output terminal VN of the input circuit is lower than the ability of the fourth input transistor N2 to pull down the voltage of the second output terminal VP of the input circuit, and the voltage of the first output terminal VN of the input circuit is higher than the voltage of the second output terminal VP of the input circuit.

[0186] When the input signal turns on only the third input transistor N1, for example, the input signal is 0.9 V and is smaller than the reference signal, the ability of the third input transistor N1 to pull down the voltage of the first output terminal VN of the input circuit is greater than the ability of the fourth input transistor N2 to pull down the voltage of the second output terminal VP of the input circuit, and the voltage of the first output terminal VN of the input circuit is lower than the voltage of the second output terminal VP of the input circuit.

[0187] The positive feedback process has been explained in the first case and will not be repeated here.

[0188] During the regeneration phase, due to the pull-down effect of the input circuit, the drain voltage of the first output transistor 1021 and the drain voltage of the second output transistor 1022 reach the flip voltage. If the voltage of the first output terminal VN of the input circuit is higher than the voltage of the second output terminal VP of the input circuit, the first output transistor 1021 and the fourth output transistor 1024 are gradually disconnected, and the second output transistor 1022 and the third output transistor 1023 are gradually turned on, thereby increasing the ability to pull down the drain voltage of the fourth output transistor 1024 and increasing the ability to pull up the drain voltage of the third output transistor 1023.

[0189] In the decision stage, the first output transistor 1021 and the fourth output transistor 1024 are disconnected, and the second output transistor 1022 and the third output transistor 1023 are turned on, continuing to pull down the drain voltage of the fourth output transistor 1024 and pull up the drain voltage of the third output transistor 1023. After pulling the drain of the fourth output transistor 1024 to a high level and pulling the drain voltage of the third output transistor 1023 to a low level, the drain voltages of the third output transistor 1023 and the fourth output transistor 1024 are maintained.

[0190] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the third output transistor 1023 and the fourth output transistor 1024 are reset to a high level by the third clock-controlled transistor 1036 and the fourth clock-controlled transistor 103 .

[0191] In the above technical solution, two groups of input transistors of different types receive input signals and reference signals, and two groups of feedback transistors of different types perform positive feedback. When the reference signal changes from 0V to VDD, the sizes of the input signal and the reference signal can also be accurately sensed to achieve rail-to-rail detection.

[0192] Figure 6 A specific circuit diagram of a comparator is provided for the present application. The comparator includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0193] The input circuit 101 includes a first input transistor 1011, a second input transistor 1012, a third input transistor 1013, a fourth input transistor 1014, a fifth input transistor 1015, and a sixth input transistor 1016. The connection relationship between the first input transistor 1011 to the sixth input transistor 1016 is the same as Figure 5 The embodiments shown are the same and will not be described again here.

[0194] The output circuit 102 includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023, and a fourth output transistor 1024. The connection relationship between the first output transistor 1021 to the fourth output transistor 1024 is the same as Figure 5 The embodiments shown are the same and will not be described again here.

[0195] It should be noted that when the first output transistor 1021 and the second output transistor 1022 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. When the third output transistor 1023 and the fourth output transistor 1024 are N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0196] The positive feedback circuit 104 includes a first positive feedback module 1040 and a second positive feedback module 1049. The first positive feedback module 1040 includes a first positive feedback unit 1041 and a second positive feedback unit 1042. The second positive feedback module 1049 includes a third positive feedback unit 1043 and a fourth positive feedback unit 1044. The connection relationship between the first positive feedback unit 1041 and the second positive feedback unit 1042 is the same as Figure 5 Similarly, the second positive feedback module 1049 includes a third positive feedback unit 1043 and a fourth positive feedback unit 1044. Figure 5The same is not repeated here. The first positive feedback unit 1041 includes a first positive feedback transistor 1045, and the second positive feedback unit 1042 includes a second positive feedback transistor 1046. The third positive feedback unit 1043 includes a third positive feedback transistor 1047, and the fourth positive feedback unit 1044 includes a fourth positive feedback transistor 1048. The connection relationship between the first positive feedback transistor 1045 to the fourth positive feedback transistor 1048 is the same. Figure 5 The same, no further description here.

[0197] The connection relationship between the transistors in the input circuit 101, the transistors in the output circuit 102, and the transistors in the positive feedback circuit 104 has been described in detail in the embodiment shown in the figure and will not be repeated here.

[0198] The comparator further includes a first reset circuit 1031, a second reset circuit 1032, and a third reset circuit 1033. The first reset circuit 1031 includes a first clock-controlled transistor 1034 and a second clock-controlled transistor 1035. The connection relationship between the first clock-controlled transistor 1034 and the second clock-controlled transistor 1035 is the same as Figure 5 The same, no further description here.

[0199] The second reset circuit 1032 includes a third clock-controlled transistor 1036. The third clock-controlled transistor 1036 has the same connection relationship with the transistors in the output circuit 102. Figure 5 The third reset circuit 1033 includes a fourth clock-controlled transistor 1037, and the connection relationship between the fourth clock-controlled transistor 1037 and the transistor in the output circuit 102 is the same as Figure 5 The same, no further description here.

[0200] It should be noted that when the first clocked transistor 1034 to the fourth clocked transistor 1037 are N-type transistors, the drain of the N-type transistor is the second end, the gate of the N-type transistor is the control end, the source of the N-type transistor is the first end, and the source of the N-type transistor is grounded.

[0201] The following describes the working process of the comparator shown in the figure in combination with the four working stages of the comparator:

[0202] During the reset phase, the clock signal is at a low level, the control terminal of the fifth input transistor P3 is at a high level, and the control terminal of the sixth input transistor P6 is at a low level. The fifth input transistor P3 and the sixth input transistor P6 are disconnected, and the input circuit 101 and the output circuit 102 stop operating. The control terminals of the first clocked transistor N10 and the second clocked transistor N11 are at a high level, turning on the first clocked transistor N10 and the second clocked transistor N11. The first reset circuit 1031 operates, and the voltages of the first output terminal ON and the second output terminal OP of the input circuit 101 are pulled down to a low level. The control terminals of the third clocked transistor N6 and the fourth clocked transistor N7 are also at a high level, turning on the third clocked transistor N6 and the fourth clocked transistor N7. The second reset circuit 1032 and the third reset circuit 1033 operate, pulling the drain voltages of the third output transistor N5 and the fourth output transistor N6 to a low level.

[0203] During the sampling phase and Figure 5 The description of the embodiment of the comparator shown is the same as that in the embodiment of the comparator, and will not be repeated here.

[0204] During the regeneration phase, since the two output terminals of the input circuit have pull-up capability, the drain voltage of the first output transistor P4 and the drain voltage of the second output transistor P5 reach the flip voltage. When the drain voltage of the first input transistor P4 is higher than the drain voltage of the second input transistor P5, the first output transistor P4 and the fourth output transistor N5 are closed, and the second output transistor P5 and the third output transistor N4 are disconnected, pulling down the drain voltage of the fourth output transistor N5 and pulling up the drain voltage of the third output transistor N4.

[0205] In the decision stage, the first output transistor P4 and the fourth output transistor N5 are closed, the second output transistor P5 and the third output transistor N4 are disconnected, and the drain voltage of the third output transistor N4 continues to be pulled up, and the drain voltage of the fourth output transistor N5 is pulled down. After the drain of the third output transistor N4 is pulled to a high level and the drain voltage of the fourth output transistor N5 is pulled to a low level, the drain voltages of the third output transistor N4 and the fourth output transistor N5 are maintained.

[0206] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the third output transistor N4 and the fourth output transistor N5 are reset to a low level by the third clock-controlled transistor N4 and the fourth clock-controlled transistor N5.

[0207] In the above technical solution, two groups of input transistors of different types receive input signals and reference signals, and two groups of feedback transistors of different types perform positive feedback. When the reference signal changes from 0V to VDD, the sizes of the input signal and the reference signal can also be accurately sensed to achieve rail-to-rail detection.

[0208] Figure 7 A structural block diagram of a comparator provided in this application is shown in FIG. Figure 7 As shown, the comparator includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0209] The input circuit 101 has two output terminals, denoted as a first output terminal VN and a second output terminal VP. The positive feedback circuit 104 includes a first controllable positive feedback module 21 and a second controllable positive feedback module 22 .

[0210] The first controllable positive feedback module 21 includes at least one first controllable positive feedback submodule 23, wherein each first controllable positive feedback submodule 23 includes a first positive feedback unit 1041, a second positive feedback unit 1042, a first switch 1001, and a second switch 1002. The first positive feedback unit 1041 and the second positive feedback unit 1042 are each provided with a control terminal and a first terminal.

[0211] The control end of the first positive feedback unit 1041 is connected to the first output end VN of the input circuit 101 via the first switch 1001, and the first end of the first positive feedback unit 1041 is connected to the second output end VP of the input circuit 101. The control end of the second positive feedback unit 1042 is connected to the second output end VP of the input circuit 101 via the second switch 1002, and the first end of the second positive feedback unit 1042 is connected to the first output end VN of the input circuit 101.

[0212] The first positive feedback unit 1041 is configured to increase the voltage of the second output terminal VP of the input circuit based on the voltage of the first output terminal VN of the input circuit under the control of the first switch 1001. The second positive feedback unit 1042 is configured to increase the voltage of the first output terminal VN of the input circuit based on the voltage of the second output terminal VP of the input circuit under the control of the second switch 1002. By controlling the closing and opening of the first and second switches 1001, 1002, it is possible to control whether the first controllable positive feedback submodule generates positive feedback. When both the first and second switches 1001, 1002 are closed, the first controllable positive feedback submodule 23 can accelerate the difference between the differential signals at the output terminals of the input circuit 101 through a positive feedback mechanism. When both the first and second switches 1001, 1002 are open, the first controllable positive feedback submodule 23 is disconnected from the input circuit 101, and no positive feedback mechanism can be generated at the output terminals of the input circuit 101.

[0213] The second controllable positive feedback module 22 includes at least one second controllable positive feedback submodule 24, wherein each second controllable positive feedback submodule 24 includes a third positive feedback unit 1043, a fourth positive feedback unit 1044, a third switch 1003, and a fourth switch 1004. The third positive feedback unit 1043 and the fourth positive feedback unit 1044 each have a control terminal and a first terminal.

[0214] The control terminal of the third positive feedback unit 1043 is connected to the first output terminal VN of the input circuit 101 via the third switch 1003, and the first terminal of the third positive feedback unit 1043 is connected to the second output terminal VP of the input circuit 101. The control terminal of the fourth positive feedback unit 1044 is connected to the second output terminal VP of the input circuit 101 via the third switch 1004, and the first terminal of the fourth positive feedback unit 1044 is connected to the first output terminal VN of the input circuit 101.

[0215] The third positive feedback unit 1043 is configured to pull down the voltage of the second output terminal VP of the input circuit based on the voltage of the first output terminal VN of the input circuit under the control of the third switch 1003. The fourth positive feedback unit 1044 is configured to pull down the voltage of the first output terminal VN of the input circuit based on the voltage of the second output terminal VP of the input circuit under the control of the fourth switch 1004. By controlling the closing and opening of the third and fourth switches 1003 and 1004, it is possible to control whether the second controllable positive feedback submodule 23 generates positive feedback. When both the third and fourth switches 1003 and 1004 are closed, the second controllable positive feedback submodule 23 can accelerate the difference between the differential signals at the output terminals of the input circuit 101 through a positive feedback mechanism. When both the third and fourth switches 1003 and 1004 are open, the second controllable positive feedback submodule 23 is disconnected from the input circuit 101, and the positive feedback mechanism cannot be generated at the output terminals of the input circuit 101.

[0216] When the comparator is operating, the number of the first controllable positive feedback submodule 23 and the second controllable positive feedback submodule 24 generating positive feedback can be controlled, thereby controlling the ability of the first controllable positive feedback module 21 and the second controllable positive feedback module 22 to increase the difference between the differential signals. This, on the one hand, controls the time the comparator is in the sampling phase, ensuring the comparator's response rate. On the other hand, it also balances the ability of the positive feedback circuit 104 to increase the voltage at the output of the input circuit 101 with the ability of the input signal and the reference signal to increase the voltage at the output of the input circuit 101, ensuring that the comparator can accurately output a comparison result based on the input signal and the reference signal.

[0217] Figure 8 、 Figure 9 and Figure 10 Based on Figure 7 FIG1 is a circuit diagram of a comparator shown in FIG1 , wherein the structures of the input circuit 101 and the output circuit 102 are the same as those of the comparator shown in FIG1 , and are not described in detail here. The comparator also includes a first reset circuit 1031, a second reset circuit 1032, and a third reset circuit 1033. These three reset circuits have been described in detail in the embodiment shown in FIG1 , and are not described in detail here.

[0218] The following combination Figure 9 The specific circuit structure of each first controllable positive feedback submodule 23 in the positive feedback circuit 104 is described. The first positive feedback unit 1041 includes a first positive feedback transistor 1045. The control terminal of the first positive feedback transistor 1045 serves as the control terminal of the first positive feedback unit 1041, and the second terminal of the first positive feedback transistor 1045 serves as the first terminal of the first positive feedback unit.

[0219] The control terminal of the first positive feedback transistor 1045 is connected to the second terminal of the first input transistor 1011 via the first switch 1001. The second terminal of the first positive feedback transistor 1045 is connected to the second terminal of the second input transistor 1012. The first switch 1001 includes a first transmission gate G1, which is controlled by a first enable signal EN1. The first enable signal EN1 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and a test mode signal.

[0220] The second positive feedback unit 1042 includes a second positive feedback transistor 1046 . The control terminal of the second positive feedback transistor 1046 is the control terminal of the second positive feedback unit 1042 . The second terminal of the second positive feedback transistor 1046 is the first terminal of the second positive feedback unit 1042 .

[0221] The control terminal of the second positive feedback transistor 1046 is connected to the second terminal of the second input transistor 1012 via the second switch 1002. The second terminal of the second positive feedback transistor 1046 is connected to the second terminal of the first input transistor 1011. The second switch 1002 includes a second transmission gate G2, which is controlled by a second enable signal EN2. The second enable signal EN2 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0222] The switch states of the first transmission gate G1 and the second transmission gate G2 are controlled by the enable signal, thereby controlling whether the first positive feedback transistor 1045 and the second positive feedback transistor 1046 provide a positive feedback mechanism, thereby adjusting the number of first controllable positive feedback submodules participating in the positive feedback.

[0223] In one embodiment, the first controllable positive feedback submodule 23 further includes a first zero switch 201 and a zeroth zero switch 202. The control terminal of the first positive feedback unit 1041 is further connected to the power supply terminal via the first zero switch 201. The first zero switch 201 is configured to be turned on when the first transmission gate G1 is closed, thereby preventing the transistor in the first positive feedback unit 1041 from floating, thereby reducing interference from external interference on the comparator. The control terminal of the second positive feedback unit 1042 is further connected to the power supply terminal via the zeroth zero switch 202. The zeroth zero switch 202 is configured to be turned on when the second transmission gate G2 is closed, thereby preventing the transistor in the second positive feedback unit 1042 from floating, thereby reducing interference from external interference on the comparator.

[0224] The following combination Figure 10 The specific circuit structure of each second controllable positive feedback submodule 24 in the positive feedback circuit 104 is described. The third positive feedback unit 1043 includes a third positive feedback transistor 1047. The control terminal of the third positive feedback transistor 1047 serves as the control terminal of the third positive feedback unit 1043, and the first terminal of the third positive feedback transistor 1047 serves as the first terminal of the third positive feedback unit 1043.

[0225] The control terminal of the third positive feedback transistor 1047 is connected to the first terminal of the third input transistor 1013 via the third switch 1003. The first terminal of the third positive feedback transistor 1047 is connected to the first terminal of the second input transistor 1012. The third switch 1003 includes a third transmission gate G3, which is controlled by a third enable signal EN3. The third enable signal EN3 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0226] The fourth positive feedback unit 1048 includes a fourth positive feedback transistor 1048 , a control terminal of the fourth positive feedback transistor 1048 is the control terminal of the fourth positive feedback unit 1044 , and a first terminal of the fourth positive feedback transistor 1048 is the first terminal of the fourth positive feedback unit 1044 .

[0227] A control terminal of the fourth positive feedback transistor 1048 is connected to a first terminal of the fourth input transistor 1014 via a fourth switch 1004. A first terminal of the fourth positive feedback transistor 1048 is connected to a first terminal of the first input transistor 1011. The fourth switch 1004 includes a fourth transmission gate G4. The second transmission gate G4 is controlled by a second enable signal EN4. The second enable signal EN4 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and a test mode signal.

[0228] The enable signal controls the switching states of the third transmission gate G3 and the fourth transmission gate G4, thereby controlling whether the third positive feedback transistor 1047 and the fourth positive feedback transistor 1048 provide a positive feedback mechanism, thereby adjusting the number of second controllable positive feedback submodules participating in the positive feedback.

[0229] In one embodiment, the second controllable positive feedback submodule 24 further includes a zeroth switch 203 and a first-first switch 204. The control terminal of the third positive feedback unit 1041 is further connected to the ground terminal via the zeroth switch 203. The zeroth switch 203 is configured to be turned on when the third transmission gate G3 is closed, thereby preventing the transistor in the third positive feedback unit 1043 from floating, thereby reducing interference from external interference on the comparator. The control terminal of the third positive feedback unit 1043 is further connected to the ground terminal via the first-first switch 204. The first-first switch 204 is configured to be turned on when the fourth transmission gate G4 is closed, thereby preventing the transistor in the fourth positive feedback unit 1044 from floating, thereby reducing interference from external interference on the comparator.

[0230] In one embodiment, the first zero switch 201 and the zeroth zero switch 202 are P-type transistors, the first end of the first zero switch 201 is connected to the control end of the first positive feedback transistor 1045, the first end of the zeroth zero switch 202 is connected to the control end of the second positive feedback transistor 1046, and the second ends of the first zero switch 201 and the zeroth zero switch 202 are connected to the power supply end, so as to pull the first positive feedback transistor 1045 to a high level when the first transmission gate G1 is closed, and pull the second positive feedback transistor 1046 to a high level when the second transmission gate G2 is closed.

[0231] In one embodiment, the zeroth switch 203 and the first switch 204 are N-type transistors, wherein the drain of the N-type transistor is a first terminal, the source of the N-type transistor is a second terminal, and the gate of the N-type transistor is a control terminal. The first terminal of the first zero switch 203 is connected to the control terminal of the third positive feedback transistor 1047, the first terminal of the zeroth zero switch 204 is connected to the control terminal of the fourth positive feedback transistor 1048, and the second terminals of the first zero switch 203 and the zeroth zero switch 204 are connected to ground, so as to pull the third positive feedback transistor 1047 to a low level when the third transmission gate G3 is closed, and pull the fourth positive feedback transistor 1048 to a low level when the fourth transmission gate G4 is closed.

[0232] Figure 11 based on Figure 7 One of the specific circuit diagrams of the comparator shown in FIG. 1 , wherein the structures of the input circuit 101 and the output circuit 102 are the same Figure 6 The comparator shown is the same and will not be described again here. Figure 9 and Figure 10 The circuit shown is the same and will not be described again this time.

[0233] In the above embodiment, the positive feedback circuit 104 includes multiple first controllable positive feedback sub-modules and multiple second controllable positive feedback sub-modules. By controlling the number of controllable positive feedback sub-modules that provide the positive feedback mechanism, the ability of the positive feedback circuit 104 to pull the voltage of the two output terminals of the input circuit 101 is adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the positive feedback circuit 104 and the input signal and reference signal on the output terminal of the input circuit 101, thereby improving the response rate and accuracy of the comparator.

[0234] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0235] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A comparator, characterized in that: include: an input circuit, comprising a first pair of transistors and a second pair of transistors, wherein the first pair of transistors and the second pair of transistors both receive an input signal and a reference signal, and are configured to generate a differential signal according to the input signal and the reference signal during a sampling phase, wherein the first pair of transistors and the second pair of transistors have different transistor types; an output circuit connected to the output terminal of the input circuit, and configured to amplify and latch the voltage signal at the output terminal of the input circuit in a regeneration phase to output a comparison result; The comparator further includes: a positive feedback circuit connected to the output terminal of the input circuit and configured to accelerate the difference between the differential signals; The positive feedback circuit comprises: A first positive feedback module is connected to the output end of the input circuit and is used to pull the voltage of the output end of the input circuit to accelerate the difference between the differential signals; A second positive feedback module is connected to the output end of the input circuit and is used to pull the voltage of the output end of the input circuit to accelerate the difference between the differential signals; The first positive feedback module includes at least one first controllable positive feedback submodule, and each first controllable positive feedback submodule includes: a first positive feedback unit, having a control end connected to the first output end of the input circuit via a first switch, and a first end connected to the second output end of the input circuit, for pulling the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit under the control of the first switch; a second positive feedback unit, a control end of which is connected to the second output end of the input circuit via a second switch, and a first end of which is connected to the first output end of the input circuit, for pulling the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit under the control of the second switch; The second positive feedback module includes at least one second controllable positive feedback submodule, and each first controllable positive feedback submodule includes: a third positive feedback unit, whose control end is connected to the first output end of the input circuit through a third switch, and whose first end is connected to the second output end of the input circuit, and is used to pull the voltage of the second output end of the input circuit according to the voltage of the first output end of the input circuit under the control of the third switch; A fourth positive feedback unit, whose control end is connected to the second output end of the input circuit through a fourth switch, and whose first end is connected to the first output end of the input circuit, is used to pull the voltage of the first output end of the input circuit according to the voltage of the second output end of the input circuit under the control of the fourth switch.

2. The comparator according to claim 1, wherein: The first positive feedback unit includes: a first positive feedback transistor, a control terminal of which is the input terminal of the first positive feedback unit, and a second terminal of which is the first terminal of the first positive feedback unit; The second positive feedback unit includes: a second positive feedback transistor, a control terminal of which is the input terminal of the second positive feedback unit, and a second terminal of which is the first terminal of the second positive feedback unit; The third positive feedback unit includes: a third positive feedback transistor, a control end of which is the input end of the third positive feedback unit, and a first end of which is the first end of the third positive feedback unit; The fourth positive feedback unit includes: a fourth positive feedback transistor, a control end of which is the input end of the fourth positive feedback unit, and a first end of which is the first end of the fourth positive feedback unit.

3. The comparator according to claim 2, wherein: The input circuit comprises: a first input transistor, whose control terminal is used to receive the input signal, whose second terminal serves as the first output terminal of the input circuit, and whose first terminal is connected to the first terminal of the first positive feedback transistor; a second input transistor, whose control terminal is used to receive the reference signal, whose second terminal serves as the second output terminal of the input circuit, and whose first terminal is connected to the first terminal of the second positive feedback transistor; a third input transistor, whose control terminal is used to receive the input signal, whose first terminal serves as the first output terminal of the input circuit, and whose second terminal is connected to the second terminal of the third positive feedback transistor; A fourth input transistor has a control terminal for receiving the reference signal, a first terminal serving as the second output terminal of the input circuit, and a second terminal connected to the second terminal of the fourth positive feedback transistor.

4. The comparator according to claim 3, wherein: The input circuit further includes: a fifth input transistor, having a control end for receiving a clock signal, a second end connected to the first end of the first input transistor, the first end of the second input transistor, the first end of the first positive feedback transistor, and the first end of the second positive feedback transistor, and a first end connected to a power supply end; A sixth input transistor, whose control end is used to receive a clock signal, whose first end is connected to the second end of the third input transistor, the second end of the fourth input transistor, the second end of the third positive feedback transistor, and the second end of the fourth positive feedback transistor, and whose second end is connected to the ground end.

5. The comparator according to claim 3, wherein: The first positive feedback transistor, the second positive feedback transistor, the first input transistor and the second input transistor are of the same type; The third positive feedback transistor, the fourth positive feedback transistor, the third input transistor, and the fourth input transistor are of the same type.

6. The comparator according to claim 3, wherein: The first positive feedback transistor, the second positive feedback transistor, the first input transistor, and the second input transistor are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; The third positive feedback transistor, the fourth positive feedback transistor, the third input transistor and the fourth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

7. The comparator according to claim 1, wherein: The comparator further includes: The first reset circuit is connected between the first output terminal of the input circuit and the second output terminal of the input circuit, and is used for resetting the voltage of the first output terminal of the input circuit and the voltage of the second output terminal of the input circuit.

8. The comparator according to claim 7, wherein: The comparator further includes: a second reset circuit connected to the first output terminal of the output circuit, for resetting the voltage of the first output terminal of the output circuit; The third reset circuit is connected to the second output terminal of the output circuit and is used to reset the voltage of the second output terminal of the output circuit.

9. The comparator according to claim 7, wherein: The first reset circuit includes: a first clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to the first output terminal of the input circuit; A second clock-controlled transistor has a control end receiving a clock signal, a second end connected to the second output end of the input circuit, and a first end connected to the first end of the first clock-controlled transistor.

10. The comparator according to claim 8, wherein: The second reset circuit includes: a third clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to the first output terminal of the output circuit; The third reset circuit includes: a fourth clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the second output terminal of the output circuit.

11. The comparator according to claim 8 or 10, characterized in that: The first clocked transistor, the second clocked transistor, the third clocked transistor and the fourth clocked transistor are of the same type.

12. The comparator according to claim 3, wherein: The output circuit includes: a first output transistor, a second terminal of which is a first input terminal of the output circuit; a second output transistor, a second terminal of which is a second input terminal of the output circuit; a third output transistor, having a control end connected to the control end of the first output transistor, a control end further connected to the second end of the fourth output transistor, a second end connected to the first end of the first output transistor, and the second end of the third output transistor serving as the first output end of the output circuit; A fourth output transistor, whose control end is connected to the control end of the second output transistor, and whose control end is also connected to the second end of the third output transistor, and whose second end is connected to the first end of the second output transistor, and the second end of the fourth output transistor serves as the second output end of the output circuit.

13. The comparator according to claim 12, wherein: The first output transistor and the second output transistor are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; The third output transistor and the fourth output transistor are both P-type transistors, the first to fourth clock-controlled transistors are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

14. The comparator according to claim 12, wherein: The first input transistor and the second output transistor are both P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; The third output transistor and the fourth output transistor are both N-type transistors, the first to fourth clock-controlled transistors are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

15. The comparator according to claim 4, wherein: The first positive feedback transistor and the second positive feedback transistor have the same size, the first input transistor, the second input transistor, and the fifth input transistor have the same size, and the size of the first positive feedback transistor is less than half of the size of the first input transistor; The third positive feedback transistor and the fourth positive feedback transistor have the same size, the third input transistor, the fourth input transistor and the sixth input transistor have the same size, and the size of the third positive feedback transistor is less than half of the size of the third input transistor.

16. The comparator according to claim 1, wherein: The first switch includes a first transmission gate controlled by a first enable signal; The second switch includes a second transmission gate controlled by a second enable signal; The third switch includes a third transmission gate, and the third transmission gate is controlled by a third enable signal; The fourth switch includes a fourth transmission gate, and the fourth transmission gate is controlled by a fourth enable signal; The first to fourth enable signals are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

17. The comparator according to claim 1, wherein: The control end of the first positive feedback unit is further connected to the power supply end through a first zero switch; The control end of the second positive feedback unit is further connected to the power supply end through the zeroth zero switch; The control end of the third positive feedback unit is further connected to the ground end through the zero-first switch; The control end of the fourth positive feedback unit is further connected to the ground end through the first switch.

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