Pipeline analog-to-digital converter and signal conversion method

Abstract

A pipeline analog-to-digital converter includes a plurality of converter circuit systems and a correction circuit system. The plurality of converter circuit systems converts an input signal into a plurality of first digital codes in sequence. A first converter circuit system of the plurality of converter circuit systems performs a quantization operation to generate a first corresponding digital code of the plurality of first digital codes according to a first signal, wherein the first signal is one of the input signal and a preceding residual signal, which is a signal processed by the first converter circuit system. The correction circuit system combines the plurality of first digital codes to output a second digital code, detects whether the quantization operation is completed to generate a plurality of control signals, and determines whether to set the second digital code as a second corresponding digital code of a plurality of default digital codes according to the plurality of control signals.

Description

TECHNICAL FIELD

[0001] The present application relates to a pipeline analog-to-digital converter, and more particularly, to a pipeline analog-to-digital converter with default digital codes and a signal conversion method thereof. BACKGROUND

[0002] A pipeline analog-to-digital converter can sequentially convert an input signal into corresponding digital codes through multiple stages of conversion. In the prior art, the operation period of each stage of conversion is fixed. As the frequency speed increases, the period of time for one cycle becomes shorter. As a result, the comparator circuit in the pipeline analog-to-digital converter can not be able to generate a correct quantization result within a predetermined period of time, resulting in an inaccurate final output digital code. SUMMARY

[0003] In some embodiments, a pipeline analog-to-digital converter includes a plurality of converter circuit systems and a correction circuit system. The plurality of converter circuit systems are configured to sequentially convert an input signal into a plurality of first digital codes. A first converter circuit system of the plurality of converter circuit systems is configured to perform a quantization operation according to a first signal to generate a first corresponding digital code of the plurality of first digital codes, wherein the first signal is the input signal and one of previous stage residual signals processed by the first converter circuit system. The correction circuit system is configured to combine the plurality of first digital codes to output a second digital code, and to detect whether the quantization operation is completed to generate a plurality of control signals, and to determine whether to set the second digital code as a second corresponding digital code of a plurality of default digital codes according to the plurality of control signals.

[0004] In some embodiments, a signal conversion method includes the following operations: sequentially converting an input signal into a plurality of first digital codes by a plurality of converter circuit systems, wherein a first converter circuit system of the plurality of converter circuit systems performs a quantization operation according to a first signal to generate a first corresponding digital code of the plurality of first digital codes, and the first signal is the input signal and one of previous stage residual signals processed by the first converter circuit system; combining the plurality of first digital codes to output a second digital code; and detecting whether the quantization operation is completed to generate a plurality of control signals, and determining whether to set the second digital code as a second corresponding digital code of a plurality of default digital codes according to the plurality of control signals.

[0005] The features, operations and effects of the present application will be described in detail below with reference to the accompanying drawings and preferred embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present application is shown;

[0007] Figure 2A Fig. 1 shows a schematic diagram of a signal conversion method according to some embodiments of the present application; Figure 1 Fig. 2 shows a schematic diagram of a converter circuit system in Fig. 1 ;

[0008] Figure 2B Fig. 3 shows a schematic diagram of a sub-ADC circuit in Fig. 1 ; Figure 2A Fig. 4 shows a schematic diagram of a detection circuit in Fig. 1 ;

[0009] Figure 2C Fig. 5 shows a schematic diagram of a correction circuit system in Fig. 1 ; and Figure 1 Fig. 6 shows a schematic diagram of a signal conversion method according to some embodiments of the present application.

[0010] Figure 2D Fig. 7 shows a plot of a conversion characteristic of a signal and a residual signal in Fig. 1 ; Figure 1 Fig. 8 shows a flowchart of an operation of a correction circuit system in Fig. 1 ; and

[0011] Figure 3 Fig. 9 shows a flowchart of a signal conversion method according to some embodiments of the present application. Figure 1

[0012] Figure 4 00, 01, 10: digital code

[0013] 100: pipeline ADC

[0014] 110: sample-and-hold circuit

[0015] 120[1], 120[2], 120[3]: converter circuit system

[0016] 121: sub-ADC circuit

[0017] 122: multiplication DAC circuit

[0018] 122-1: sub-DAC circuit

[0019] 122-2: subtracter circuit

[0020] 122-3: residue amplifier circuit

[0021] 130: correction circuit system

[0022] 132: detection circuit

[0023] 134: control logic circuit

[0024]

[0025]

[0026] ​​​201, 202: comparator circuit

[0027] 203: encoder circuit

[0028] 211-212: logic gate circuit

[0029] 213-214: flip-flop circuit

[0030] 221, 222: section

[0031] 400: signal conversion method

[0032] A, A', B, B', C, C', D, D': point

[0033] CLK1, CLK2, CLK1', CLK2', CLK3, CLK3': frequency signal

[0034] D1[1]-D1[3], DOUT: digital code

[0035] D2[1]-D2[4]: default digital code

[0036] S1, S2, S3: signal

[0037] S2[1], S2[2]: residual signal

[0038] S310, S320, S330, S410, S420, S430: operation

[0039] SV[1], SV[2]: effective signal

[0040] VC[1]-VC[4]: control signal

[0041] VIN: input signal

[0042] Tsample: sampling period

[0043] Tamplify: amplification period

[0044] VREF, VREF1, VREF2: reference voltage

[0045] VO1-VO4: output signal DETAILED DESCRIPTION

[0046] All technical and scientific terms used herein have their ordinary meaning. The definitions in commonly used dictionaries apply to all terms as set forth herein, including any terms discussed in this disclosure, unless expressly stated otherwise. Similarly, the disclosure is not limited to the embodiments shown in the figures.

[0047] As used herein, "coupled" or "connected" can be electrically or physically, where "electrically" or "physically" can mean directly or indirectly, as understood by one of ordinary skill in the art. As used herein, the term "circuitry" can refer to an entirety of a system formed of at least one circuit, and the term "circuit" can refer to a device that connects at least one transistor and / or at least one passive component in a certain manner to process a signal.

[0048] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. In the present document, the use of first, second, third, etc., words is used to describe and distinguish various components. Thus, a first component as described herein can also be termed a second component without departing from the true intent and scope of the present application. For ease of understanding, like components in the various drawings will be designated by the same reference numerals.

[0049] Figure 1 A schematic diagram of a pipeline analog-to-digital converter 100 is drawn according to some embodiments of the present application. The pipeline analog-to-digital converter 100 includes a sample-and-hold circuit 110, a plurality of converter circuitries 120[1]-120[3], and a correction circuitry 130.

[0050] The sample-and-hold circuit 110 samples an input signal VIN according to a frequency signal CLK1 and outputs the sampled input signal VIN as a signal S1. In some embodiments, the sample-and-hold circuit 110 can be implemented by a switched-capacitor circuit. The plurality of converter circuitries 120[1]-120[3] sequentially convert the input signal VIN (i.e., the signal S1) sampled by the sample-and-hold circuit 110 into a plurality of digital codes D1[1]-D1[3]. In some embodiments, the plurality of converter circuitries 120[1]-120[2] have the same structure. In some embodiments, the converter circuitry 120[3] can be (but not limited to) a flash analog-to-digital converter circuit that generates a digital code D1[3] according to a residual signal S2[2] generated by the converter circuitry 120[2].

[0051] The correction circuitry 130 detects whether a quantization operation of the converter circuitry 120[1] is completed to generate a plurality of control signals VC[1] and VC[2], and detects whether a quantization operation of the converter circuitry 120[2] is completed to generate a plurality of control signals VC[3] and VC[4]. The correction circuitry 130 further combines the plurality of digital codes D1[1]-D1[3] to output a digital code DOUT, and determines whether to set the digital code DOUT to a corresponding one of a plurality of default digital codes D2[1]-D2[4] according to the plurality of control signals VC[1]-VC[4].

[0052] In some embodiments, the correction circuitry 130 is further configured to test the plurality of converter circuitries 120[1]~120[3] during a test period to generate a plurality of default digital codes D2[1]~D2[4]. Details regarding the operation will be described later with reference to Figure 3

[0053] In some embodiments, the correction circuitry 130 comprises a detection circuit 132 and a control logic circuit 134. The detection circuit 132 is configured to detect whether the quantization operation of the converter circuitry 120[1] and the converter circuitry 120[2] is completed to generate a plurality of control signals VC[1]~VC[4]. The control logic circuit 134 is configured to combine the plurality of digital codes D1[1]~D1[3] into a digital code DOUT. The control logic circuit 134 is configured to determine whether to set the digital code DOUT as a corresponding one of the default digital codes D2[1]~D2[4] according to the plurality of control signals VC[1]~VC[4].

[0054] For example, if the detection circuit 132 detects that the quantization operation of the comparator circuit (e.g., the comparator circuit 201 of Figure 2B ) in the converter circuitry 120[1] is not completed, the detection circuit 132 can output a control signal VC[1] having a first logic value (e.g., a logic value 1). In response to the control signal VC[1], the control logic circuit 134 can set the digital code DOUT as the default digital code D2[1]. If the detection circuit 132 detects that the quantization operation of another comparator circuit (e.g., the comparator circuit 202 of Figure 2B ) in the converter circuitry 120[1] is not completed, the detection circuit 132 can output a control signal VC[2] having the first logic value. In response to the control signal VC[2], the control logic circuit 134 can set the digital code DOUT as the default digital code D2[2]. If the control signal VC[1] or the control signal VC[2] has a second logic value (e.g., a logic value 0), the control logic circuit 134 does not set the digital code DOUT as the default digital code D2[1] or the default digital code D2[2]. In the same manner, the corresponding relationship between the plurality of control signals VC[3]~VC[4] and the default digital codes D2[3]~D2[4] should be understood. In some embodiments, the control logic circuit 134 can be implemented by a plurality of digital circuits and at least one buffer circuit, wherein the at least one buffer circuit can be used to store the plurality of default digital codes D2[1]~D2[4].

[0055] Figure 2A Figures 1A~1C illustrate the operation of the correction circuitry 130 according to some embodiments of the present application. Figure 1 ​FIG. 1 shows a schematic diagram of a converter circuit system 120[1] in accordance with some embodiments of the present application. The converter circuit system 120[1] includes a sub-ADC circuit 121 and a multiplying digital-to-analog converter (MDAC) circuit 122 (hereinafter referred to as the MDAC circuit 122). During a sampling period Tsample of a frequency signal CLK1, the sub-ADC circuit 121 performs a quantization operation on a signal S1 to generate a digital code D1[1]. The MDAC circuit 122 processes the digital code D1[1] and the signal S1 to generate a first-stage residue signal S2[1] in accordance with a frequency signal CLK2. For example, in response to a rising edge of the frequency signal CLK2, the MDAC circuit 122 can start processing the digital code D1[1] and the signal S1 and generate the first-stage residue signal S2[1] during an amplification period Tamplify of the frequency signal CLK2.

[0056] In some embodiments, the MDAC circuit 122 includes a sub-DAC circuit 122-1, a subtractor circuit 122-2, and a residue amplifier circuit 122-3. In response to the frequency signal CLK2, the sub-DAC circuit 122-1 can convert the digital code D1[1] to a signal S2. The subtractor circuit 122-2 subtracts the signal S2 from the signal S1 to generate a signal S3. The residue amplifier circuit 122-3 can amplify the signal S3 to output the first-stage residue signal S2[1]. In some embodiments, the sub-DAC circuit 122-1, the subtractor circuit 122-2, and the residue amplifier circuit 122-3 can be implemented by a switched-capacitor circuit (not shown). Some switches of the switched-capacitor circuit are turned on during the sampling period Tsample of the frequency signal CLK1 to store the signal S1. Other switches of the switched-capacitor circuit are turned on during the amplification period Tamplify of the frequency signal CLK2 to perform the relevant operations of the MDAC circuit 122.

[0057] Figure 2B FIG. 2 shows a schematic diagram of a converter circuit system 120[2] in accordance with some embodiments of the present application. Figure 2Aa schematic diagram of a sub-analog-to-digital converter circuit 121 in FIG. 1. In some embodiments, the sub-analog-to-digital converter circuit 121 includes a comparator circuit 201, a comparator circuit 202, and an encoder circuit 203. The comparator circuit 201 and the comparator circuit 202 compare the signal S1 with a reference voltage VREF1 and a reference voltage VREF2, respectively (equivalent to the aforementioned quantization operation), to generate a plurality of output signals VO1-VO4. The encoder circuit 203 encodes the plurality of output signals VO1-VO4 according to a frequency signal CLK2 to output a corresponding digital code D1[1]. In some embodiments, the encoder circuit 203 can include a plurality of logic gate circuits (such as, but not limited to, a plurality of AND gate circuits) that output the digital code D1[1] when the frequency signal CLK2 is at a high level.

[0058] In detail, the comparator circuit 201 compares the signal S1 with the reference voltage VREF1 to generate an output signal VO1 and an output signal VO2. In some embodiments, the comparator circuit 201 is a differential comparator circuit. In an initial state, both output terminals of the differential comparator circuit are reset to a preset level, so that the output signal VO1 and the output signal VO2 have a default level. For example, the preset level is a high level, and the output signal VO1 and the output signal VO2 have a logic value of 1 in the initial state. Alternatively, in another example, the preset level is a low level, and the output signal VO1 and the output signal VO2 have a logic value of 0 in the initial state. After the comparison between the signal S1 and the reference voltage VREF1 is completed, one output terminal of the comparator circuit 201 has a high level, and the other output terminal of the comparator circuit 201 has a low level. In other words, after the quantization operation is completed, one of the output signal VO1 and the output signal VO2 has a logic value of 1 and the other has a logic value of 0. Therefore, the detection circuit 132 can determine whether the quantization operation of the comparator circuit 201 is completed according to the logic values of the plurality of output signals VO1-VO2, and can determine whether the quantization operation of the comparator circuit 202 is completed according to the logic values of the plurality of output signals VO3-VO4. The related operations of the comparator circuit 202 can refer to the related operations of the comparator circuit 201, and thus are not repeated. In some embodiments, the reference voltage VREF1 can be (but is not limited to) -0.25 times the reference voltage VREF, and the reference voltage VREF2 can be (but is not limited to) 0.25 times the reference voltage VREF.

[0059] Figure 2C a schematic diagram of the detection circuit 132 in FIG. 1 according to some embodiments of the present application. For easy understanding, Figure 1 a schematic diagram of the detection circuit 132 in FIG. 1 according to some embodiments of the present application. For easy understanding, Figure 2COnly the circuit portion used to detect the quantization operation of the converter circuit system 120 [1] is shown. The detection circuit 132 includes multiple logic gate circuits 211-212 and multiple flip-flop circuits 213-214. As previously described, in Figure 2B In some examples, output signals VO1 and VO2 have a logic value of 1 in the initial state. After the quantization operation is completed, one of the output signals VO1 and VO2 has a logic value of 1 and the other has a logic value of 0. Under this condition, each of the multiple logic gate circuits 211 to 212 can be implemented by a NAND gate circuit. The multiple logic gate circuits 211 to 212 generate multiple active signals SV[1] to SV[2] based on the multiple output signals VO1 to VO4. For example, logic gate circuit 211 generates an active signal SV[1] based on the multiple output signals VO1 to VO2. If both output signals VO1 and VO2 have a logic value of 1, this logic gate circuit 211 can output an active signal SV[1] with a logic value of 0 to indicate that the quantization operation has not yet been completed. If one of the output signals VO1 and VO2 has a logic value of 1 and the other of the output signals VO1 and VO2 has a logic value of 0, logic gate circuit 211 can output an active signal SV[1] with a logic value of 1 to indicate that the quantization operation has been completed. Similarly, the logic gate circuit 212 can generate an effective signal SV based on multiple output signals VO3~VO4[2].

[0060] Multiple flip-flop circuits 213-214 receive multiple active signals SV[1]-SV[2] respectively based on the frequency signal CLK3 to generate multiple control signals VC[1]-VC[2]. In some embodiments, each of the multiple flip-flop circuits 213-214 may be a D-type flip-flop circuit. In some embodiments, the frequency signal CLK3 may be the frequency signal CLK2. In some embodiments, the frequency signal CLK3 and the frequency signal CLK2 have the same initial timing, or the phase of the frequency signal CLK3 leads the phase of the frequency signal CLK2. In response to the rising edge of the frequency signal CLK3, the multiple flip-flop circuits 213-214 may output multiple active signals SV[1]-SV[2] as multiple control signals VC[1]-VC[2]. If the control signal VC[1] is a logic value of 1, it means that the quantization operation of the comparator circuit 201 has been completed. If the control signal VC[1] is a logic value of 0, it means that the quantization operation of the comparator circuit 201 has not been completed. If the control signal VC[2] is a logic value of 1, it means that the quantization operation of the comparator circuit 202 has been completed. If the control signal VC[2] is a logic value of 0, it means that the quantization operation of the comparator circuit 202 has not been completed.

[0061] The above-described configuration of the detection circuit 132 is merely an example, and this invention is not limited thereto. For example, if in Figure 2BIn other examples, output signals VO1 and VO2 have a logic value of 0 in the initial state. After the quantization operation is completed, one of output signals VO1 and VO2 has a logic value of 1 and the other has a logic value of 0. Under this condition, each of the plurality of logic gate circuits 211 to 212 can be implemented by a non-OR gate circuit.

[0062] The circuit structure of converter circuit system 120[2] is the same as that of converter circuit system 120[1]. For example Figure 1 As shown, the operation of the converter circuit system 120[2] is performed based on the frequency signals CLK1' and CLK2'. Similar to... Figure 2A The frequency signals CLK1 and CLK2 are given. CLK1' has a sampling period Tsample, and CLK2' has an amplification period Tapmplify, with Tapmplify following the sampling period Tsample of CLK1'. In some embodiments, the sampling period Tsample of CLK1' and the amplification period Tapmplify of CLK2 may partially overlap or not overlap. Similarly, the detection circuit 132 may include two additional logic gate circuits and two additional flip-flop circuits to detect the quantization operation of the converter circuit system 120[2]. The two additional logic gate circuits receive multiple output signals from the converter circuit system 120[2], and the two additional flip-flop circuits operate according to another frequency signal (e.g., Tsample). Figure 1 The frequency signal CLK3') outputs control signals VC[3] and VC[4], wherein the setting method between the frequency signal CLK3' and the frequency signal CLK2' is similar to that of the frequency signal CLK2'. Figure 2C The setting method between frequency signal CLK3 and frequency signal CLK2. The operation and setting method of the above converter circuit system 120[2] and detection circuit 132 can be referred to Figure 2B as well as Figure 2C I understand, so I won't repeat myself.

[0063] Figure 2D Drawings for some embodiments of the present invention. Figure 1 The conversion characteristics of the input signal VIN and the residual signal S2[1] are shown in the figure. Figure 2D In the diagram, the horizontal axis represents the input signal VIN (i.e., signal S1) to the converter circuit system 120[1], and the vertical axis represents the current residual signal S2[1] to the converter circuit system 120[2]. Figure 2BIn the example of FIG. 1, the sub-ADC circuit 121 corresponds to a 1.5-bit ADC that provides a digital code D1[l] (or D1[2]) corresponding to the region in which the analog signal (e.g., signal S1 or residual signal S2[l]) falls. For example, if the input signal VIN is less than -0.25 times a reference voltage VREF (i.e., VREF1), the digital code D1[l] is 00 (which corresponds to a value of -1). If the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF (i.e., VREF2), the digital code D1[l] is 01 (which corresponds to a value of 0). If the input signal VIN is greater than 0.25 times the reference voltage VREF, the digital code D1[l] is 10 (which corresponds to a value of 1).

[0064] To ensure that the residual signal S2[l] falls within the input signal range of the secondary converter circuitry (e.g., converter circuitry 120[2]), the MDAC circuit 122 can perform a corresponding operation on the input signal VIN based on the current digital code D1[l] (as follows). In this way, the converter circuitry 120[2] can properly process the input signal VIN in sequence.

[0065] S2[l] = 2 x V IN - VREF, if V IN > 0.25 x VREF

[0066] S2[l] = 2 x V IN , if -0.25 x VREF < V IN < 0.25 x VREF

[0067] S2[l] = 2 x V IN + VREF, if V IN < -0.25 x VREF

[0068] According to the above equation, if the sub-ADC circuit 121 determines that the input signal VIN is less than -0.25 times the reference voltage VREF, the MDAC circuit 122 will shift the input signal VIN upward to output the current stage residual signal S2[1]. As a result, the subsequent converter circuit system (e.g., the converter circuit system 120[2] and the converter circuit system 120[3]) will output digital codes D1[2]-D1[3] with larger values according to the current stage residual signal S2[1]. Alternatively, if the sub-ADC circuit 121 determines that the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF, the MDAC circuit 122 will not shift the input signal VIN to output the current stage residual signal S2[1]. As a result, the subsequent converter circuit system will output digital codes D1[2] and D1[3] with smaller values according to the current stage residual signal S2[1] compared to the digital codes D1[2] and D1[3] in the above case. If the sub-ADC circuit 121 determines that the input signal VIN is greater than 0.25 times the reference voltage VREF, the MDAC circuit 122 will shift the input signal VIN downward to output the current stage residual signal S2[1]. As a result, the subsequent converter circuit system will output digital codes D1[2] and D1[3] with the smallest values according to the current stage residual signal S2[1] compared to the digital codes D1[2] and D1[3] in the previous two cases.

[0069] In terms of the two intervals corresponding to the two consecutive digital codes 00 and the digital code 01, if the input signal VIN (e.g., falling at the position of point A) is less than but very close to -0.25 times the reference voltage VREF, in an ideal case, the comparator circuit 201 can determine that the input signal VIN is less than -0.25 times the reference voltage VREF. However, due to the effect of noise and / or due to the effect of the voltage difference (e.g., the difference between the input signal VIN and the reference voltage VREF2) being too small (indicated as the interval 221), the comparator circuit 201 can need a longer time to complete the quantization operation. If the quantization operation cannot be completed within the predetermined amplification period Tamplify, the comparator circuit 201 can misjudge that the input signal VIN (e.g., falling at the position of point A') is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will not shift the input signal VIN (corresponding to the position of point A') upward, and the subsequent converter circuit system 120[2] and the converter circuit system 120[3] will output relatively small digital codes D1[2]-D1[3]. As a result, the subsequent output digital code DOUT will not be accurate.

[0070] Alternatively, if the input signal VIN (e.g., falling at point B) is greater than but very close to -0.25 times the reference voltage VREF, in an ideal case, the comparator circuit 201 can determine that the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. However, due to noise effects and / or due to the effects of the voltage difference being too small, the comparator circuit 201 can erroneously determine that the input signal VIN (e.g., falling at point B') is less than -0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will shift the input signal VIN (corresponding to point B') up, and the subsequent converter circuitry 120[2] and 120[3] will output larger digital codes D1[2]-D1[3]. As a result, the digital code DOUT will be inaccurate.

[0071] Similarly, in terms of the two intervals corresponding to the two digital codes 01 and 10 in succession, if the input signal VIN (e.g., falling at point C) is very close to but less than 0.25 times the reference voltage VREF, in an ideal case, the comparator circuit 202 can determine that the input signal VIN is less than 0.25 times the reference voltage VREF. However, due to noise effects and / or due to the effects of the voltage difference (e.g., the difference between the input signal VIN and the reference voltage VREF) being too small (indicated as interval 222), the comparator circuit 202 can take a long time to complete the quantization operation. If the quantization operation cannot be completed within the predetermined amplification period Tamplify, the comparator circuit 202 can erroneously determine that the input signal VIN (e.g., falling at point C') is greater than 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will shift the input signal VIN (corresponding to point C') down, and the subsequent converter circuitry 120[2] and 120[3] will output smaller digital codes D1[2]-D1[3]. As a result, the subsequently output digital code DOUT will be inaccurate.

[0072] Alternatively, if the input signal VIN (e.g., at point D) is greater than but very close to 0.25 times the reference voltage VREF, ideally, the comparator circuit 202 can determine that the input signal VIN is greater than 0.25 times the reference voltage VREF. However, due to noise and / or due to the small voltage difference, the comparator circuit 202 may misjudge the input signal VIN (e.g., misjudge it as falling at point D') to be at -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will not shift the input signal VIN (corresponding to the position of point D'), and the subsequent converter circuit system 120[2] and converter circuit system 120[3] will output larger digital codes D1[2] to D1[3]. This will make the digital code DOUT inaccurate. In some embodiments, the correction circuit system 130 can be used to... Figure 3 The relevant operations will be used to improve the above problems.

[0073] Figure 3 Drawings for some embodiments of the present invention. Figure 1 The operation flowchart of the correction circuit system 130 is shown. In some embodiments, Figure 3 Multiple operations can be performed by the control logic circuit 134 of the correction circuit system 130. In operation S310, during the test, the maximum value generated by subsequent converter circuit systems (e.g., converter circuit systems 120[2] to 120[3] after converter circuit system 120[1]) based on the current residual signal output by the converter circuit system when a converter circuit system (e.g., converter circuit system 120[1]) outputs a corresponding digital code with a first value is recorded. For example, when converter circuit system 120[1] outputs a digital code D1[1] with a value of -1, the control logic circuit 134 can record the maximum value generated by converter system 120[2] and converter circuit system 120[3] based on the residual signal S2[1]. As previously mentioned, the above-mentioned maximum value may occur when a signal S1 with a value of 0 is misjudged as a digital code D1[1] with a value of -1 (e.g., misjudging point B as point B'). Alternatively, when the converter circuit system 120[2] outputs a digital code D1[2] with a value of -1, the control logic circuit 134 can record the maximum value generated by the converter circuit system 120[3] based on the residual signal S2[2].

[0074] At operation S320, during the test, the minimum value generated by the subsequent converter circuitry according to the level residual signal outputted by the converter circuitry when the converter circuitry outputs a corresponding digital code with a second value is recorded, where the first value and the second value are consecutive values, and the second value is greater than the first value. For example, when the converter circuitry 120[1] outputs the digital code D1[1] with the value of 0, the control logic circuit 134 can record the minimum value generated by the converter circuitry 120[2] and the converter circuitry 120[3] according to the residual signal S2[1]. As previously described, the minimum value can be the value generated in the case that the signal S1 with the value of -1 is misjudged as the digital code D1[1] with the value of 0 (e.g., the point A is misjudged as the point A'). Alternatively, when the converter circuitry 120[2] outputs the digital code D1[2] with the value of 0, the control logic circuit 134 can record the minimum value generated by the converter circuitry 120[3] according to the residual signal S2[2].

[0075] At operation S330, the corresponding one of the plurality of default digital codes is determined according to the minimum value, the maximum value, the first value, and the second value. In some embodiments, after recording the maximum value and the minimum value corresponding to all the comparator circuits in the converter circuitry 120[1] and the converter circuitry 120[2], the corresponding one of the plurality of default digital codes D2[1]-D2[4] can be determined. For example, the default digital code D2[1] corresponding to the comparator circuit 201 in the converter circuitry 120[1] can be determined as follows: Figure 2B

[0076]

[0077] where N1 is the first value (e.g., -1), N2 is the second value (e.g., 0), X1 is the minimum value, X2 is the maximum value, and ω is a weight value. In some embodiments, ω represents the normalization of the digital code (e.g., the digital code D1[1]) of the current converter circuitry to all the digital codes (e.g., the digital code D1[2] and the digital code D1[3]) outputted by the subsequent converter circuitry.

[0078] According to the above formula, the default digital code D2[1] can be determined as follows: Figure 2D It can be understood that, after obtaining the minimum value and the maximum value, the default digital code D2[1] can be determined by using the above formula, so that the default digital code D2[1] can be located at the middle value of the interval 221. In this way, a default digital code D2[1] with a conversion characteristic close to the ideal conversion characteristic can be obtained. Therefore, when it is detected that the quantization operation of the comparator circuit 201 is not completed, the control signal VC[1] has the logic value of 1. In response to the control signal VC[1], the control logic circuit 134 can set the digital code DOUT as the default digital code D2[1].​

[0079] By analogy, through operations S310-S330, the correction circuitry 130 can record the plurality of default digital codes D2[1]-D2[4] corresponding to the plurality of comparator circuits (e.g., the plurality of comparator circuits 201 and 202) in the converter circuitry 120[1] and the converter circuitry 120[2] during the test. In this way, in a subsequent operation, the correction circuitry 130 can determine whether to set the digital code DOUT as a corresponding digital code in the plurality of default digital codes D2[1]-D2[4] according to the detection result of the quantization operation.

[0080] Figure 4 A flowchart of a signal conversion method 400 according to some embodiments of the present application is shown. In operation S410, an input signal is converted into a plurality of first digital codes by a plurality of converter circuitries (e.g., the converter circuitries 120[1]-120[3]) in sequence, wherein a first converter circuitry in the plurality of converter circuitries performs a quantization operation according to a first signal to generate a first corresponding digital code in the plurality of first digital codes, and the first signal is one of the input signal and a previous-stage residual signal processed by the first converter circuitry. For example, if the first converter circuitry is the converter circuitry 120[1], the first signal is the sampled input signal VIN (e.g., the signal S1). Alternatively, if the first converter circuitry is the converter circuitry 120[2], the first signal is the residual signal S2[1] from the converter circuitry 120[1]. In operation S420, the plurality of first digital codes are combined to output a second digital code. In operation S430, it is detected whether the quantization operation is completed to generate a plurality of control signals, and it is determined whether to set the second digital code as a second corresponding digital code in a plurality of default digital codes according to the plurality of control signals.

[0081] The above-mentioned operations S410, S420, and S430 are described with reference to the above-mentioned various embodiments, and thus are not repeated. The plurality of operations of the signal conversion method 400 are only examples, and are not limited to be performed in the order in the examples. Various operations in the signal conversion method 400 can be appropriately added, replaced, omitted, or performed in different orders without departing from the operation manner and scope of the embodiments of the present application.

[0082] In summary, the pipeline ADC and the signal conversion method in some embodiments of the present application can detect whether the quantization operation of each-stage converter circuitry is completed, and determine whether to replace the final output digital code with a default digital code. In this way, the inaccuracy of the digital code generated by each-stage converter circuitry can be avoided.

[0083] The above merely describes preferred embodiments of the present application, but these embodiments are not intended to limit the present application. Any modification, equivalent replacement, or improvement made on the technical solutions of the present application within the technical scope disclosed by the present application should be covered by the patent protection of the present application. In other words, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A pipelined analog-to-digital converter, characterized in that, The pipeline analog-to-digital converter includes: Multiple converter circuit systems are configured to sequentially convert an input signal into multiple first digital codes, wherein the first converter circuit system in the multiple converter circuit systems is configured to perform a quantization operation based on a first signal to generate a first corresponding digital code among the multiple first digital codes, wherein the first signal is a signal processed by the first converter circuit system and is one of the input signal and the previous stage residual signal. as well as A calibration circuit system is used to combine the plurality of first digital codes to output a second digital code, and to detect whether the quantization operation is completed to generate a plurality of control signals, and to determine whether to set the second digital code as the second corresponding digital code among a plurality of default digital codes based on the plurality of control signals.

2. The pipeline analog-to-digital converter as described in claim 1, characterized in that, The first converter circuit system is further configured to process the first signal according to the first corresponding digital code to generate a current level residual signal, and the correction circuit system is further configured to record, during the test, the maximum value generated by at least one of the plurality of converter circuit systems according to the current level residual signal when the first converter circuit system outputs the first corresponding digital code with a first value, and to record the minimum value generated by at least one of the plurality of converter circuit systems according to the current level residual signal when the first converter circuit system outputs the first corresponding digital code with a second value, so as to generate a corresponding one among the plurality of default digital codes.

3. The pipeline analog-to-digital converter as described in claim 2, characterized in that, The first value and the second value are consecutive values, and the second value is greater than the first value.

4. The pipeline analog-to-digital converter as described in claim 2, characterized in that, The corresponding value among the plurality of default numeric codes is determined based on the minimum value, the maximum value, the third value, and the fourth value, wherein the third value is the product of the first value and the weight value, and the fourth value is the product of the second value and the weight value.

5. The pipeline analog-to-digital converter as described in claim 1, characterized in that, The correction circuit system includes: A detection circuit is used to detect whether the quantization operation is completed, so as to generate the plurality of control signals; and A control logic circuit is configured to combine the plurality of first digital codes to generate the second digital code, and to determine whether to set the second digital code as the second corresponding digital code based on the plurality of control signals.

6. The pipeline analog-to-digital converter as described in claim 5, characterized in that, The detection circuit includes: Multiple logic gate circuits are used to generate multiple active signals based on multiple output signals from the first converter circuit system; as well as Multiple flip-flop circuits are used to receive the multiple active signals to generate the multiple control signals.

7. The pipeline analog-to-digital converter as described in claim 6, characterized in that, The first converter circuit system includes: A multiplicative digital-to-analog converter circuit is used to process the first corresponding digital code and the first signal according to the first frequency signal to generate a current residual signal. The plurality of flip-flop circuits are used to generate the plurality of control signals according to the second frequency signal, wherein the second frequency signal is the same as the first frequency signal, or the phase of the second frequency signal leads the phase of the first frequency signal.

8. The pipeline analog-to-digital converter as described in claim 6, characterized in that, The first converter circuit system includes a sub-analog-to-digital converter circuit, and the sub-analog-to-digital converter circuit includes: Multiple comparator circuits are used to compare the first signal with multiple reference voltages respectively to generate the multiple output signals; as well as An encoder circuit is used to encode the plurality of output signals to output the first corresponding digital code.

9. A signal conversion method, characterized in that, The signal conversion method includes: An input signal is converted into a plurality of first digital codes in sequence by a plurality of converter circuit systems, wherein the first converter circuit system in the plurality of converter circuit systems performs a quantization operation according to a first signal to generate a first corresponding digital code among the plurality of first digital codes, and the first signal is a signal processed by the first converter circuit system and is one of the input signal and the previous stage residual signal. Combine the plurality of first digital codes to output a second digital code; as well as The system detects whether the quantization operation is complete to generate multiple control signals, and determines whether to set the second digital code as the second corresponding digital code among multiple default digital codes based on the multiple control signals.

10. The signal conversion method as described in claim 9, characterized in that, The first converter circuit system is further configured to process the first signal according to the first corresponding digital code to generate a current residual signal, and the signal conversion method further includes: During the test, the maximum value generated by at least one of the plurality of converter circuit systems based on the current residual signal is recorded when the first converter circuit system outputs the first corresponding digital code with a first value. as well as During the test, the minimum value generated by at least one of the plurality of converter circuit systems based on the current residual signal is recorded when the first converter circuit system outputs the first corresponding digital code with a second value. as well as The corresponding value among the plurality of default numeric codes is generated based on the first value, the second value, the minimum value, and the maximum value.

Images