Light emitting diode chip structure with reflective element

Abstract

A light emitting diode (LED) chip structure with a cup-shaped reflective element is provided. The LED chip structure includes a substrate, an isolation element, and a mesa including an LED and surrounded by the isolation element. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is in the substrate, and the upper isolation portion protrudes from a surface of the substrate. A reflective layer is disposed on sidewalls of the upper isolation portion, and a bottom of the reflective layer does not contact the mesa. The cup-shaped reflective element includes at least the isolation element with the reflective layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 013,358, filed April 21, 2020, entitled “LIGHT-EMITTING DIODE CHIP STRUCTURES WITH REFLECTIVE ELEMENTS”, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to light-emitting diode (LED) display devices, and more specifically, to LED chip structures having one or more reflective elements. Background Technology

[0004] With the development of mini-LED and micro-LED technologies in recent years, consumer devices and applications such as augmented reality (AR), projection, head-up displays (HUDs), mobile device displays, wearable device displays, and automotive displays require LED panels with improved resolution and brightness. LEDs can be miniaturized and used as pixel light emitters in display systems, such as in micro-display systems. Achieving higher resolution and brightness on small displays can be challenging when simultaneously meeting both requirements. That is, pixel resolution and brightness can be difficult to balance because they can have inverse relationships. For example, achieving high brightness per pixel may result in low resolution. Conversely, achieving high resolution may reduce brightness.

[0005] Furthermore, the light emitted by micro-LEDs may be spontaneously generated and therefore potentially non-directional, resulting in a large divergence angle. A large divergence angle can cause various problems in micro-LED displays. On one hand, due to the large divergence angle, only a small fraction of the light emitted by the micro-LED can be utilized. This can significantly reduce the efficiency and brightness of the micro-LED display system. On the other hand, due to the large divergence angle, the light emitted by one micro-LED pixel may illuminate its adjacent pixels, leading to inter-pixel crosstalk, loss of sharpness, and loss of contrast. Traditional solutions for reducing large divergence angles may not effectively handle the overall light emitted by the micro-LED, potentially utilizing only the central portion of the light emitted from the micro-LED while leaving the remaining light emitted at a more oblique angle unused.

[0006] Therefore, it is desirable to provide an LED structure for a display device to address, in particular, the aforementioned disadvantages and other defects. Summary of the Invention

[0007] Exemplary embodiments of this disclosure pertain to LED chip structures having one or more reflective elements. In some embodiments, the reflective element is a cup-shaped structure surrounding an LED pixel unit.

[0008] Exemplary embodiments of the LED chip structure in this disclosure include an isolation element comprising an upper isolation portion and a lower isolation portion. An exemplary embodiment also includes a reflective layer disposed directly or indirectly on the upper isolation portion. The isolation element can reduce the divergence of light emitted from the mesa comprising the LED pixel units and reduce optical crosstalk between adjacent pixels. For example, the isolation element and the reflective layer can utilize light from an angled region. In this way, higher efficiency in collecting and converging this light can be achieved, resulting in a display with higher brightness and higher power efficiency than conventional solutions. Additionally, the isolation element can block light emitted by LEDs in adjacent pixels, which can effectively suppress inter-pixel crosstalk and enhance color contrast and sharpness. Exemplary embodiments of this disclosure can improve projection brightness and contrast, thereby reducing power consumption in projection applications. Exemplary embodiments of this disclosure can also improve the light emission directionality of the display, thereby providing users with better image quality and protecting user privacy in direct-view applications.

[0009] The exemplary embodiments of this disclosure can provide several advantages. One advantage is that the exemplary embodiments of this disclosure can suppress inter-pixel optical crosstalk and improve brightness. For example, the pitch refers to the distance between the centers of adjacent pixels on a display panel. The pitch can vary from about 40 micrometers to about 20 micrometers, to about 10 micrometers, and / or to about 5 micrometers or less. With the pitch specification determined, the area of ​​a single pixel is fixed. The exemplary embodiments of this disclosure can suppress inter-pixel optical crosstalk at smaller pitches while improving the brightness within a single pixel in a more power-efficient manner. Another advantage is that, in the exemplary embodiments of this disclosure, the light-emitting diode can be directly bonded to a substrate with a pixel driver without the need for an intermediate substrate, which can improve heat dissipation, thereby improving the reliability and performance of the LED chip.

[0010] Therefore, this disclosure includes, but is not limited to, the following exemplary embodiments.

[0011] Some exemplary embodiments provide a first LED chip structure. The first LED chip structure includes a substrate and an isolation element. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is located in the substrate, and the upper isolation portion protrudes from the surface of the substrate. The first LED chip structure also includes a reflective layer disposed on a sidewall of the upper isolation portion. The first LED chip structure also includes a mesa, which includes LED components and is surrounded by the isolation element, and the bottom portion of the reflective layer does not contact the mesa.

[0012] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the substrate includes a semiconductor wafer and a bonding metal layer located on the semiconductor wafer.

[0013] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, a reflective layer is disposed on the sidewalls and top surface of the upper isolation portion, and the bottom portion of the reflective layer extends in the direction from the isolation element to the platform.

[0014] In some exemplary embodiments of the first LED chip structure or any combination of the foregoing exemplary embodiments, the first LED chip structure further includes a dielectric layer disposed at the bottom of the sidewall of the platform, the dielectric layer being covered by the bottom portion of the reflective layer.

[0015] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the height of the upper isolation portion is greater than the height of the lower isolation portion.

[0016] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the bottom width of the upper isolation portion is equal to or greater than the top width of the lower isolation portion.

[0017] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the bottom width of the upper isolation portion is greater than the top width of the lower isolation portion and less than twice the top width of the lower isolation portion, and two protrusions are formed at each bottom end of the upper isolation portion, the width of each of the two protrusions being less than half the top width of the lower isolation portion.

[0018] In some exemplary embodiments of the first LED chip structure, or any combination of the aforementioned exemplary embodiments, in a side view, the cross-section of the upper isolation portion is trapezoidal, the cross-section of the lower isolation portion is inverted trapezoidal, and the bottom of the upper isolation portion covers the top of the lower isolation portion. In some embodiments, the area of ​​the bottom of the upper isolation portion is larger than the area of ​​the top of the lower isolation portion.

[0019] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the upper isolation portion and the lower isolation portion are axisymmetric and coaxial.

[0020] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the height of the upper isolation portion relative to the surface of the substrate is greater than the height of the mesa relative to the surface of the substrate, and the tilt angle of the sidewall of the upper isolation portion relative to an axis orthogonal to the surface of the substrate is greater than the tilt angle of the sidewall of the mesa relative to an axis orthogonal to the surface of the substrate.

[0021] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the tilt angle of the sidewall of the platform is less than 45°, and the tilt angle of the sidewall of the upper isolation portion is greater than 45°.

[0022] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, a dielectric layer covers the top surface and sidewalls of the mesa, the top surface of the mesa including areas not covered by the dielectric layer or without a dielectric layer.

[0023] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the dielectric layer is transparent to the light emitted by the first LED chip structure.

[0024] In some exemplary embodiments of the first LED chip structure or any combination of the foregoing exemplary embodiments, the dielectric layer includes one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

[0025] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the silicon-containing dielectric layer comprises silicon oxide or nitride, the aluminum-containing dielectric layer comprises aluminum oxide, and the titanium-containing dielectric layer comprises titanium oxide.

[0026] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the oxide of titanium is Ti3O5.

[0027] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the reflective layer comprises a multilayer structure.

[0028] In some exemplary embodiments of the first LED chip structure or any combination of the foregoing exemplary embodiments, the multilayer structure includes a stack of one or more reflective material layers and one or more dielectric material layers.

[0029] In some exemplary embodiments of the first LED chip structure, or any combination of the foregoing exemplary embodiments, the reflective layer comprises one or more metallic conductive materials having high reflectivity. In some embodiments, the high reflectivity is 70% or higher. In some embodiments, the high reflectivity is 80% or higher. In some embodiments, the high reflectivity is 90% or higher.

[0030] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the one or more metallic conductive materials include one or more of aluminum, gold, or silver.

[0031] In some exemplary embodiments of the first LED chip structure, or any combination of the foregoing exemplary embodiments, the top surface and sidewalls of the mesa, as well as the top surface and sidewalls of the upper isolation portion, are completely or partially covered by a conductive layer. In some embodiments, the conductive layer is continuous.

[0032] In some exemplary embodiments of the first LED chip structure or any combination of the foregoing exemplary embodiments, the conductive layer is transparent to the light emitted by the first LED chip structure.

[0033] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the isolation element comprises a photosensitive dielectric material.

[0034] In some exemplary embodiments of the first LED chip structure or any combination of the aforementioned exemplary embodiments, the photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

[0035] Other exemplary embodiments provide a second LED chip structure. The second LED chip structure includes a substrate, an isolation element, a mesa, a dielectric layer, and a conductive layer. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is located in the substrate, and the upper isolation portion protrudes from the surface of the substrate. The mesa includes LED components and is surrounded by the isolation element. The dielectric layer covers the top surface and sidewalls of the mesa, and the top surface of the mesa also includes areas not covered by the dielectric layer, such as areas without a dielectric layer. The conductive layer covers the dielectric layer, the top surface of the mesa including the areas without a dielectric layer, and at least one sidewall of the upper isolation portion. A reflective layer is disposed at least on the conductive layer covering the sidewalls of the upper isolation portion, and the bottom portion of the reflective layer does not contact the mesa.

[0036] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the substrate includes a semiconductor wafer and a bonding metal layer located on the semiconductor wafer.

[0037] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, a conductive layer is disposed on the top surface and sidewalls of the upper isolation portion, and a reflective layer is disposed on the conductive layer disposed on the top surface and sidewalls of the upper isolation portion, wherein the bottom portion of the reflective layer extends from the isolation element to the platform.

[0038] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the height of the upper isolation portion is greater than the height of the lower isolation portion.

[0039] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the bottom width of the upper isolation portion is equal to or greater than the top width of the lower isolation portion.

[0040] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the bottom width of the upper isolation portion is greater than the top width of the lower isolation portion and less than twice the top width of the lower isolation portion, and two protrusions are formed at each bottom end of the upper isolation portion, the width of each of the two protrusions being less than half the top width of the lower isolation portion.

[0041] In some exemplary embodiments of the second LED chip structure, or any combination of the aforementioned exemplary embodiments, in a side view, the cross-section of the upper isolation portion is trapezoidal, the cross-section of the lower isolation portion is inverted trapezoidal, and the bottom of the upper isolation portion covers the top of the lower isolation portion. In some embodiments, the area of ​​the bottom of the upper isolation portion is larger than the area of ​​the top of the lower isolation portion.

[0042] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the upper isolation portion and the lower isolation portion are axisymmetric and coaxial.

[0043] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the height of the upper isolation portion relative to the surface of the substrate is greater than the height of the mesa relative to the surface of the substrate, and the tilt angle of the sidewall of the upper isolation portion relative to an axis orthogonal to the surface of the substrate is greater than the tilt angle of the sidewall of the mesa relative to an axis orthogonal to the surface of the substrate.

[0044] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the tilt angle of the sidewall of the platform is less than 45°, and the tilt angle of the sidewall of the upper isolation portion is greater than 45°.

[0045] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the dielectric layer is transparent to the light emitted by the second LED chip structure.

[0046] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the dielectric layer includes one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

[0047] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the silicon-containing dielectric layer comprises silicon oxide or nitride, the aluminum-containing dielectric layer comprises aluminum oxide, and the titanium-containing dielectric layer comprises titanium oxide.

[0048] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the oxide of titanium is Ti3O5.

[0049] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the reflective layer comprises a multilayer structure.

[0050] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the multilayer structure includes a stack of one or more reflective material layers and one or more dielectric material layers.

[0051] In some exemplary embodiments of the second LED chip structure, or in any combination of the foregoing exemplary embodiments, the reflective layer comprises one or more metallic conductive materials having high reflectivity. In some embodiments, the high reflectivity is 70% or higher. In some embodiments, the high reflectivity is 80% or higher. In some embodiments, the high reflectivity is 90% or higher.

[0052] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the one or more metallic conductive materials include one or more of aluminum, gold, or silver.

[0053] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the conductive layer is transparent to the light emitted by the second LED chip structure.

[0054] In some exemplary embodiments of the second LED chip structure or any combination of the foregoing exemplary embodiments, the isolation element comprises a photosensitive dielectric material.

[0055] In some exemplary embodiments of the second LED chip structure or any combination of the aforementioned exemplary embodiments, the photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

[0056] These and other features, aspects, and advantages of this disclosure will become apparent from reading the following detailed description together with the accompanying drawings, which are briefly described below. This disclosure includes any combination of two or more features or elements set forth in this disclosure, whether or not such features or elements are explicitly combined in the particular exemplary embodiments described herein or are otherwise described. This disclosure is intended to be read holistically, such that any separable features or elements in any aspect of this disclosure and in exemplary embodiments should be considered composable unless the context of this disclosure expressly provides otherwise.

[0057] Therefore, it should be understood that the purpose of providing this brief summary of the invention is merely to outline some exemplary embodiments in order to provide a basic understanding of some aspects of this disclosure. Consequently, it should be understood that the above exemplary embodiments are merely examples and should not be construed as limiting the scope or spirit of this disclosure in any way. Other exemplary embodiments, aspects, and advantages will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate by way of example the principles of some of the described exemplary embodiments. Attached Figure Description

[0058] To enable this disclosure to be understood in more detail, it can be described more specifically by referring to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, these drawings only illustrate relevant features of this disclosure and should not be considered limiting, as the description may allow for other valid features.

[0059] Figure 1 A top view of an LED chip structure according to some exemplary embodiments is shown.

[0060] Figure 2 A cross-sectional view of an LED chip structure according to some exemplary embodiments is shown.

[0061] Figure 3 A cross-sectional view of another LED chip structure according to some exemplary embodiments is shown.

[0062] Figure 4 A cross-sectional view of a reflective layer with a multilayer structure according to some exemplary embodiments is shown.

[0063] As is common practice, the various features illustrated in the accompanying drawings may not be drawn to scale. Therefore, for clarity, the dimensions of the features may be arbitrarily expanded or reduced. Additionally, some drawings may not depict all parts of a given system, method, or apparatus. Finally, the same reference numerals may be used to denote similar features throughout the specification and drawings. Detailed Implementation

[0064] Some embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, of the embodiments of this disclosure. In fact, various embodiments of this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these exemplary embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of this disclosure to those skilled in the art. For example, unless otherwise stated, referring to something as first, second, etc., should not be construed as implying a particular order. Furthermore, something may be described above something (unless otherwise stated) or below something, and vice versa; similarly, something described as being to the left of something may be on the right, and vice versa. The same reference numerals always refer to the same elements.

[0065] The exemplary embodiments disclosed herein are generally directed to LED display devices, and more particularly to LED chip structures having a reflective layer.

[0066] Figure 1A top view of an LED chip structure 100 according to some exemplary embodiments is shown. As shown, in some embodiments, the LED chip structure 100 includes one or more mesa 101 (e.g., mesa 101a, 101b, and 101c). Each mesa 101 may include an LED or a microLED. Each mesa 101 has a top and a bottom. For example, a circle 120a may indicate the top of mesa 101b, a circle 120b may indicate the bottom of mesa 101b, and the surface connecting the top and bottom of mesa 101b, i.e., the sidewall of the mesa, is represented in the figure by the space between circles 120a and 120b. In some embodiments, the diameter of the top of each mesa 101 may be in the range of 1 μm to 8 μm, and the diameter of the bottom of each mesa may be in the range of 3 μm to 10 μm. In some embodiments, the diameter of the top of each mesa 101 may be in the range of 8 μm to 25 μm, and the diameter of the bottom of each mesa may be in the range of 10 μm to 35 μm. The distance between the centers of two adjacent platforms can range from 1 μm to 10 μm. In some embodiments, the distance between the centers of two adjacent platforms can vary from about 40 μm to about 20 μm, to about 10 μm, and / or to about 5 μm or less. The size of the platforms and the distance between them depend on the resolution of the display. For example, for a display panel with 5000 pixels per inch (PPI), the diameter or width of the top of platform 101b can be 1.5 μm, while the diameter or width of the bottom of platform 101b can be 2.7 μm. The height of the platforms is approximately 1.3 μm. The distance between the nearest bottom edges of platforms 101a and 101b can be 2.3 μm.

[0067] In some embodiments, the platform 101 may be surrounded by at least one isolation element 102. The isolation element 102 can isolate light emitted from different platforms. For example, when the height of the isolation element 102 is greater than the height of the platform 101a and / or 101c, the isolation element 102 can isolate at least a portion of the light emitted from the platform 101a and / or 101c from the light emitted from the platform 101b. Therefore, the isolation element 102 can suppress inter-pixel optical crosstalk and improve the contrast of the LED display.

[0068] In some embodiments, the LED chip structure 100 further includes one or more reflective layers 103 (e.g., reflective layers 103a, 103b, and 103c). Each reflective layer 103 may be disposed on the sidewall of the isolation element 102. For example, as Figure 1As shown, the reflective layer 103b can be disposed on the circular sidewall of the isolation element 102 surrounding the platform 101b. The reflective layer 103b can reflect the light emitted from the platform 101, thereby improving the brightness and luminous efficiency of the LED display. For example, the light emitted from the platform 101b can reach the reflective layer 103b and can be reflected upwards by the reflective layer 103b.

[0069] The reflective layer 103, together with the isolating element 102, can utilize the reflection direction and / or reflection intensity of the light emitted from the mesa 101. For example, the sidewalls of the isolating element 102 can be tilted at an angle, so the reflective layer 103b disposed on the sidewalls of the isolating element 102 is tilted at the same angle (within manufacturing tolerances). When light emitted from the mesa 101b reaches the reflective layer 103b, the light emitted from the mesa 101b is reflected by the reflective layer 103b according to the sidewall angle of the isolating element 102. The material of the reflective layer 103 can be highly reflective, so that most (e.g., more than 60%) of the light emitted from the mesa 101, such as mesa 101b, can be reflected. For simplicity, Figure 1 Some components of the LED chip structure 100 are omitted below. (Refer to the following...) Figure 2-4 Some embodiments of the LED chip structure are described in more detail.

[0070] Figure 2 A cross-sectional view of an LED chip structure 200 according to some exemplary embodiments is shown. In some embodiments, the cross-section of the LED chip structure 200 is along... Figure 1The AA line is cut off in the figure. As shown, in some embodiments, the LED chip structure 200 includes a substrate 208, which includes a wafer 207 and one or more bonding metal layers 206 located on the wafer 207. The bonding metal layers 206 (e.g., bonding metal layers 206a, 206b, and 206c) may be disposed on the wafer 207 and electrically bonded to the wafer 207. In some embodiments, the thickness of the bonding metal layer 206 is from about 0.1 micrometers to about 3 micrometers. For example, for a display panel with 5000 PPI, the thickness of the bonding metal layer 206 is about 1.3 μm. In some cases, the bonding metal layer 206 includes two metal layers. One of the metal layers is deposited on the mesa 201. The other corresponding bonding metal layer is also deposited on the wafer 207. In some embodiments, the composition of the bonded metal layer 206 includes Au-Au bonding, Au-Sn bonding, Au-In bonding, Ti-Ti bonding, Cu-Cu bonding, or combinations thereof. For example, if Au-Au bonding is chosen, the two Au layers require a Cr coating as an adhesive layer and a Pt coating as an anti-diffusion layer, respectively. The Pt coating is located between the Au layer and the Cr layer. The Cr layer and the Pt layer are located at the top and bottom of the two bonded Au layers. In some embodiments, when the two Au layers are of approximately the same thickness, the Au on the two layers diffuses into each other under high pressure and high temperature, bonding the two layers together. Eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding are exemplary techniques that can be used.

[0071] In some embodiments, the LED chip structure 200 may include a pixel driver integrated circuit (IC) integrated in a wafer 207. The wafer 207 may contain silicon as a carrier material with high thermal conductivity, which can promote heat dissipation and provide low thermal expansion.

[0072] In some embodiments, the LED chip structure 200 further includes at least one isolation element 202, similar to the one described above. Figure 1 Explanation of isolation element 102. (e.g.) Figure 2 As shown, in some embodiments, the isolation element 202 may include one or more upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) and one or more lower isolation portions 205 (e.g., lower isolation portions 205a and 205b). For example, as Figure 2 As shown, the isolation element 202 includes an upper isolation portion 204a and a lower isolation portion 205a. In some embodiments, the upper isolation portion 204a and the lower isolation portion 205a are integrally formed as a single component, such as... Figure 2As shown. The lower isolation portion 205a is located in the substrate 208, for example, in the region of the bonding metal layer 206. The upper isolation portion 204a protrudes from the surface of the substrate 208, for example, from the top surface of the bonding metal layer 206, and is located on top of the lower isolation portion 205a.

[0073] In one embodiment, the respective upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) may be electrically connected to each other, for example, by using a conductive material or by extending the respective upper isolation portions to make them contact or overlap each other. In another embodiment, the respective upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) may be isolated from each other, for example, by utilizing a buffer space disposed between adjacent upper isolation portions.

[0074] In some embodiments, the LED chip structure 200 further includes one or more mesa 201 (e.g., mesa 201a, 201b, and 201c) surrounded by isolation elements 202, similar to those described above. Figure 1 The explanation. For example, as... Figure 2 As shown, mesa 201b is surrounded by isolation elements 202, such as upper isolation portions 204a and 204b and lower isolation portions 205a and 205b. Each mesa 201 can be located on the substrate 208, for example, on the bonding metal layer 206, and can be driven individually or collectively by the pixel driver IC.

[0075] In some embodiments, the mesa 201 can be electrically connected to the wafer 207 via a bonding metal layer 206. For example, although Figure 2 Not shown, but the p-electrode of mesa 201 and the output of the driving transistor can be located below mesa 201 and electrically connected via bonding metal layer 206. Mesa current drive signal connections (between the p-electrode of the mesa and the output of the pixel driver), ground connections (between the n-electrode and system ground), Vdd connections (between the source of the pixel driver and system Vdd), and control signal connections to the pixel driver gate are made according to various embodiments, such as those described in U.S. Patent Application Serial No. 15 / 135,217 (U.S. Publication No. 2017 / 0179192), entitled "Semiconductor Devices with Integrated Thin-Film Transistor Circuitry," which is incorporated herein by reference.

[0076] The mesa 201 can be an LED or microLED that produces widely diffused light. For example, the mesa 201b can be a single LED or microLED, or a group of LEDs or microLEDs. In one embodiment, the amount of light emitted from the sidewalls of the mesa 201 is greater than the amount of light emitted from the top of the mesa 201. This can result in a wide-spreading emitted light with a large angular range in the far field, potentially up to 180 degrees, which can cause inter-pixel crosstalk. The isolation element 202 can suppress inter-pixel crosstalk. In some embodiments, such as Figure 2 As shown, the mesa 201b is surrounded by upper isolation portions 204a and 204b and lower isolation portions 205a and 205b. The isolation element 202 can be used as an optical isolator to isolate at least a portion of the light emitted by the mesa 201b. For example, a portion of the light emitted by the mesa 201b can be isolated by the upper isolation portions 204a and 204b, thereby preventing light emitted by the mesa 201a and / or 201c from irradiating the light emitted by the mesa 201b.

[0077] In some embodiments, the LED chip structure 200 further includes one or more reflective layers 203 (e.g., reflective layers 203a, 203b, and 203c), similar to those described above. Figure 1 As explained. Each reflective layer 203 is disposed on one or more sidewalls of one or more upper isolation portions of the isolation element 202. For example, as Figure 2 As shown, a reflective layer 203b is disposed on the sidewall of the upper isolation portion 204a, and a reflective layer 203b is also disposed on the sidewall of the upper isolation portion 204b. In some embodiments, each reflective layer 203, including the bottom of each reflective layer, does not directly contact each mesa 201. For example, the bottom of the reflective layer 203b does not contact or directly contacts the mesa 201b, or other mesa 201a and 201c. The reflective layer 203 can be used as a passive optical device to reflect a portion of the light emitted by the mesa 201. For example, light emitted by the mesa 201b can reach the reflective layer 203b and be reflected upward by the reflective layer 203b, thereby reducing the divergence of the light emitted by the mesa 201b.

[0078] In some embodiments, the reflective layer 203 is disposed on one or more sidewalls of one or more upper isolation portions 204 and / or on the top surface of one or more upper isolation portions 204. For example, as Figure 2As shown, reflective layer 203b can be disposed on the sidewalls of upper isolation portions 204a and 204b, and reflective layers 203d and 203e can be disposed on upper isolation portions 204a and 204b, respectively. The bottom of reflective layer 203 extends from isolation element 202 to the table surface. For example, the bottom of reflective layer 203b extends from upper isolation portions 204a and 204b to table surface 201b. In one embodiment, reflective layers 203a-203e can be identical reflective layers formed using the same materials and processes.

[0079] In some embodiments, the reflective layer 203 may include one or more metallic conductive materials that have a high reflectivity to light emitted by the LED chip structure 200. In some embodiments, the high reflectivity is 70% or higher. In some embodiments, the high reflectivity is 80% or higher. In some embodiments, the high reflectivity is 90% or higher. In these embodiments, the one or more metallic conductive materials may include one or more of aluminum, gold, or silver. In some embodiments, the reflective layer 203 may be prepared by one or more electron beam deposition or sputtering processes.

[0080] In some embodiments, the LED chip structure 200 further includes one or more dielectric layers 209 (e.g., dielectric layers 209a, 209b, and 209c). Each dielectric layer 209 may be located above the top surface of a portion of the bonding metal layer 206, between mesa 201, and at the bottom of the sidewall of each mesa 201. For example, for a display panel with 5000 PPI, the width of the portion of the top surface of the bonding metal layer 206 located at one side end of the bottom of the mesa 201 is 0.55 μm. And the bottom portion of the dielectric layer 209 above the top surface of the portion of the bonding metal layer 206 is covered by the bottom portion of each reflective layer 203. For example, as... Figure 2 As shown, dielectric layer 209b is disposed above the top surface of the bonding and metal layer 206b portions, located between mesa 201 and at the bottom of the sidewalls of mesa 201b. The bottom portion of dielectric layer 209b above the top surface of the bonding metal layer 206b portions is covered by the bottom portion of each reflective layer 203b. In some embodiments, dielectric layer 209 can be prepared by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering.

[0081] In some embodiments, each dielectric layer 209 may further cover the top surface and sidewalls of each mesa 201; however, the top surface of each mesa 201 may include areas not covered by the corresponding dielectric layer, i.e., areas without a dielectric layer. For example, as Figure 2As shown, dielectric layer 209b covers the sidewalls and top surface of mesa 201b. The top surface of mesa 201b includes areas or openings not covered by dielectric layer 209b. Using dielectric layer 209b ensures that the bottom of each reflective layer 203 does not directly contact mesa 201b.

[0082] In some embodiments, dielectric layer 209 may be transparent. In some embodiments, dielectric layer 209 is transparent to light emitted by LED chip structure 200. In some embodiments, dielectric layer 209 may include one or more of silicon-containing dielectric layers, aluminum-containing dielectric layers, or titanium-containing dielectric layers. In these embodiments, for dielectric layer 209, silicon-containing dielectric layer may include silicon oxide or nitride, aluminum-containing dielectric layer may include aluminum oxide, and titanium-containing dielectric layer may include titanium oxide. In one embodiment, for dielectric layer 209, titanium oxide is Ti3O5.

[0083] In some embodiments, the LED chip structure 200 further includes at least one conductive layer 210. The top surface and sidewalls of each mesa 201 and the top surface and sidewalls of each upper isolation portion 204 are covered by the conductive layer 210. For example, as Figure 2 As shown, the conductive layer 210 directly or indirectly covers the top surface and sidewalls of the upper isolation portions 204a and 205a, as well as the top surface and sidewalls of the mesa 201b. In some embodiments, the conductive layer 210 is transparent. In some embodiments, the conductive layer 210 is transparent to the light emitted by the LED chip structure 200. In some embodiments, the conductive layer 210 may include a transparent conductive oxide (TCO) layer containing one or more of indium tin oxide (ITO) or ZnO.

[0084] In some embodiments, the conductive layer 210 can be prepared by one or more of thermal evaporation or sputtering processes. The conductive layer 210 can be prepared before or after the formation of the reflective layer 203, provided that the current in the conductive layer 210, such as the current for the N-electrode, can be rapidly and uniformly distributed through the reflective layer 203. For example, the conductive layer 210 can be prepared on top of the reflective layer 203 (e.g., Figure 2 (as shown) or covered by reflective layer 203 (such as) Figure 3 (As shown). In some embodiments, the dielectric layer 209 may be fabricated before or after the formation of the isolation element 202, provided that both the isolation element 202 and the conductive layer 210 are insulated from the bonding metal layer 206. For example, the N-electrode current within the conductive layer 210 and the reflective layer 203 may be insulated from the bonding metal layer 206 connected to the P-electrode. The conductive layer 210 may, for example, conduct current between the mesa 201b and the system Vdd.

[0085] As described above, when the isolating element 202 is higher than the mesa 201, the isolating element 202 can isolate light emitted from one mesa (e.g., mesa 201a) from light emitted from another mesa (e.g., mesa 201b). In some embodiments, for the isolating element 202, the height of each upper isolating portion 204 is determined to be the distance from the top surface of the upper isolating portion 204 to the top surface of the bonding metal layer 206. In some embodiments, for the isolating element 202, the height of each lower isolating portion 205 is determined to be the distance from the bottom surface of the lower isolating portion 205 to the top surface of the bonding metal layer 206. In some embodiments, for the isolating element 202, the height of the upper isolating portion 204 may be higher than the height of the lower isolating portion 205. For example, as... Figure 2 As shown, the height of the upper isolation portion 204a is higher than the height of the lower isolation portion 205a. In other embodiments, the height of the upper isolation portion 204a may be the same as or lower than the height of the lower isolation portion 205a. Furthermore, the heights of the various upper isolation portions may be different. For example, the height of the upper isolation portion 204a may be different from the height of the upper isolation portion 204b. The heights of the various lower isolation portions 205a may also be different. For example, the height of the lower isolation portion 205a may be different from the height of the lower isolation portion 205b.

[0086] In some embodiments, for the isolation element 202, the bottom width of each upper isolation portion 204 may be equal to or greater than the top width of each lower isolation portion 205. For example, as Figure 2 As shown, the bottom width of the upper isolation portion 204a can be equal to or greater than the top width of the lower isolation portion 205b. For example, for a 5000 PPI display panel, the bottom width of the upper isolation portion 204b is approximately 1.7 μm, the top width of the lower isolation portion 205b is approximately 1.2 μm, and the bottom width of the lower isolation portion 205b is approximately 0.3 μm. In these embodiments, there is a difference between the bottom width of the upper isolation portion 204a and the top width of the lower isolation portion 205a, thus forming two protrusions at the bottom of the upper isolation portion 204a. The bottom width of the upper isolation portion 204a can exceed the top width of the lower isolation portion 205a, but the excess portion is less than the top width of the lower isolation portion 205a. The total bottom width of the upper isolation portion 204a is greater than the top width of the lower isolation portion 204a but less than twice the top width of the lower isolation portion 204a. In some embodiments, the width of each of the two protrusions can be different. For example, the width of the protrusion on the bottom left side of the upper isolation portion 204a is different from the width of the protrusion on the bottom right side of the upper isolation portion 204a. For example, for a display panel with 5000 PPI, the width of the protrusion on the bottom left side of the upper isolation portion 204a is approximately 0.2 μm.

[0087] In some embodiments, for the isolation element 202, the cross-section of each upper isolation portion 204 is trapezoidal and the cross-section of each lower isolation portion 205 is an inverted trapezoid, and the bottom of each upper isolation portion 204 covers the top of each lower isolation portion 205. In some embodiments, the area of ​​the bottom of the upper isolation portion 204 is larger than the area of ​​the top of the lower isolation portion 205. For example, as... Figure 2 As shown, the upper isolation portion 204a has a trapezoidal cross-section, and the lower isolation portion 205a has an inverted trapezoidal cross-section. The bottom of the upper isolation portion 204a covers the top of the lower isolation portion 205a. Furthermore, the trapezoid and the inverted trapezoid can be isosceles or right-angled. For example, the upper isolation portion 204a is a trapezoid, and the lower isolation portion 205a is an inverted trapezoid; both can be isosceles. In other embodiments, the upper isolation portion (e.g., upper isolation portion 204a) and the corresponding lower isolation portion (e.g., lower isolation portion 205a) can be axisymmetric and / or coaxial.

[0088] In some embodiments, the height of each upper isolation portion 204 relative to the surface of the bonding metal layer 206 may be greater than the height of each mesa 201 relative to the surface of the bonding metal layer 206. In some embodiments, the tilt angle of the sidewall of each upper isolation portion 204 relative to an axis orthogonal to the surface of the wafer 207 may be greater than the tilt angle of the sidewall of each mesa 201 relative to an axis orthogonal to the surface of the wafer 207.

[0089] For example, such as Figure 2 As shown, the height of the upper isolation portion 204a relative to the surface of the bonding metal layer 206 can be higher than the height of the mesa 201b relative to the surface of the bonding metal layer 206. The height of the upper isolation portion 204a can also be higher than the other mesa 201s (i.e., mesa 201a and 201c). Additionally, as... Figure 2 As shown, the tilt angle α of the sidewall of the upper isolation portion 204a relative to the top surface of the bonding metal layer 206 can be less than 90°, and the tilt angle β of the sidewall of the mesa 201a relative to the top surface of the bonding metal layer 206 can be less than 90°. The tilt angle α of the sidewall of the upper isolation portion 204a can be less than the tilt angle β of the sidewall of the mesa 201a. In some embodiments, the tilt angle β of the sidewall of the mesa 201a can be greater than 45°, while the tilt angle α of the sidewall of the upper isolation portion 204a can be less than 45°.

[0090] In some embodiments, the isolation element 202 includes a dielectric material, such as silicon oxide. In some embodiments, the isolation element 202 includes a photosensitive dielectric material. In some embodiments, the photosensitive dielectric material includes SU-8 or photosensitive polyimide (PSPI). In other embodiments, the isolation element 202 includes a photoresist. However, in some embodiments, the isolation element 202 can be produced by a photolithography process.

[0091] The LED chip structure 200 can increase the overall collimation of the light produced by the mesa 201. A well-collimated beam (such as a beam emitted from the top of the mesa) will not strike the isolating element 202 and will exit the LED chip structure 200 without being redirected by the isolating element 202. Conversely, a poorly collimated beam (such as a beam emitted from the sidewall of the mesa 201) will strike the isolating element 202 and be redirected to a more collimated direction, including the same direction as the beam emitted from the top of the mesa 201. Therefore, the divergence angle is reduced, and the overall collimation of the light produced by the mesa 201, including in the forward direction (vertical direction of the LED chip surface), is improved. The luminous efficiency and brightness of the LED chip structure 200 at small angles are also enhanced.

[0092] Figure 3 A cross-sectional view of an LED chip structure 300 according to some exemplary embodiments is shown. In some embodiments, the cross-section of the LED chip structure 300 is along... Figure 1 The AA line in the figure is cut off. As shown in the figure, in some embodiments, the LED chip structure 300 includes a substrate 308, which includes a wafer 307 and one or more bonding metal layers 306 located on the wafer 307. Each bonding metal layer (e.g., bonding metal layers 306a, 306b, and 306c) may be formed on the wafer 307. The material and structure of the bonding metal layer 306 are similar to Figure 2 The bonding metal layer 206 is described in the figure. In some embodiments, the LED chip structure 300 may include a pixel driver IC integrated in a wafer 307. The wafer 307 may contain silicon as a carrier material with high thermal conductivity, which facilitates heat dissipation and achieves low thermal expansion.

[0093] In some embodiments, the LED chip structure 300 further includes at least one isolation element 302, similar to the one described above. Figure 1 Explanation of isolation element 102. (e.g.) Figure 3 As shown, in some embodiments, the isolation element 302 may include one or more upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) and one or more lower isolation portions 305 (e.g., lower isolation portions 305a and 305b). For example, as Figure 3 As shown, the isolation element 302 includes an upper isolation portion 304a and a lower isolation portion 305a. In some embodiments, such as Figure 3 As shown, the upper isolation portion 304a and the lower isolation portion 305a are integrally formed into one component. The lower isolation portion 305a is located in the substrate 308, for example, in the region of the bonding metal layer 306. The upper isolation portion 304a protrudes from the surface of the substrate 308, for example, from the top surface of the bonding metal layer 306, and is located above the lower isolation portion 305a.

[0094] In some embodiments, the isolation element 302 may include a photosensitive dielectric material. In other embodiments, the photosensitive dielectric material may be SU-8 or photosensitive polyimide (PSPI). However, in some embodiments, the isolation element 302 may be produced by a photolithography process. In one embodiment, the upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) may be electrically connected to each other, for example, by utilizing a conductive material or by extending the respective upper isolation portions to contact or overlap each other. In another embodiment, the upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) may be isolated from each other, for example, by utilizing a buffer space disposed between adjacent upper isolation portions.

[0095] In some embodiments, the LED chip structure 300 further includes one or more mesa 301 (e.g., mesa 301a, 301b, and 301c) surrounded by isolation elements 302, similar to those described above. Figure 1 The explanation. For example, as... Figure 3 As shown, the mesa 301b is surrounded by isolation elements 302, such as upper isolation portions 304a and 304b and lower isolation portions 305a and 305b. The mesa 301b may be located on the substrate 308, for example, on the bonding metal layer 306, and may be driven individually or collectively by the pixel driver IC.

[0096] In some embodiments, the mesa 301 can be electrically connected to the wafer 307 via a bonding metal layer 306. For example, although Figure 3 Not shown, but the p-electrode of mesa 301 and the output of the driving transistor can be located below mesa 301 and electrically connected via bonding metal layer 306. Mesa 301 can be an LED or microLED that produces widely diffused light. For example, mesa 301b can be a single LED or microLED, or a group of LEDs or microLEDs. Isolation element 302 can suppress inter-pixel crosstalk. In some embodiments, such as Figure 3 As shown, the mesa 301b is surrounded by upper isolation portions 304a and 304b and lower isolation portions 305a and 305b. The isolation element 302 can be used as an optical isolator to isolate a portion of the light emitted by the mesa 301b. For example, a portion of the light emitted by the mesa 301b can be isolated by the upper isolation portions 304a and 304b, thereby suppressing inter-pixel optical crosstalk.

[0097] In some embodiments, the LED chip structure 300 further includes one or more dielectric layers 309 (e.g., dielectric layers 309a, 309b, and 309c). Each dielectric layer 309 may be located above a portion of the top surface of the bonding metal layer 306, between mesa 301, and at the bottom of each mesa 301 sidewall. For example, for a display panel with 5000 PPI, the width of the portion of the top surface of the bonding metal layer 306 located at the bottom side of the mesa 301 is 0.55 μm. Furthermore, the bottom portion of the dielectric layer 309 above the portion of the top surface of the bonding metal layer 306 is covered by the bottom portion of each conductive layer 310, as described below.

[0098] In some embodiments, each dielectric layer 309 may cover the top surface and sidewalls of each mesa 301; however, the top surface of each mesa 301 may include areas not covered by the corresponding dielectric layer. For example, as Figure 3 As shown, dielectric layer 309b covers the sidewalls of mesa 301b and a portion of the top surface of mesa 301b. Additionally, the top surface of mesa 301b includes areas or openings not covered by dielectric layer 309b. Using dielectric layer 309 ensures that the bottom of conductive layer 310 or each reflective layer 303 does not directly contact mesa 301. In some embodiments, dielectric layer 309 can be produced by one or more of CVD, ALD, or sputtering processes.

[0099] In some embodiments, dielectric layer 309 may be transparent. In some embodiments, dielectric layer 309 is transparent to light emitted by LED chip structure 300. In some embodiments, dielectric layer 309 may include one or more of silicon-containing dielectric layers, aluminum-containing dielectric layers, or titanium-containing dielectric layers. In these embodiments, for dielectric layer 309, silicon-containing dielectric layers may include silicon oxide or nitride, aluminum-containing dielectric layers may include aluminum oxide, and titanium-containing dielectric layers may include titanium oxide. In other embodiments, titanium oxide may be Ti3O5.

[0100] In some embodiments, the LED chip structure 300 further includes at least one conductive layer 310. For example... Figure 3 As shown, the conductive layer 310 covers the dielectric layer 309, the top surface of each mesa 301 including the area not covered by the dielectric layer 309, and the sidewalls of each upper isolation portion 304 (e.g., upper isolation portions 304a and 304b). In some embodiments, such as Figure 3As shown, the conductive layer 310 covers the top surface and sidewalls of the upper insulating portions 304a and 304b, as well as the top surface and sidewalls of various mesa such as mesa 301b. In some embodiments, the conductive layer 310 is transparent. In some embodiments, the conductive layer 310 is transparent to the light emitted by the LED chip structure 300. In some embodiments, the conductive layer 310 may include a transparent conductive oxide (TCO) layer containing one or more of indium tin oxide (ITO) or ZnO.

[0101] In some embodiments, the conductive layer 310 can be prepared by one or more of thermal evaporation or sputtering processes. The conductive layer 310 can be prepared before or after the formation of the reflective layer 303, provided that the current in the conductive layer 310, such as the current used for the N-electrode, can be rapidly and uniformly distributed through the reflective layer 303. For example, the conductive layer 310 can be prepared on top of the reflective layer 303 (e.g., Figure 2 (as shown) or covered by reflective layer 303 (such as) Figure 3 (As shown). In some embodiments, the dielectric layer 309 may be prepared before or after the isolation element 302 is formed, as long as the isolation element 302 and the conductive layer 310 are insulated from the bonding metal layer 306. For example, the N-electrode current in the conductive layer 310 and the reflective layer 303 is insulated from the bonding metal layer 306 connected to the P-electrode. The conductive layer 310 may, for example, conduct current between the mesa 301b and the system Vdd.

[0102] In some embodiments, the LED chip structure 300 further includes one or more reflective layers 303 (e.g., reflective layers 303a, 303b, and 303c), similar to those described above. Figure 1 As explained. Each reflective layer 303 is disposed on at least one or more sidewalls of one or more upper isolation portions 304 of the isolation element 302, and the bottom of each reflective layer 303 may not contact the table surface 301. For example, as Figure 3 As shown, a reflective layer 303b is disposed on the sidewall of the upper isolation portion 304a and the sidewall of the upper isolation portion 304b. In some embodiments, each reflective layer 303, including its bottom, does not directly contact each mesa 301. The bottom of the reflective layer 303b may not contact or may not directly contact the mesa 301b. The reflective layer 303 can be used as a passive optical device to reflect a portion of the light emitted by the mesa 301. For example, light emitted by the mesa 301b can reach the reflective layer 303b and be reflected upwards by the reflective layer 303b, thereby reducing the divergence of the light emitted by the mesa 301b and enhancing brightness and luminous efficiency.

[0103] In some embodiments, the reflective layer 303 may include one or more metallic conductive materials having a high reflectivity to light emitted by the LED chip structure 300. In some embodiments, the high reflectivity is 70% or higher. In some embodiments, the high reflectivity is 80% or higher. In some embodiments, the high reflectivity is 90% or higher. In these embodiments, the one or more metallic conductive materials may include one or more of aluminum, gold, or silver. In some embodiments, the reflective layer 303 may be prepared by one or more of electron beam deposition or sputtering processes.

[0104] In some embodiments, the conductive layer 310 may be disposed on the top surface and sidewalls of each upper isolation portion 304 (e.g., upper isolation portions 304a and 304b), and the reflective layer may be disposed on the conductive layer disposed on the top surface and sidewalls of each upper isolation portion. For example, as Figure 3 As shown, the top surfaces and sidewalls of the upper isolation portions 304a and 304b are covered by a conductive layer 310, and a reflective layer further covers the conductive layer 310 covering the top surfaces and sidewalls of the upper isolation portions 304a and 304b. In some embodiments, the bottom of each reflective layer 303 can extend from the isolation element 302 to the corresponding mesa. For example, as Figure 3 As shown, the bottom of the reflective layer 303b extends from the upper isolation portions 304a and 304b of the isolation element 302 to the platform 301b.

[0105] As described above, due to its height, the isolation element 302 can isolate the light emitted from mesa 301a and / or 301c from the light emitted from mesa 301b. In some embodiments, for the isolation element 302, the height of each upper isolation portion 304 is determined as the distance from the top surface of the upper isolation portion 304 to the top surface of the bonding metal layer 306. In some embodiments, for the isolation element 302, the height of each lower isolation portion 305 is determined as the distance from the bottom surface of the lower isolation portion 305 to the top surface of the bonding metal layer 306. In some embodiments, for the isolation element 302, the height of the upper isolation portion 304 may be greater than the height of the lower isolation portion 305. For example, as... Figure 3 As shown, the height of the upper isolation portion 304a is higher than the height of the lower isolation portion 305a. In other embodiments, the height of the upper isolation portion 304a may be the same as or lower than the height of the lower isolation portion 305a. Furthermore, the heights of the various upper isolation portions may be different. For example, the height of the upper isolation portion 304a may be different from the height of the upper isolation portion 304b. The heights of the various lower isolation portions 305a may also be different from each other. For example, the height of the lower isolation portion 305a may be different from the height of the lower isolation portion 305b.

[0106] In some embodiments, for the isolation element 302, the bottom width of each upper isolation portion 304 may be equal to or greater than the top width of each lower isolation portion 305. For example, as Figure 3 As shown, the bottom width of the upper isolation portion 304a can be equal to or greater than the top width of the lower isolation portion 305b. For example, for a 5000 PPI display panel, the bottom width of the upper isolation portion 304b is approximately 1.7 μm, the top width of the lower isolation portion 305b is approximately 1.2 μm, and the bottom width of the lower isolation portion 305b is approximately 0.3 μm. In these embodiments, there is a difference between the bottom width of the upper isolation portion 304a and the top width of the lower isolation portion 305a, thus forming two protrusions at the bottom of the upper isolation portion 304a. The bottom width of the upper isolation portion 304a can exceed the top width of the lower isolation portion 305a, but the excess portion is less than the top width of the lower isolation portion 305a. The total bottom width of the upper isolation portion 304a is greater than the top width of the lower isolation portion 304a but less than twice the top width of the lower isolation portion 304a. In some embodiments, the width of each of the two protrusions can be less than half the top width of the lower isolation portion 304a. In other embodiments, the width of each of the two protrusions can be different. For example, the width of the left protrusion at the bottom of the upper isolation portion 304a is different from the width of the right protrusion at the bottom of the upper isolation portion 304a. For example, for a display panel with 5000 PPI, the width of the left protrusion at the bottom of the upper isolation portion 304a is approximately 0.2 μm.

[0107] In some embodiments, for the isolation element 302, the cross-section of each upper isolation portion 304 is trapezoidal and the cross-section of each lower isolation portion 305 is an inverted trapezoid, and the bottom of each upper isolation portion 304 covers the top of each lower isolation portion 305. In some embodiments, the area of ​​the bottom of the upper isolation portion 304 is larger than the area of ​​the top of the lower isolation portion 305. For example, as... Figure 3 As shown, the upper isolation portion 304a has a trapezoidal cross-section, and the lower isolation portion 305a has an inverted trapezoidal cross-section. The bottom of the upper isolation portion 304a covers the top of the lower isolation portion 305a. Furthermore, the trapezoid and the inverted trapezoid can be isosceles or right-angled. For example, the upper isolation portion 304a is a trapezoid, and the lower isolation portion 305a is an inverted trapezoid; both can be isosceles. In other embodiments, the upper isolation portion (e.g., upper isolation portion 304a) and the corresponding lower isolation portion (e.g., lower isolation portion 305a) can be axisymmetric and / or coaxial.

[0108] In some embodiments, the height of each upper isolation portion 304 relative to the surface of the bonding metal layer 306 may be greater than the height of each mesa 301 (e.g., mesa 301a, 301b, and 301c) relative to the surface of the bonding metal layer 306, and the tilt angle of the sidewall of each upper isolation portion 304 relative to an axis orthogonal to the surface of the wafer 307 may be greater than the tilt angle of the sidewall of each mesa 301 (e.g., mesa 301a, 301b, and 301c) relative to an axis orthogonal to the surface of the wafer 307.

[0109] For example, such as Figure 3 As shown, the height of the upper isolation portion 304a relative to the surface of the bonding metal layer 306 can be higher than the height of the mesa 301b relative to the surface of the bonding metal layer 306. The height of the upper isolation portion 304a can also be higher than the other mesa 301s (i.e., mesa 301a and 301c). Additionally, as... Figure 3 As shown, the inclination angle α of the sidewall of the upper isolation portion 304a relative to the top surface of the bonding metal layer 306 can be less than 90°, and the inclination angle β of the sidewall of the mesa 301a relative to the top surface of the bonding metal layer 306 can be less than 90°. The inclination angle α of the sidewall of the upper isolation portion 304a can be less than the inclination angle β of the sidewall of the mesa 301a. In some embodiments, the inclination angle β of the sidewall of the mesa 301a can be greater than 45°, while the inclination angle α of the sidewall of the upper isolation portion 304a can be less than 45°.

[0110] Figure 1 , Figure 2 and Figure 3 Only LED chip structures according to some embodiments are shown. In other embodiments, the LED chip structure may include a different number of mesa 101 and / or a different number of reflective layers 103. In other embodiments, each mesa 101 may include multiple individual light elements, such as multiple LEDs or microLEDs connected in parallel or stacked one-to-one. In other embodiments, the mesa 101 may not be circular in top view. In other embodiments, the sidewalls of the isolating element 102 surrounding each mesa 101 may not be circular in top view. That is, the isolating element 102 surrounding the sidewalls of each mesa 101 may have other shapes in top view, including but not limited to triangles, squares, rectangles, pentagons, hexagons, and octagons. In other embodiments, the isolating element 102 may include multiple individual or isolated sub-elements, each sub-element may surround a mesa. Buffer spaces may be created between multiple individual or isolated sub-elements.

[0111] Figure 4A cross-sectional view of a reflective layer 400 having a multilayer structure is shown according to some exemplary embodiments. For the LED chip structure described above, the reflective layer 400 may include a multilayer structure. The multilayer structure may include a stack of one or more reflective material layers and one or more dielectric material layers. In one exemplary embodiment, as... Figure 4 As shown, the reflective layer 400 includes a multilayer structure comprising a reflective material layer 401 and a dielectric material layer 402. In other embodiments, the multilayer structure may include two reflective material layers and a dielectric material layer located between the two reflective material layers. However, in some other embodiments, the multilayer structure may also include two dielectric material layers and a reflective material layer located between the two dielectric layers. In some embodiments, the multilayer structure may include two or more metal layers. For example, the metal layers may include one or more of TiAu, CrAl, or TiWAg.

[0112] In some embodiments, the multilayer structure may be a multilayer omnidirectional reflector (ODR), including a metal layer and a transparent conductive oxide (TCO). For example, the multilayer structure may include a dielectric material layer, a metal layer, and a TCO layer. In some embodiments, the multilayer structure may include two or more dielectric material layers, which are alternately arranged to form a distributed Bragg reflector (DBR). For example, the multilayer structure may include a dielectric material layer, a metal layer, and a transparent dielectric layer. The transparent dielectric layer may include one or more of SiO2, Si3N4, or Al2O3. The multilayer structure may also include a dielectric material layer, a TCO, and a DBR. In other embodiments, the reflective layer 400 may include one or more metallic conductive materials with high reflectivity. In some embodiments, the high reflectivity is above 70%. In some embodiments, the high reflectivity is above 80%. In some embodiments, the high reflectivity is above 90%. In these embodiments, the one or more metallic conductive materials may include one or more of aluminum, gold, or silver.

[0113] The foregoing description of the disclosed embodiments is provided to enable making or using the embodiments and variations thereof described herein. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

[0114] According to one or more embodiments of this disclosure, different types of display panels can be manufactured. For example, the resolution of display panels can typically range from 8×8 to 3840×2160. Common display resolutions include QVGA with a resolution of 320×240 and an aspect ratio of 4:3, XGA with a resolution of 1024×768 and an aspect ratio of 4:3, D with a resolution of 1280×720 and an aspect ratio of 16:9, FHD with a resolution of 1920×1080 and an aspect ratio of 16:9, UHD with a resolution of 3840×2160 and an aspect ratio of 16:9, and 4K with a resolution of 4096×2160. A wide variety of pixel sizes are also possible, ranging from submicron and below to 10mm and above. The overall display area size can also vary widely, ranging from diagonal sizes as small as tens of micrometers or smaller to hundreds of inches or larger.

[0115] Example applications include displays for home / office projectors and portable electronics such as smartphones, laptops, wearable devices, light engines for AR and VR glasses, and retinal projection. Power consumption can range from as low as a few milliwatts for retinal projectors to up to kilowatts for large-screen outdoor displays, projectors, and smart car headlights. In terms of frame rate, due to the fast response (nanosecond level) of inorganic LEDs, frame rates can reach the kHz level, or even the MHz level for low resolutions.

[0116] The features of this invention can be implemented using a computer program product or with the aid of a computer program product, such as a storage medium (of various media) or a computer-readable storage medium (of various media), wherein instructions are stored thereon or thereon, which can be used to program a processing system to perform any of the features presented herein. The storage medium may include, but is not limited to, high-speed random access memory, such as DRAM, SRAM, DDRRAM, or other random access solid-state memory devices, and may include non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state memory devices. The memory may optionally include one or more storage devices located remotely from the CPU. The non-volatile memory devices within the memory, or optionally within the memory, include non-transitory computer-readable storage media.

[0117] Features of the invention, stored on any machine-readable medium (of various kinds), can be contained in software and / or firmware for controlling the hardware of a processing system and enabling the processing system to interact with other entities using the results of the invention. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.

[0118] It should be understood that although this article may use terms such as “firstly” and “secondly” to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0119] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the appended claims, the singular forms “a,” “an,” and “this” are intended to include multiple forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It should also be understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of said features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups.

[0120] As used herein, the term "if" can be interpreted as meaning, depending on the context, that the prerequisite of a statement is true "in the case of," "when," or "in response to detection." Similarly, the phrases "if it is determined that [the prerequisite of that statement is true]," "if [the prerequisite of the statement is true]," or "when [the prerequisite of the statement is true]" can be interpreted as meaning, depending on the context, that the stated prerequisite is true "when determined," "in response to determined," "according to determined," "when detected," or "in response to detection."

[0121] The foregoing description, used for illustration, has been described with reference to specific embodiments. However, the foregoing illustrative discussion is not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations can be made in light of the foregoing teachings. The embodiments were chosen and described in order to best explain the principles of practical application and operation, thereby enabling others skilled in the art to best utilize the invention and its various embodiments.

Claims

1. A light-emitting diode (LED) chip structure, comprising: substrate; An isolation element includes an upper isolation portion and a lower isolation portion, wherein the lower isolation portion is located in the substrate, and the upper isolation portion protrudes from the surface of the substrate; The tabletop includes LED components and is surrounded by the isolation element. The height of the upper isolation portion relative to the surface of the substrate is greater than the height of the tabletop relative to the surface of the substrate, and the tilt angle of the sidewall of the upper isolation portion relative to an axis orthogonal to the surface of the substrate is greater than the tilt angle of the sidewall of the tabletop relative to an axis orthogonal to the surface of the substrate. A dielectric layer covers the top surface and sidewalls of the platform, wherein the top surface of the platform includes an area not covered by the dielectric layer; A conductive layer, covering the dielectric layer, the top surface of the platform including the area not covered by the dielectric layer, and at least one sidewall of the upper isolation portion; and A reflective layer is disposed at least on the conductive layer covering the sidewall of the upper insulating portion, wherein the bottom of the reflective layer does not contact the table surface.

2. The LED chip structure according to claim 1, wherein, The conductive layer is disposed on the top surface and the side wall of the upper isolation portion, and the reflective layer is disposed on the conductive layer disposed on the top surface and the side wall of the upper isolation portion, wherein the bottom of the reflective layer extends from the isolation element to the platform.

3. The LED chip structure according to claim 1 or 2, wherein, The height of the upper isolation section is higher than the height of the lower isolation section.

4. The LED chip structure according to claim 1 or 2, wherein, The bottom width of the upper isolation portion is equal to or greater than the top width of the lower isolation portion.

5. The LED chip structure according to claim 4, wherein, The bottom width of the upper isolation portion is greater than the top width of the lower isolation portion but less than twice the top width of the lower isolation portion. Two protrusions are formed at each bottom end of the upper isolation portion, and the width of each of the two protrusions is less than half the top width of the lower isolation portion.

6. The LED chip structure according to claim 5, wherein, In the side view, the cross-section of the upper isolation part is trapezoidal, the cross-section of the lower isolation part is inverted trapezoidal, and the bottom of the upper isolation part covers the top of the lower isolation part.

7. The LED chip structure according to claim 6, wherein, The upper isolation portion and the lower isolation portion are axially symmetric and coaxial.

8. The LED chip structure according to claim 1, wherein, The tilt angle of the sidewall of the tabletop is less than 45°, and the tilt angle of the sidewall of the upper isolation part is greater than 45°.

9. The LED chip structure according to claim 1, 2, or 8, wherein, The dielectric layer is transparent to the light emitted by the LED chip structure.

10. The LED chip structure according to claim 1, 2, or 8, wherein, The dielectric layer includes one or more of the following: a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

11. The LED chip structure according to claim 10, wherein, The silicon-containing dielectric layer comprises silicon oxide or nitride, the aluminum-containing dielectric layer comprises aluminum oxide, and the titanium-containing dielectric layer comprises titanium oxide.

12. The LED chip structure according to claim 11, wherein, The oxide of the titanium is Ti3O5.

13. The LED chip structure according to claim 1, 2, or 8, wherein, The reflective layer comprises a multi-layer structure.

14. The LED chip structure according to claim 13, wherein, The multilayer structure comprises a stack of one or more reflective material layers and one or more dielectric material layers.

15. The LED chip structure according to claim 1, 2, or 8, wherein, The reflective layer comprises one or more metallic conductive materials with a high reflectivity of over 80%.

16. The LED chip structure according to claim 15, wherein, The one or more metallic conductive materials include one or more of aluminum, gold, or silver.

17. The LED chip structure according to claim 1, 2, or 8, wherein, The conductive layer is transparent to the light emitted by the LED chip structure.

18. The LED chip structure according to claim 1, 2, or 8, wherein, The isolation element includes a photosensitive dielectric material.

19. The LED chip structure according to claim 18, wherein, The photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

20. The LED chip structure according to claim 1, 2, or 8, wherein, The substrate includes a semiconductor wafer and a bonding metal layer located on the semiconductor wafer.

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