Domestic dsp core voltage management method, circuit, device and medium

Abstract

The application discloses a domestic DSP core voltage management method, a circuit, equipment and a medium, and belongs to the domestic chip application field, and comprises the following steps: S1, an MSU sets a core voltage to a high voltage by default; S2, a function application program notifies the MSU of whether FFT and DMA will be simultaneously run when being initialized; S3, the MSU monitors whether a DSP chip core voltage needs to be set to a low voltage; if yes, the DSP chip core voltage is set to the low voltage, and S4 is performed; otherwise, S5 is performed; S4, the MSU sets the core voltage to the high voltage, and S6 is performed; S5, the MSU sets the core voltage to the low voltage, and S6 is performed; S6, the MSU collects and compares whether a Feiteng M6678 core voltage is consistent with the set value, and if not, the system is reported to control the Feiteng M6678 core voltage exception through a control bus. The application has the advantages of low power consumption, low cost and high reliability.

Description

Technical Field

[0001] This invention relates to the field of domestic chip applications, and more specifically, to a method, circuit, device, and medium for managing the core voltage of a domestic DSP. Background Technology

[0002] A key characteristic of integrated electronic systems is that most functions are implemented by adding different software to general-purpose hardware modules. Commonly used embedded processors for these general-purpose hardware modules include Field-Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs), and General Purpose Processors (GPPs). FPGAs offer abundant input / output pins and parallel task execution capabilities; DSPs provide efficient data processing and a convenient and flexible debugging and development environment; and GPPs effectively support control-intensive applications that are not digital signal processing-based. Each of these three types of embedded processors has its advantages, running different programs within the integrated system to handle different types of tasks, and their powerful performance is realized through the programs running within them. Currently, integrated electronic information systems mainly include general-purpose data processing modules (DPMs), general-purpose signal processing modules (SPMs), network switching modules (RCMs), system control modules (SCMs), and high-speed large-scale storage modules (MMMs). The functional unit division and design of these modules follow the requirements of a general functional framework. The general functional framework requirements for the modules are as follows: each module consists of a Module Support Unit (MSU), a Processing Unit (PU), a Routing Unit (RU), a Network Interface Unit (NIU), a Power Support Component (PSE), and a Module Physical Interface (MPI), achieving standardized, generalized, and integrated design of the module hardware circuitry. The MSU is a unit present in every hardware module, typically connected to the system control via a control bus. It receives system control commands to perform board-level management tasks such as power-on control, reset control, program loading, program updates, current acquisition, voltage acquisition, temperature acquisition, and health status reporting.

[0003] The Phytium M6678 is a domestically developed DSP completely independently developed by the National University of Defense Technology. Its single-core floating-point theoretical speed reaches 16 GFLOPS, and it features a powerful FFT coprocessor. It is a mainstream DSP chip in current integrated electronic systems, typically used in general-purpose signal processing hardware modules. The Phytium M6678 uses a 28nm process and integrates eight C66x processors with a single-core clock speed of 1Hz. It features peripherals including a DDR3 controller, DMA controller, SRIO interface, EMIF interface, GPIO interface, UART interface, and SPI interface. Its operation requires multiple power supplies for the core, SERDES core, digital I / O, DDR, and SERDES I / O.

[0004] If a functional application deployed on the Phytium M6678 runs both FFT and DMA simultaneously, core voltage instability may occur, leading to DSP malfunction. The Phytium M6678 manufacturer's solution is to increase the core voltage. However, while some functional applications in integrated electronic systems may run both FFT and DMA simultaneously, most applications do not. If the functional application currently loaded on the Phytium M6678 is running both FFT and DMA simultaneously, then increasing the core voltage is necessary. If the functional application currently loaded on the Phytium M6678 is not running both FFT and DMA simultaneously, then increasing the core voltage will result in additional power consumption.

[0005] In integrated electronic systems, the timing and loading of specific application programs are controlled by dynamic loading instructions issued by the system. For general-purpose signal processing hardware modules, they only receive these instructions and execute the program loading operation; they are unaware whether the loaded application program will simultaneously run FFT and DMA. Only the application program developer knows whether FFT and DMA will run concurrently. Hardware module developers can only follow the solution provided by the Phytium M6678 manufacturer: increasing the core voltage of all Phytium M6678 cores that might load applications that run FFT and DMA simultaneously. While this solves the problem of unstable core voltage leading to DSP malfunctions when FFT and DMA are running concurrently, it significantly increases power consumption when loading applications that do not require simultaneous FFT and DMA. This technical problem urgently needs to be solved by those in the field. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a domestic DSP core voltage management method, circuit, device and medium to achieve low power consumption, low cost and high reliability.

[0007] The objective of this invention is achieved through the following solution:

[0008] A domestically developed DSP core voltage management method includes the following steps:

[0009] S1, the power chip corresponding to the core voltage controlled by the MSU will set the core voltage to high voltage by default;

[0010] S2, the functional application will notify the MSU whether FFT and DMA will run simultaneously during initialization;

[0011] S3, MSU monitors whether the DSP chip core voltage needs to be set to low voltage; if so, the DSP chip core voltage needs to be set to low voltage, proceed to step S4; otherwise, proceed to step S5.

[0012] S4, the MSU controls the power chip corresponding to the core voltage to set the core voltage to high voltage, and proceeds to step S6;

[0013] S5, the MSU controls the power chip corresponding to the core voltage to set the core voltage to a low voltage, and proceeds to step S6;

[0014] S6, MSU collects and compares whether the core voltage of Phytium M6678 is consistent with the setting. If they are inconsistent, the system will report the abnormal core voltage of Phytium M6678 through the control bus.

[0015] Furthermore, during initialization, the functional application notifies the MSU whether FFT and DMA will run simultaneously. The notification method is EMIF, and the notification content is 1 if FFT and DMA are running simultaneously, and 0 if FFT and DMA are not running simultaneously.

[0016] Furthermore, the core voltage has a low voltage range of 0.90 to 0.95V and a high voltage range of 1.00 to 1.05V.

[0017] Furthermore, the power chip includes HCE4630ML / MB or a replacement model thereof.

[0018] Furthermore, the control method for the power supply chip corresponding to the core voltage to set the core voltage to high or low voltage is to adjust the resistance value of the resistor RFB added between the VFB pin and GND.

[0019] Furthermore, the resistance adjustment of the RFB is achieved by connecting resistors R1 and R2 in series, with R2 connected in parallel to an electronic switch or electromagnetic relay. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay through a driver chip, controlling the electronic switch or electromagnetic relay to open or close, thereby connecting or removing resistor R2 to the RFB.

[0020] Furthermore, the resistance value of R1 is the resistance value corresponding to high voltage, and the resistance value of R1+R2 is the resistance value corresponding to low voltage.

[0021] A circuit for managing the core voltage of a domestically produced DSP includes a Phytium M6678, an MSU, an electronic switch or electromagnetic relay, resistors R1 and R2, and a power supply chip HCE4630. The Phytium M6678 is connected to the MSU via an EMIF interface. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay. The electronic switch or electromagnetic relay is connected in parallel with resistor R2. Resistors R1 and R2 are connected in series, with one end grounded and the other end connected to the VFB pin of the HCE4630. The output of the HCE4630 is fed into the core voltage pin VDD of the Phytium M6678 and the voltage acquisition pin of the MSU, respectively. When this circuit for managing the core voltage of the domestically produced DSP operates, it follows the domestically produced DSP core voltage management method as described in any one of claims 1 to 7.

[0022] A computer device comprising a processor and a memory, the memory storing a computer program which, when loaded by the processor, executes the method as described in any of the preceding claims.

[0023] A readable storage medium storing a computer program, the computer program being loaded by a processor and executed as described in any of the preceding methods.

[0024] The beneficial effects of this invention include:

[0025] (1) Low power consumption: This invention determines whether to set the core voltage of Phytium M6678 to high voltage based on whether the functional application confirms during initialization whether FFT and DMA will run simultaneously, thus avoiding the additional power consumption caused by uniformly increasing the core voltage of Phytium M6678.

[0026] (2) Low cost: The present invention utilizes the MSU unit, which is present in all hardware modules of the integrated electronic system. The functional application deployed in the Phytium M6678 notifies the MSU whether FFT and DMA will run simultaneously during initialization. The MSU then uses this information to control the connection or removal of the resistor, thereby realizing the generation and switching of two Phytium M6678 core voltages, namely high voltage and low voltage, with almost no cost increase compared to the original design.

[0027] (3) High reliability: The present invention uses the MSU to control the power chip corresponding to the core voltage to set the core voltage to high voltage by default, so that it can work normally even if the setting is forgotten; The present invention uses the MSU to collect and compare whether the core voltage of Phytium M6678 is consistent with the setting. If they are inconsistent, the system will report the abnormal core voltage of Phytium M6678 through the control bus, so that the system can know when the electronic switch or electromagnetic relay fails. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a domestically produced DSP core voltage management method according to an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the domestic DSP core voltage management circuit according to an embodiment of the present invention. Detailed Implementation

[0031] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0032] like Figure 1 As shown, this embodiment of the invention provides a domestic DSP core voltage management method, including the following steps:

[0033] S1, the power chip corresponding to the core voltage controlled by the MSU will set the core voltage to high voltage by default;

[0034] S2, the functional application will notify the MSU whether FFT and DMA will run simultaneously during initialization;

[0035] S3, MSU monitors whether the DSP chip core voltage needs to be set to low voltage; if the DSP chip core voltage needs to be set to low voltage, proceed to step S4; otherwise, proceed to step S5.

[0036] S4, the MSU controls the power chip corresponding to the core voltage to set the core voltage to high voltage, and proceeds to step S6;

[0037] S5, the MSU controls the power chip corresponding to the core voltage to set the core voltage to a low voltage, and proceeds to step S6;

[0038] S6, MSU collects and compares whether the core voltage of Phytium M6678 is consistent with the setting. If they are inconsistent, the system will report the abnormal core voltage of Phytium M6678 through the control bus.

[0039] In an optional scheme, the functional program will notify the MSU whether FFT and DMA will run simultaneously during initialization. The notification method is EMIF, and the notification content is 1 if FFT and DMA are running simultaneously, and 0 if FFT and DMA are not running simultaneously.

[0040] In an optional configuration, the core voltage has a low voltage range of 0.90 to 0.95V and a high voltage range of 1.00 to 1.05V.

[0041] In an optional configuration, the MSU power chip is an HCE4630ML / MB or a replacement model thereof.

[0042] In an optional scheme, the control method for setting the core voltage to high or low voltage by the power supply chip corresponding to the control core voltage is to adjust the resistance value of the added resistor RFB between the VFB pin and GND.

[0043] In an optional scheme, the resistance of RFB is adjusted by connecting resistors R1 and R2 in series, and R2 in parallel with an electronic switch or electromagnetic relay. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay through the driver chip to control the electronic switch or electromagnetic relay to open or close, thereby connecting or removing resistor R2 to RFB.

[0044] In an optional configuration, the resistance of R1 is the resistance value corresponding to high voltage, and the resistance of R1+R2 is the resistance value corresponding to low voltage.

[0045] like Figure 2 The circuit shown is the corresponding circuit for the domestic DSP core voltage management method provided in this embodiment of the invention. It mainly includes a domestic DSP Phytium M6678, a module support unit (MSU), an electronic switch or electromagnetic relay, resistors R1 and R2, and a power supply chip HCE4630. The Phytium M6678 is connected to the MSU via an EMIF interface. The MSU's GPIO is connected to the control terminal of the electronic switch or electromagnetic relay. The electronic switch or electromagnetic relay is connected in parallel with R2. Resistors R1 and R2 are connected in series, with one end (R2 side) grounded and the other end (R1 side) connected to the VFB pin of the HCE4630. The output of the HCE4630 is fed into the core voltage pin VDD of the Phytium M6678 and the MSU voltage acquisition pin, respectively.

[0046] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0047] I. Low Power Consumption: In integrated electronic systems, some functional applications may run FFT and DMA simultaneously, while most functional applications do not. Different functional applications may be loaded each time. If the functional application currently loaded on the Phytium M6678 will run FFT and DMA simultaneously, the core voltage needs to be increased. This invention determines whether to set the Phytium M6678 core voltage to high voltage based on whether the functional application confirms during initialization whether it will run FFT and DMA simultaneously. This avoids the additional power consumption caused by uniformly increasing the core voltage of the Phytium M6678.

[0048] II. Low Cost: For cases where the core voltage only has two options, high voltage and low voltage, this invention adds only one resistor and one electronic switch or electromagnetic relay while retaining the original design. The invention utilizes the MSU unit, which is present in the hardware modules of the integrated electronic system. During initialization, the functional application deployed in the Phytium M6678 notifies the MSU whether FFT and DMA will be running simultaneously. The MSU then uses this information to control the connection or removal of the resistor, thereby realizing the generation and switching of the two Phytium M6678 core voltages, namely high voltage and low voltage. Compared with the original design, there is almost no increase in cost.

[0049] III. High Reliability: To address the possibility that functional applications might forget to configure whether FFT and DMA are running simultaneously, this invention uses the MSU to control the power supply chip corresponding to the core voltage, setting the core voltage to a high voltage by default, ensuring normal operation even if the setting is forgotten. Simultaneously, to address the issue of electronic switches or electromagnetic relays failing, this invention uses the MSU to collect and compare the Phytium M6678 core voltage with the set value. If they do not match, the system is notified of the abnormal Phytium M6678 core voltage via the control bus, ensuring that the system is aware of any failures in electronic switches or electromagnetic relays.

[0050] Example 1

[0051] A domestically developed DSP core voltage management method includes the following steps:

[0052] S1, the power chip corresponding to the core voltage controlled by the MSU will set the core voltage to high voltage by default;

[0053] S2, the functional application will notify the MSU whether FFT and DMA will run simultaneously during initialization;

[0054] S3, MSU monitors whether the DSP chip core voltage needs to be set to low voltage; if so, the DSP chip core voltage needs to be set to low voltage, proceed to step S4; otherwise, proceed to step S5.

[0055] S4, the MSU controls the power chip corresponding to the core voltage to set the core voltage to high voltage, and proceeds to step S6;

[0056] S5, the MSU controls the power chip corresponding to the core voltage to set the core voltage to a low voltage, and proceeds to step S6;

[0057] S6, MSU collects and compares whether the core voltage of Phytium M6678 is consistent with the setting. If they are inconsistent, the system will report the abnormal core voltage of Phytium M6678 through the control bus.

[0058] Example 2

[0059] Based on Example 1, the functional application will notify the MSU whether FFT and DMA will run simultaneously during initialization. The notification method is EMIF, and the notification content is 1 if FFT and DMA are running simultaneously, and 0 if FFT and DMA are not running simultaneously.

[0060] Example 3

[0061] Based on Example 1, the core voltage has a low voltage range of 0.90 to 0.95V and a high voltage range of 1.00 to 1.05V.

[0062] Example 4

[0063] Based on Example 1, the power chip includes HCE4630ML / MB or its alternative model.

[0064] Example 5

[0065] Based on Example 1, the control method for setting the core voltage to high or low voltage by the power chip corresponding to the core voltage is to adjust the resistance value of the added resistor RFB between the VFB pin and GND.

[0066] Example 6

[0067] Based on Example 5, the resistance adjustment of RFB is achieved by connecting resistors R1 and R2 in series, and R2 in parallel with an electronic switch or electromagnetic relay. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay through the driver chip, which controls the electronic switch or electromagnetic relay to open or close, thereby connecting or removing resistor R2 to RFB.

[0068] Example 7

[0069] Based on Example 6, the resistance value of R1 is the resistance value corresponding to high voltage, and the resistance value of R1+R2 is the resistance value corresponding to low voltage.

[0070] Example 8

[0071] A circuit for managing the core voltage of a domestically produced DSP includes a Phytium M6678, an MSU, an electronic switch or electromagnetic relay, resistors R1 and R2, and a power supply chip HCE4630. The Phytium M6678 is connected to the MSU via an EMIF interface. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay. The electronic switch or electromagnetic relay is connected in parallel with resistor R2. Resistors R1 and R2 are connected in series, with one end grounded and the other end connected to the VFB pin of the HCE4630. The output of the HCE4630 is fed into the core voltage pin VDD of the Phytium M6678 and the voltage acquisition pin of the MSU, respectively. When this circuit is in operation, it runs the domestically produced DSP core voltage management method as described in any of Examples 1 to 7.

[0072] Example 9

[0073] A computer device includes a processor and a memory, wherein the memory stores a computer program that is loaded by the processor and executed as described in any one of Embodiments 1 to 7.

[0074] Example 10

[0075] A readable storage medium storing a computer program, the computer program being loaded by a processor and executed as described in any one of Examples 1 to 7.

[0076] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0077] According to one aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various alternative implementations described above.

[0078] In another aspect, this application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

[0079] All parts not covered in this invention are the same as or can be implemented using existing technologies.

[0080] The above technical solution is only one embodiment of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or modifications, and not limited to the methods described in the above specific embodiments of the present invention. Therefore, the methods described above are only preferred and are not restrictive.

[0081] In addition to the examples above, other embodiments may be obtained by those skilled in the art based on the above disclosure or by making modifications using knowledge or technology in related fields. The features of each embodiment may be interchanged or replaced. Modifications and changes made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A domestically produced DSP core voltage management method, characterized in that, Includes the following steps: S1, the module support unit MSU controls the power chip corresponding to the core voltage to set the core voltage to high voltage by default; S2, the functional application will notify the MSU whether FFT and DMA will run simultaneously during initialization; S3, MSU monitors whether the DSP chip core voltage needs to be set to low voltage; if so, set the DSP chip core voltage to low voltage and proceed to step S4; otherwise, proceed to step S5. S4, the MSU controls the power chip corresponding to the core voltage to set the core voltage to high voltage, and proceeds to step S6; S5, the MSU controls the power chip corresponding to the core voltage to set the core voltage to a low voltage, and proceeds to step S6; S6, MSU collects and compares whether the core voltage of Phytium M6678 is consistent with the setting. If they are inconsistent, the system will report the abnormal core voltage of Phytium M6678 through the control bus. During initialization, the application will notify the MSU whether FFT and DMA will run simultaneously. The notification method is EMIF. The notification content is 1 if FFT and DMA are running simultaneously, and 0 if FFT and DMA are not running simultaneously.

2. The domestic DSP core voltage management method according to claim 1, characterized in that, The core voltage has a low voltage range of 0.90~0.95V and a high voltage range of 1.00~1.05V.

3. The domestic DSP core voltage management method according to claim 1, characterized in that, The power chip includes HCE4630ML / MB.

4. The domestic DSP core voltage management method according to claim 1, characterized in that, The power supply chip that controls the core voltage sets the core voltage to high or low voltage by adjusting the resistance value of the resistor RFB added between the VFB pin and GND.

5. The domestic DSP core voltage management method according to claim 4, characterized in that, The resistance of the RFB is adjusted by connecting resistors R1 and R2 in series, and R2 in parallel with an electronic switch or electromagnetic relay. The GPIO of the MSU is connected to the control terminal of the electronic switch or electromagnetic relay through the driver chip, which controls the electronic switch or electromagnetic relay to open or close, thereby connecting or removing resistor R2.

6. The domestic DSP core voltage management method according to claim 5, characterized in that, The resistance value of R1 is the resistance value corresponding to high voltage, and the resistance value of R1+R2 is the resistance value corresponding to low voltage.

7. A circuit for core voltage management of a domestically produced DSP, characterized in that, The circuit includes a Phytium M6678, a Module Support Unit (MSU), an electronic switch or electromagnetic relay, resistors R1 and R2, and a power supply chip HCE4630. The Phytium M6678 is connected to the MSU via an EMIF interface. The MSU's GPIO is connected to the control terminal of the electronic switch or electromagnetic relay. The electronic switch or electromagnetic relay is connected in parallel with resistor R2. Resistors R1 and R2 are connected in series, with one end grounded and the other end connected to the VFB pin of the HCE4630. The output of the HCE4630 is fed into the core voltage pin VDD of the Phytium M6678 and the MSU voltage acquisition pin, respectively. When this domestic DSP core voltage management circuit is in operation, it runs the domestic DSP core voltage management method as described in any one of claims 1 to 6.

8. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded by the processor and executed according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, A computer program is stored in a computer-readable storage medium, the computer program being loaded by a processor and executing the method as described in any one of claims 1 to 6.

Images