Initialization method, equipment and medium for multi-SRIO domestic switching chips

Abstract

The present invention discloses a method, device and medium for initializing multiple SRIO domestic switch chips, which belongs to the field of domestic chip applications and includes the following steps: S1, numbering, sorting and classifying domestic SRIO switch boards; S2, powering on domestic SRIO switch boards with first-class numbers; S3, powering on domestic SRIO switch boards with second-class numbers; S4, determining the port link status; S5, if the link status of a port in the first-class SRIO domestic switch chip is abnormal, then proceeding to S6; if the link status of all ports in the first-class SRIO domestic switch chip is normal, then proceeding to S7; S6, performing a port reset operation on the SRIO domestic switch chip and returning to S4; if the reset number exceeds the upper limit, then proceeding to S7, otherwise returning to S4; S7, reporting the result. The present invention has the advantages of low cost and strong stability.

Description

Technical Field

[0001] The present invention relates to the application field of domestic chips, and more specifically, to a method, device and medium for initializing multi-SRIO domestic switching chips. Background Art

[0002] In embedded system applications, all hardware components are connected via buses. Due to limitations in transmission rates and system topology, traditional interconnect buses are no longer able to meet the demands of ever-increasing processor frequencies and performance. Therefore, in embedded environments, the RapidIO interconnect bus protocol is widely used for inter-chip and inter-board transmission, achieving communication rates ranging from 1Gbps to 60Gbps.

[0003] Currently, integrated electronic information systems primarily consist of general-purpose data processing modules (DPMs), general-purpose signal processing modules (SPMs), network switching modules (RCMs), and I / O modules. The RapidIO interconnect bus protocol is used between chips and boards to achieve highly reliable data transmission. The network switching modules, I / O modules, and data processing modules all utilize one or more domestically produced SRIO switching chips, forming a RapidIO-based network transmission framework.

[0004] Currently, after domestic SRIO switch chips are powered on, serdes parameters need to be configured according to manufacturer requirements. When multiple domestic SRIO switch chips are interconnected and serdes operations are performed simultaneously, there is a certain probability that the link status of the port of the domestic SRIO switch chip on the opposite end will be affected. This status can be determined by checking the RIO Port Error and Status CSR, that is, the status of register 0x158. If the PORT_OK bit of this register is normal, initialization is normal; if the PORT_OK bit is invalid, the link is abnormal. Once the link is abnormal, RapidIO communication between RapidIO nodes will be blocked. The solution proposed by domestic SRIO switch chip manufacturers is to change the initial RapidIO rate of the hardware. After power-on, due to the RapidIO rate mismatch, the link status of the port will not be affected during the serdes operation.

[0005] According to the manufacturer's method for initializing domestic SRIO switch chips, the hardware RapidIO rate needs to be planned in advance to ensure that the rates of adjacent domestic SRIO switch chips do not match. After waiting for the serdes operation to be configured, the RapidIO rate needs to be modified to ensure that the rates of all domestic SRIO switch chips match. The disadvantages of this method are:

[0006] (1) Requires hardware cooperation and is relatively costly.

[0007] (2) Configuring the registers of domestic SRIO switch chips to achieve domestic SRIO switch chip rate matching may cause the RIO Port Error and Status CSR to contain an error state, that is, the link state is unstable, which will affect RapidIO communication to a certain extent.

[0008] (3) After the rate is modified, there is a certain delay waiting for the rate modification to take effect, which affects the initialization efficiency to a certain extent. Summary of the Invention

[0009] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, device and medium for initializing a multi-SRIO domestic switch chip, which has the advantages of low cost and strong stability.

[0010] The object of the present invention is achieved through the following solutions:

[0011] A method for initializing a multi-SRIO domestic switching chip, comprising the steps of:

[0012] S1, number multiple domestic SRIO switch boards, and sort and classify them according to the serial numbers;

[0013] S2, power on the domestic SRIO switch board with the first type number;

[0014] S3, power on the domestic SRIO switch board with the second type number;

[0015] S4: Check the RIO Port Error and Status CSR of all ports of the first-class domestic SRIO switch board to determine the port link status;

[0016] S5, if the link status of a port in the first type numbered SRIO domestic switch chip is abnormal, proceed to step S6; if the link status of all ports in the first type numbered SRIO domestic switch chip is normal, proceed to step S7;

[0017] S6, for a port link status abnormality, perform SRIO domestic switch chip port reset operation, and return to step S4; this step sets the reset number limit, if the reset number limit is exceeded, proceed to step S7, otherwise return to step S4;

[0018] S7, report the results.

[0019] Furthermore, in step S1, a plurality of domestic SRIO switch boards constitute an SRIO network environment.

[0020] Furthermore, in step S1, the numbering is sequential.

[0021] Furthermore, in step S1, the sorting according to the serial numbers specifically includes: sorting in an ascending order of 1, 2, 3, 4, 5, 6...

[0022] Furthermore, classification is performed according to the serial numbers, specifically, classification is performed according to the odd or even serial numbers.

[0023] Furthermore, the first category number is an odd-numbered category number.

[0024] Furthermore, the second category numbering is an even-numbered category numbering.

[0025] Furthermore, in step S7, the result reporting is specifically reporting via a control bus.

[0026] A computer device includes a processor and a memory, wherein a computer program is stored in the memory. When the computer program is loaded by the processor and executes the method described in any one of Examples 1 to 8.

[0027] A readable storage medium stores a computer program, wherein the computer program is loaded by a processor and executes the method described in any one of Examples 1 to 8.

[0028] The beneficial effects of the present invention include:

[0029] (1) The present invention has a low-cost technical effect: the present invention utilizes the different power-on timings of the modules to stagger the configuration operations of multiple SRIO domestic switching chips serdes, which is simple and effective and does not require changes to the original hardware design.

[0030] (2) The present invention has a technical effect of strong stability: the method of the present invention avoids link instability caused by rate modification, making the RapidIO link state more stable. Furthermore, the present invention further ensures the stability of the RapidIO link state by performing RIO Port Error and Status CSR detection on all ports of the domestically produced SRIO switch chip that is powered on first, and recovering abnormal link states, thereby ensuring RapidIO communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1This is a schematic diagram of a method for initializing a multi-SRIO domestic switching chip according to an embodiment of the present invention;

[0033] Figure 2 FIG. 4 is a schematic diagram of an SRIO network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0035] The present invention aims to provide a method, device and medium for initializing multiple SRIO domestic switching chips in response to the existing problems of changing the initial RapidIO rate of the hardware. In the specific implementation process, it includes providing a method for initializing multiple SRIO domestic switching chips, such as Figure 1 As shown, the following steps are included:

[0036] S11, sort the serially connected domestic SRIO switch boards in the system in ascending order of 1, 2, 3, 4, 5, 6... and then classify them by odd or even sequence numbers;

[0037] S12, odd-numbered domestic SRIO switch boards are powered on;

[0038] S13, even-numbered domestic SRIO switch boards are powered on;

[0039] S14: Check the RIO Port Error and Status CSR of all ports of the odd-numbered domestic SRIO switch board to determine the port link status;

[0040] S15, if the link status of a port in the odd-numbered SRIO domestic switch chip is abnormal, proceed to step S16; if the link status of all ports in the odd-numbered SRIO domestic switch chip is normal, proceed to step S17;

[0041] S16, for a port link status abnormality, perform SRIO domestic switch chip port reset operation, and proceed to step S14. This process can set an upper limit on the number of resets. If the upper limit is exceeded, proceed to step S17, otherwise proceed to step S14.

[0042] S17, report the results.

[0043] In another embodiment of the present invention, Figure 2 As shown in the figure, taking the example of six SRIO domestic switch boards in two chassis, where two of them are connected to build an SRIO network environment, the specific implementation includes the following steps:

[0044] SS1, classify the six SRIO domestic switch boards according to odd and even numbers, as shown in the figure. The odd-numbered SRIO domestic switch boards are not interconnected with the even-numbered SRIO domestic switch boards.

[0045] SS2, the control bus controls the power-on of SRIO domestic switch chips 1, 3, and 5;

[0046] SS3, control bus control SRIO domestic switch chips 2, 4, and 6 power on;

[0047] SS4, control bus to check the RIO Port Error and Status CSR status of all ports of SRIO domestic switch chips 1, 3, and 5;

[0048] SS5: If the link status of a port in the SRIO domestic switch chips 1, 3, and 5 is abnormal, proceed to step SS6; if the link status of all ports in the SRIO domestic switch chips 1, 3, and 5 is normal, proceed to step SS7;

[0049] SS6, for a port link status abnormality, perform SRIO domestic switch chip port reset operation; proceed to step SS4, this process can set the upper limit of reset times, exceed the upper limit of reset times, proceed to step SS7, otherwise proceed to step SS4.

[0050] S7, report the result through the control bus.

[0051] The beneficial effects of the embodiments of the present invention are:

[0052] 1) Low cost: In response to manufacturers' requirements for the initial hardware rate, the present invention utilizes different module power-on sequences to stagger the configuration operations of multiple SRIO domestic switching chips, SerDes. This is simple and effective, and does not require changes to the original hardware design.

[0053] 2) Strong stability: Configuring domestic SRIO switch chip registers to achieve domestic SRIO switch chip rate matching may cause the RIO Port Error and Status CSR to contain an error state, i.e., link status instability. The method of the present invention avoids link instability caused by rate modification, making the RapidIO link status more stable. Furthermore, the present invention further ensures the stability of the RapidIO link status by performing RIO Port Error and Status CSR detection on all ports of the domestic SRIO switch chip that is powered on first, and recovering any abnormal link status, thereby ensuring RapidIO communication.

[0054] Example 1

[0055] A method for initializing a multi-SRIO domestic switching chip, comprising the steps of:

[0056] S1, number multiple domestic SRIO switch boards, and sort and classify them according to the serial numbers;

[0057] S2, power on the domestic SRIO switch board with the first type number;

[0058] S3, power on the domestic SRIO switch board with the second type number;

[0059] S4: Check the RIO Port Error and Status CSR of all ports of the first-class domestic SRIO switch board to determine the port link status;

[0060] S5, if the link status of a port in the first type numbered SRIO domestic switch chip is abnormal, proceed to step S6; if the link status of all ports in the first type numbered SRIO domestic switch chip is normal, proceed to step S7;

[0061] S6, for a port link status abnormality, perform SRIO domestic switch chip port reset operation, and return to step S4; this step sets the reset number limit, if the reset number limit is exceeded, proceed to step S7, otherwise return to step S4;

[0062] S7, report the results.

[0063] Example 2

[0064] Based on Example 1, in step S1, a plurality of domestic SRIO switch boards form an SRIO network environment.

[0065] Example 3

[0066] Based on Example 1, in step S1, the numbering is sequential.

[0067] Example 4

[0068] On the basis of Example 1, in step S1, the sorting according to the serial number specifically includes: sorting in an ascending order of 1, 2, 3, 4, 5, 6...

[0069] Example 5

[0070] On the basis of Example 1, classification is performed according to the serial numbers, specifically, classification is performed according to the odd or even serial numbers.

[0071] Example 6

[0072] Based on Example 5, the first category number is an odd-numbered category number.

[0073] Example 7

[0074] Based on Example 6, the second category numbering is an even-numbered category numbering.

[0075] Example 8

[0076] Based on Example 1, in step S7, the result reporting is specifically reporting via the control bus.

[0077] Example 9

[0078] A computer device includes a processor and a memory, wherein a computer program is stored in the memory. When the computer program is loaded by the processor and executes the method described in any one of Examples 1 to 8.

[0079] Example 10

[0080] A readable storage medium stores a computer program, wherein the computer program is loaded by a processor and executes the method described in any one of Examples 1 to 8.

[0081] The units involved in the embodiments of the present invention may be implemented in software or hardware, and the units described may also be provided in a processor. In some cases, the names of these units do not limit the units themselves.

[0082] According to one aspect of the present application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0083] As another aspect, the present application further provides a computer-readable medium, which may be included in the electronic device described in the above embodiments, or may exist independently without being incorporated into the electronic device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device implements the method described in the above embodiments.

[0084] The parts not involved in the present invention are the same as the existing technology or can be implemented by using the existing technology.

[0085] The above technical solution is only one embodiment of the present invention. For those skilled in the art, it is easy to make various types of improvements or modifications based on the application methods and principles disclosed in the present invention, and it is not limited to the method described in the above specific embodiment of the present invention. Therefore, the method described above is only preferred and does not have a restrictive meaning.

[0086] In addition to the above examples, those skilled in the art may obtain other embodiments based on the above disclosure or by utilizing knowledge or technology in related fields to make modifications. The features of each embodiment may be interchangeable or replaced. The modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A method for initializing a multi-SRIO domestic switch chip, characterized in that: Including steps: S1, number multiple domestic SRIO switch boards, and sort and classify them according to the serial numbers; S2, power on the domestic SRIO switch board with the first type number; S3, power on the domestic SRIO switch board with the second type number; S4: Check the RIO Port Error and Status CSR of all ports of the first-class domestic SRIO switch board to determine the port link status; S5, if the link status of a port in the first type numbered SRIO domestic switch chip is abnormal, proceed to step S6; if the link status of all ports in the first type numbered SRIO domestic switch chip is normal, proceed to step S7; S6, for a port link status abnormality, perform SRIO domestic switch chip port reset operation, and return to step S4; this step sets the reset number limit, if the reset number limit is exceeded, proceed to step S7, otherwise return to step S4; S7, report the results.

2. The method for initializing a multi-SRIO domestic switching chip according to claim 1, characterized in that: In step S1, a plurality of domestic SRIO switch boards form an SRIO network environment.

3. The method for initializing a multi-SRIO domestic switching chip according to claim 1, wherein: In step S1, the numbers are numbered sequentially.

4. The method for initializing a multi-SRIO domestic switching chip according to claim 1, wherein: In step S1, the sorting according to the serial numbers specifically includes sorting in an ascending order of 1, 2, 3, 4, 5, 6...

5. The method for initializing a multi-SRIO domestic switching chip according to claim 1, wherein: Classify by serial number, specifically by odd or even serial number.

6. The method for initializing a multi-SRIO domestic switching chip according to claim 5, characterized in that: The first category numbers are odd-numbered categories.

7. The method for initializing a multi-SRIO domestic switching chip according to claim 6, characterized in that: The second category number is an even-numbered category number.

8. The method for initializing a multi-SRIO domestic switching chip according to claim 1, characterized in that: In step S7, the result reporting is specifically reporting via a control bus.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein a computer program is stored in the memory. When the computer program is loaded by the processor, the method according to any one of claims 1 to 8 is executed.

10. A readable storage medium, characterized in that: A computer program is stored in a readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 1 to 8.

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