Semiconductor structure, layout structure and memory

Abstract

The embodiments of the present disclosure provide a semiconductor structure, a layout structure and a memory. The semiconductor structure comprises: a plurality of memory cell arrays arranged side by side along a first direction; a plurality of read-write control circuits arranged side by side along the first direction, located on one side of the memory cell arrays in a second direction, and each read-write control circuit is connected to a corresponding memory cell array through a first data line, the read-write control circuit is used for controlling writing or reading data to the memory cell array, and the second direction is perpendicular to the first direction; a check circuit, the check circuit is located on a side of the read-write control circuit away from the memory cell array, and the check circuit is connected to the read-write control circuit through a second data line, and the check circuit is used for checking the data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a layout structure and a memory. BACKGROUND

[0002] Dynamic random access memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. Dynamic random access memory usually includes a core storage area and a peripheral circuit area. The core storage area is used to set a plurality of storage units for storing data information. The peripheral circuit area is electrically connected to the storage units through data lines to enable the storage units to store or read data information.

[0003] With the development of semiconductor technology, the integration of storage units is becoming higher and higher, and the connection lines between the peripheral circuits and the storage units are becoming more and more complex, increasing the difficulty of the preparation process of the memory, and at the same time, increasing the power consumption of the memory, thereby reducing the performance of the memory. SUMMARY

[0004] Therefore, the present disclosure provides a semiconductor structure, a layout structure and a memory.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] a plurality of storage unit arrays arranged side by side along a first direction;

[0007] a plurality of read-write control circuits arranged side by side along the first direction, located on one side of the storage unit arrays in a second direction, and each read-write control circuit is connected to a corresponding storage unit array through a first data line, the read-write control circuit is used to control writing or reading data to the storage unit array, and the second direction is perpendicular to the first direction;

[0008] a verification circuit, the verification circuit is located on a side of the read-write control circuit away from the storage unit array, and the verification circuit is connected to the read-write control circuit through a second data line, and the verification circuit is used to verify the data.

[0009] In some embodiments, each storage unit array is connected to a plurality of first data lines extending along the second direction;

[0010] The read-write control circuit includes a plurality of sub-circuits, and each sub-circuit is connected to the corresponding storage unit array of the read-write control circuit through a first data line.

[0011] In some embodiments, the check circuit comprises at least:

[0012] a plurality of first-level check units connected to at least one of the read-write control circuits, for checking data read by the read-write control circuit or data to be written, to obtain a first-level check result;

[0013] The first-level check units are arranged on a side of the read-write control circuit away from the memory cell array and along the first direction.

[0014] In some embodiments, the check circuit further comprises:

[0015] at least one second-level check unit connected to at least one of the first-level check units, for checking the first-level check result to obtain a second-level check result;

[0016] The second-level check units and the first-level check units are alternately arranged along the first direction, or the second-level check units are located on a side of the first-level check units away from the read-write control circuit.

[0017] In some embodiments, the check circuit further comprises:

[0018] a check memory unit connected to the second-level check unit, for storing a final check result in the second-level check result.

[0019] In some embodiments, the semiconductor structure further comprises a first metal layer and a second metal layer; the second metal layer is located on the first metal layer; the first-level check units and the read-write control circuits are connected by conductive lines located in the first metal layer;

[0020] The second-level check units and other check circuits are connected by conductive lines located in the second metal layer.

[0021] In some embodiments, the first-level check units and the read-write control circuits are connected by at least one first conductive line in the first metal layer, and the first conductive line extends along the second direction;

[0022] The second-level check units and other check circuits are connected by at least one second conductive line in the second metal layer, and the second conductive line extends along the first direction.

[0023] In some embodiments, the first-level check units are connected to two adjacent read-write control circuits.

[0024] In some embodiments, the plurality of second-level check units comprises at least one first check unit and at least one second check unit;

[0025] The first check unit is connected with at least one of the first-level check units, and is configured to perform first check on the first-level check result.

[0026] The second check unit is connected with at least one of the first check units, and is configured to perform second check on the first check result and output a final check result.

[0027] In some embodiments, the semiconductor structure comprises:

[0028] 8 storage unit arrays and 8 read-write control circuits, each of the read-write control circuits comprising 16 sub-circuits; wherein each of the storage unit arrays is connected with the sub-circuit of the corresponding read-write control circuit through 16 first data lines;

[0029] 4 first-level check units and 3 second-level check units; wherein the 3 second-level check units comprise two first check units and one second check unit; the first-level check units and the second-level check units are alternately arranged along the first direction.

[0030] In some embodiments, the semiconductor structure comprises:

[0031] The first-level check unit is connected with two adjacent read-write control circuits through a first wire in a first metal layer, the first wire extending along the second direction;

[0032] The first check unit is connected with two first-level check units through a second wire in a second metal layer, the second wire extending along the first direction;

[0033] The second check unit is connected with two first check units through a second wire in a second metal layer, the second wire extending along the first direction.

[0034] In some embodiments, the semiconductor structure further comprises: a plurality of sub-word line drivers;

[0035] The sub-word line drivers and the storage unit arrays are alternately arranged along the first direction; the sub-word line drivers are configured to control word lines in the storage unit arrays.

[0036] In a second aspect, the embodiments of the present disclosure provide a memory comprising the semiconductor structure as described in the first aspect of the present disclosure.

[0037] In a third aspect, the embodiments of the present disclosure provide a layout structure comprising:

[0038] A plurality of storage unit array layouts arranged side by side along a first direction.

[0039] a plurality of memory cell array patterns arranged in parallel along the first direction, the memory cell array patterns being located on one side of the memory cell array in a second direction, the second direction being perpendicular to the first direction; Figure One a plurality of read-write control circuit patterns arranged in parallel along the first direction, the read-write control circuit patterns being located on one side of the memory cell array in the second direction, the second direction being perpendicular to the first direction;

[0040] a plurality of first data line patterns extending along the second direction, the first data line patterns being located on a side of the read-write control circuit patterns close to the memory cell array patterns, the memory cell array patterns being connected to the corresponding read-write control circuit patterns through the first data line patterns.

[0041] In some embodiments, the pattern structure further comprises:

[0042] a plurality of check circuit patterns arranged in parallel along the first direction, at least one of the check circuit patterns being connected to at least one of the read-write control circuit patterns;

[0043] the check circuit patterns being located on a side of the read-write control circuit patterns away from the memory cell array patterns.

[0044] In the semiconductor structure provided by the embodiments of the present disclosure, the memory cell array is arranged in parallel along the first direction, the read-write control circuit is located on one side of the memory cell array in the second direction and arranged in parallel along the first direction, and the second direction is perpendicular to the first direction; the check circuit is located on a side of the read-write control circuit away from the memory cell array. The semiconductor structure provided by the present disclosure makes the memory cell array and the read-write control circuit one-to-one corresponding in the second direction by arranging the check circuit on a side of the read-write control circuit away from the memory cell array, so that the memory cell array and the read-write control circuit can be connected through straight-line wires, the connection line between the read-write control circuit and the memory cell array is optimized, thereby reducing the difficulty of the preparation process of the memory and reducing the power consumption of the memory in the data transmission process, and improving the speed of data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure Figure One ;

[0046] Figure 2 A schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure Figure Two ;

[0047] Figure 3 A schematic diagram of a connection mode between a memory cell array and a read-write control circuit in a semiconductor structure provided by the embodiments of the present disclosure

[0048] Figure 4A schematic of a semiconductor structure including a first level of verification circuitry and a second level of verification circuitry is provided for embodiments of the present disclosure Figure One ;

[0049] Figure 5 A schematic of a semiconductor structure including a first level of verification circuitry and a second level of verification circuitry is provided for embodiments of the present disclosure Figure Two ;

[0050] Figure 6 A schematic of a semiconductor structure including a sub-word line driver is provided for embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] For the purposes of the present disclosure, the exemplary embodiments disclosed herein will be described with reference to the accompanying drawings. While the exemplary embodiments of the present disclosure will be described in conjunction with the drawings, it will be understood that they are not limitative to the present disclosure. That is, the exemplary embodiments of the present disclosure are intended to cover various modifications and alternative forms, and all such variations as can occur to those skilled in the art. In addition, the exemplary embodiments disclosed herein are intended to cover the accompanying claims and all equivalents thereof.

[0052] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In some instances, well-known features are not described in detail in order to avoid obscuring the present disclosure. In addition, some terminology can be used in the following description for the purpose of reference only.

[0053] Generally, the terminology can be understood at least in part from usage of the singular throughout the present disclosure. For example, as used herein, the terminology "one or more of, in particular, the terminology "a" or "an" can be taken to mean one or more than one and / or a combination thereof depending at least in part on context. Similarly, at least the terms "based on" and "one or more of" can be understood to not necessarily imply exclusive factors, and can instead allow for additional factors not necessarily explicitly described herein, again, depending at least in part on context.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] For a thorough understanding of the present disclosure, reference will be made to the following detailed description, in conjunction with the accompanying drawings, in which:

[0056] Semiconductor memory is a memory using semiconductor circuit for access, among which DRAM is widely used in various fields due to its fast storage speed and high integration.

[0057] In some embodiments, a check circuit is arranged in the DRAM to check whether the read data is accurate, so as to obtain higher data read-write reliability, as shown in a partial structure diagram of a DRAM. Figure 1 A partial structure diagram of a DRAM is shown. Figure 1 The semiconductor structure shown includes: a plurality of memory cell arrays 10 arranged side by side along a first direction X; a plurality of read-write control circuits RW and a plurality of error correcting code (ECC) check circuits, the read-write control circuit RW is connected with the memory cell array 10 through a plurality of data lines, for controlling writing or reading data to / from the memory cell array 10; the check circuit is connected with the read-write control circuit RW through a metal layer (not shown in the figure), so as to obtain the data of the memory cell array 10 and check it.

[0058] Referring to Figure 1 , the read-write control circuit RW and the ECC check circuit are located on one side of the memory cell array 10 in a second direction Y perpendicular to the first direction X, and are arranged alternately along the first direction X. Figure 1 The layout mode of the semiconductor structure shown makes the semiconductor structure more compact, and to some extent, improves the integration of the memory, but also causes the data line 01 connected with the read-write control circuit RW and the data line 02 connected with the memory cell array 10 not to be one-to-one corresponding in the second direction Y, in this case, the read-write control circuit RW and the memory cell array 10 cannot be connected through straight-line type conductive lines, and jumper processing needs to be performed on the data line between them to realize conduction, as shown in Figure 1As shown, a wire 03 is added between the data line 01 and the data line 02 to make the line between the read-write control circuit RW and the storage unit array 10 conductive. This makes the circuit of the memory more complex, increases the difficulty of the memory preparation process, and the jumper between the data lines increases the resistance in the circuit, reduces the speed of data transmission, and thus increases the power consumption of the memory and reduces the performance of the memory.

[0059] Therefore, the embodiments of the present disclosure provide a semiconductor structure, a layout structure and a memory.

[0060] Figure 2 A schematic diagram of a semiconductor structure of a half storage block is provided in the embodiments of the present disclosure. Referring to Figure 2 As shown, the semiconductor structure comprises:

[0061] a plurality of storage unit arrays 10 arranged side by side along a first direction X;

[0062] a plurality of read-write control circuits RW arranged side by side along the first direction X, located on one side of the storage unit array 10 in a second direction Y, and each read-write control circuit RW is connected to a corresponding storage unit array 10 through a first data line 04, the read-write control circuit RW is used to control the writing or reading of data to the storage unit array 10, and the second direction Y is perpendicular to the first direction X;

[0063] a check circuit located on the side of the read-write control circuit RW away from the storage unit array 10 and connected to the read-write control circuit RW through a second data line 05, the check circuit is used to check the data in the storage unit array 10.

[0064] In the embodiments of the present disclosure, the storage unit array 10 is used to store data, thereby realizing the storage function of the semiconductor memory. Exemplarily, the storage unit array 10 can include word lines, bit lines, storage units and the like, and the storage unit further includes a storage capacitor and a transistor, the control end of the transistor is connected to the word line, the first end of the transistor is connected to the storage capacitor, and the second end of the transistor is connected to the bit line. When the word line controls the transistor to be conductive, the storage capacitor and the bit line are conductive, thereby realizing the reading and writing of data information, i.e., when reading data information, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line sends the data information to be written to the storage capacitor. The plurality of storage unit arrays 10 in the embodiments of the present disclosure are arranged side by side along the first direction X to form a storage block, which can be a complete storage bank 20, can be half of the storage bank 20, or can be other forms, which are not limited in the embodiments of the present disclosure.

[0065] The read-write control circuit RW is a logic circuit module connected with the memory cell array 10 and used to control the memory cell array 10 to read and write data. For example, the read-write control circuit RW can be used to receive read-write enable signals (such as a read enable signal RdEn and a write enable signal WrEn), and send data to be written to the memory cell array 10 or receive read data, so as to realize the function of controlling the memory cell array 10 to write or read data. For example, during a read-write operation, the read-write control circuit RW can perform a write operation according to the write enable signal WrEn to store data into the memory cell array 10 selected by an address, and perform a read operation according to the read enable signal RdEn to output data stored in the memory cell array 10.

[0066] Each read-write control circuit RW can be connected with a corresponding memory cell array 10 through a first data line 04 and connected with a check circuit through a second data line 05, so as to realize data interaction with the memory cell array 10 and the check circuit, and then transmit data written or read from the memory cell array 10 to the check circuit. The first data line 04 can be a signal line connected to the memory cell array 10 and used to provide write data to the circuit connected to each memory cell. For example, data to be written can be transmitted to the bit line connected to the memory cell through the first data line 04, and the signal on the bit line is further transmitted to the memory cell during the write process.

[0067] The check circuit is connected with the read-write control circuit RW, and can acquire data read from the memory cell array 10 or to be written into the memory cell array 10 and perform corresponding operations, so as to check whether the data information in the memory cell array 10 is accurate, and output a check result, thereby improving the data read-write reliability of the memory cell array 10. Each check circuit can be used to check the data information of one or more memory arrays. In the embodiments of the present disclosure, the check circuit can be a parity check circuit or an error correction code (ECC) check circuit, or other check circuits or combinations of check circuits, and the like, which are not limited herein.

[0068] In an embodiment, the check circuit can be an ECC check circuit, which is used for error detection and correction of data transmission between a memory and a processor. Specifically, in the process of transmitting data from the memory to the processor, when the data is output from the memory, an ECC check code of the transmission data is generated, when the data is transmitted to the processor, error detection and correction are performed on the transmission data based on the ECC check code, after the error detection and correction, the ECC check code is discarded and the corrected data is output. In the process of transmitting data from the processor to the memory, when the data is output from the processor, an ECC check code of the transmission data is generated, when the transmission data is transmitted to the memory, error detection and correction are performed on the transmission data based on the ECC check code, after the error detection and correction, the ECC check code is discarded and the corrected data is output.

[0069] In the embodiments of the present disclosure, the memory cell arrays 10 are arranged in parallel along the first direction X; the read-write control circuits RW are arranged in parallel along the first direction X on one side of the memory cell arrays 10 in the second direction Y; and the check circuits are arranged on the side of the read-write control circuits RW away from the memory cell arrays 10.

[0070] In the embodiments of the present disclosure, the check circuits are arranged on the side of the read-write control circuits RW away from the memory cell arrays 10, so that each read-write control circuit RW corresponds to one memory cell array 10 in the second direction Y, and the memory cell arrays 10 and the read-write control circuits RW can be connected by straight wires. Compared with the arrangement in which the check circuits and the read-write control circuits RW are arranged alternately, the arrangement of the embodiments of the present disclosure optimizes the connection lines between the read-write control circuits RW and the memory cell arrays 10, thereby reducing the difficulty of the preparation process of the memory, reducing the power consumption of the memory in the data transmission process, and improving the speed of data transmission.

[0071] In some embodiments, as shown in FIG. 1, each memory cell array 10 is connected to a plurality of first data lines 04 extending along the second direction Y. Figure 3

[0072] The read-write control circuit RW includes a plurality of sub-circuits 06, and each sub-circuit 06 is connected to the corresponding memory cell array 10 of the read-write control circuit RW through one of the first data lines 04.

[0073] In the embodiments of the present disclosure, each memory cell array 10 includes a plurality of memory cells. In order to ensure the efficiency of writing or reading data of the memory cell array 10, each memory cell array 10 is connected to the read-write control circuit RW through a plurality of first data lines 04. The memory cell array 10 can receive data to be written or output stored data through the first data line 04. In the embodiments of the present disclosure, the plurality of first data lines 04 connected to each memory cell array 10 are arranged in parallel along the first direction X, and the first data line 04 is a straight wire extending along the second direction Y.

[0074] ​The sub-circuit 06 in the read-write control circuit RW is a logic circuit module connected with the memory cell array 10 and controls the memory cell array 10 to read and write data. The sub-circuit 06 in the read-write control circuit RW is located at the side of the corresponding memory cell array 10 in the second direction Y, and a plurality of sub-circuits 06 are arranged side by side along the first direction X. The plurality of first data lines 04 connected with the memory cell array 10 correspond to the sub-circuits 06 in the read-write control circuit RW in the second direction Y one by one. Each sub-circuit 06 is connected with the corresponding memory cell array 10 in the read-write control circuit RW through a first data line 04, so that the read-write control circuit RW can receive the read data or send the data to be written into the memory cell array 10 through the plurality of first data lines 04.

[0075] The present disclosure makes the first data line 04 connected with the memory cell array 10 correspond to the sub-circuit 06 in the read-write control circuit RW in the second direction Y one by one, so that the straight-line type first data line 04 extending along the second direction Y can connect the memory cell array 10 and the read-write control circuit RW. Since the read-write control circuit RW is located at the side of the corresponding memory cell array 10 in the second direction Y, the arrangement of the present disclosure further optimizes the connection line between the read-write control circuit RW and the memory cell array 10, and reduces the preparation process difficulty of the memory.

[0076] In some embodiments, as shown in FIG. 1, the check circuit at least includes: Figure 4

[0077] A plurality of first-level check units 11 connected with at least one read-write control circuit RW, for checking the data read by the read-write control circuit RW or the data to be written, to obtain a first-level check result.

[0078] The first-level check units 11 are arranged along the first direction X and are located at the side of the read-write control circuit RW away from the memory cell array 10.

[0079] The first-level check unit 11 is a calculation circuit module connected with the read-write control circuit RW and checks the data read by the read-write control circuit RW or the data to be written. The first-level check unit 11 is connected with the read-write control circuit RW through a second data line 05. Each first-level check unit 11 can be connected with one or more read-write control circuits RW, and checks the data read by the one or more read-write control circuits RW connected thereto or the data to be written, to obtain a first-level check result. For example, if the first-level check unit 11 is connected with two read-write control circuits RW, the data in the two memory cell arrays 10 corresponding to the two read-write control circuits RW are checked simultaneously in one check process, to obtain a first-level check result.

[0080] ​The first-level check units 11 are located on the side of the read-write control circuits RW away from the memory cell array 10. The first-level check units can be arranged in parallel along the first direction X or can be arranged dispersedly along the first direction X. In the embodiment of the present disclosure, the first-level check units 12-1 are arranged dispersedly along the first direction X, so that each first-level check unit 11 is as close as possible to the read-write control circuit RW corresponding thereto, thereby shortening the connection line between the first-level check unit 11 and the read-write control circuit RW, reducing the resistance in the line, thereby reducing the power consumption of the memory in the data transmission process; at the same time, the connection between the first-level check unit 11 and the read-write control circuit RW is easier to implement, the connection line between the read-write control circuit RW and the first-level check unit 11 is optimized, and the preparation process difficulty of the memory is reduced.

[0081] It should be noted that the data that can be checked by the first-level check unit 11 in one check process is limited. The number of memory cell arrays 10 that can be checked by one first-level check unit 11 at a time can be determined according to the number of bytes of data that can be checked by the first-level check unit 11 at a time and the number of bytes of data that can be stored by each memory cell array 10, and then the number of read-write control circuits RW connected to one first-level check unit 11 is determined. For example, each memory cell array 10 reads or writes 16 bits of data at a time, and the first-level check unit can check 32 bits of data at a time, so each first-level check unit can check the data in 2 memory cell arrays 10 at a time, and therefore, each first-level check unit can be connected to 2 read-write control circuits to check the data in the 2 memory cell arrays 10 connected to the 2 read-write control circuits, to obtain the first-level check result.

[0082] On the other hand, the number of first-level check units required by the memory bank can also be determined according to the amount of data that can be checked by the first-level check unit at a time and the amount of data that can be read or written by all memory cell arrays 10 in the memory block at a time. For example, half of the memory bank contains 8 memory cell arrays 10, each of which can read or write 16 bits of data at a time, i.e., 128 bits of data at a time, and the first-level check unit can check 32 bytes of data at a time, so the half of the memory bank requires 4 first-level check units.

[0083] In some embodiments, as shown in FIG. 1, Figure 4 The check circuit further includes:

[0084] at least one second-level check unit 12 connected to the at least one first-level check unit 11, configured to check the first-level check result to obtain a second-level check result;

[0085] The second-level check units 12 and the first-level check units 11 are alternately arranged along the first direction X, or the second-level check units 12 are located on the side of the first-level check units 11 away from the read-write control circuit RW.

[0086] It should be noted that the data that can be checked by the check circuit each time is limited. In order to improve the check speed and check efficiency of the check circuit and ensure the data read-write reliability of the semiconductor memory, the check circuit can check the data in the storage unit multiple times by setting check units of different levels.

[0087] In the embodiment, as shown in Figure 4 The check circuit includes the first-level check units 11 and the second-level check units 12. The first-level check units 11 are calculation circuit modules connected with the read-write control circuit RW and checking the data read by the read-write control circuit RW or the data to be written. The second-level check units 12 are calculation circuit modules connected with the first-level check units 11 and checking the first-level check result. Exemplarily, the first-level check units 11 in the check circuit first check the data in the storage unit array 10 to obtain the first-level check result. The first-level check units 11 are connected with the second-level check units 12 through the third data lines 07 and transmit the first-level check result to the second-level check units 12 through the third data lines 07. Then, the second-level check units 12 check the first-level check result to obtain the second-level check result.

[0088] In the embodiment of the present disclosure, as shown in Figure 4 The second-level check units 12 and the first-level check units 11 are both located on the side of the read-write control circuit RW away from the storage unit array 10, and the second-level check units 12 and the first-level check units 11 are alternately arranged along the first direction X, so that the second-level check units 12 are located between the first-level check units connected with the second-level check units 12. Thus, the connection line between the second-level check units 12 and the first-level check units 11 is shortened, the resistance in the line is reduced, and thus the power consumption of the memory in the data transmission process is reduced. At the same time, the connection between the second-level check units 12 and the first-level check units 11 is easier to implement, the connection line between the second-level check units 12 and the first-level check units 11 is optimized, and the preparation process difficulty of the memory is reduced.

[0089] In an example, as shown in Figure 5As shown, the first-level check unit 11 is located on the side of the read-write control circuit RW away from the memory cell array 10, and the second-level check unit 12 is located on the side of the first-level check unit 11 away from the read-write control circuit RW, so that the read-write control circuit RW, the first-level check unit 11 and the second-level check unit 12 are arranged in sequence along the second direction Y. The first-level check unit 11 is connected to the read-write control circuit RW through the second data line 05, the second-level check unit 12 is connected to the first-level check unit 11 through the third data line 07, and the second data line 05 and the third data line 07 have the same running direction. For example, the second data line 05 and the third data line 07 both extend along the second direction Y, which is conducive to forming the second data line 05 and the third data line 07 at the same time in the same process, thereby simplifying the process flow.

[0090] It should be noted that the second-level check unit 12 can be connected to one first-level check unit 11 or multiple first-level check units 11. The second-level check unit 12 can check a limited amount of data at a time, and the number of first-level check units 11 connected to the second-level check unit 12 is determined by the number of bytes of data that the second-level check unit 12 can check at a time and the number of bytes of data in the first-level check result. For example, the first-level check unit 11 can check 32 bytes of data at a time, i.e., the first-level check result including the 32 bytes of data in the first-level check unit 11; if the second-level check unit 12 can check 64 bytes of first-level check result at a time, each second-level check unit 12 can be connected to two first-level check units 11.

[0091] In some embodiments, the check circuit further comprises:

[0092] The check memory unit is connected to the second-level check unit 12 and is used to store the final check result in the second-level check result.

[0093] The check memory unit is a logic circuit module that can control the storage of the final check result in the check circuit into the corresponding memory cell array 10. In the process of transmitting data from the memory to the processor, when the data is output from the memory, the check circuit checks the data and generates a final check result; when the data is transmitted to the processor, error detection and correction are performed on the transmitted data based on the final check result, and after the error detection and correction, the final check result is discarded and the corrected data is output.

[0094] In the embodiment, the checking circuit first checks the data in the memory cell array 10 through the first-level checking unit 11 connected to obtain the first-level checking result; then checks the first-level checking result through the second-level checking unit 12 to obtain the second-level checking result, which at least includes a final checking result; the second-level checking unit 12 is connected to the checking memory cell through the fourth data line and transmits the final checking result in the second-level checking result to the checking memory cell through the fourth data line, and the checking memory cell receives and stores the final checking result in the second-level checking result; finally, the checking memory cell controls to store the final checking result into the corresponding memory cell array 10.

[0095] In some embodiments, the semiconductor structure further comprises: a first metal layer and a second metal layer; the second metal layer is located on the first metal layer;

[0096] The first-level checking unit 11 is connected to the read-write control circuit RW through the conductive line located in the first metal layer;

[0097] The second-level checking unit 12 is connected to other checking circuits through the conductive line located in the second metal layer.

[0098] The first metal layer and the second metal layer are mainly used as conductors, which can conduct the connection between the read-write control circuit, the first-level checking unit and the second-level checking unit. The materials of the first metal layer and the second metal layer include but are not limited to titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium and molybdenum, which can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) and the like.

[0099] As shown in Figure 4 The first-level checking unit 11 is connected to the read-write control circuit RW through a plurality of second data lines 05; the second-level checking unit 12 is connected to other checking circuits through a third data line 07, and the other checking circuits include the first-level checking unit 11 and other second-level checking units 12. Here, the second data line 05 can be a conductive line located in the first metal layer, and the third data line 07 can be a conductive line located in the second metal layer, i.e. the first-level checking unit 11 is connected to the read-write control circuit RW through the conductive line located in the first metal layer, and the second-level checking unit 12 is connected to other checking circuits through the conductive line located in the second metal layer.

[0100] For example, as shown in Figure 4As shown, the first-level verification unit 11 is located on one side of the read / write control circuit RW in the second direction. The second data line 05 connecting the first-level verification unit 11 and the read / write control circuit RW can extend along the second direction Y. The second-level verification circuit and the first-level verification circuit are arranged alternately along the first direction. The third data line 07 of the second-level verification unit 12 and other verification circuits (first-level verification unit 11 or other second-level verification units 12) can extend along the first direction X. Therefore, Figure 4 The second data line 05 and the third data line 07 in the semiconductor structure shown are perpendicular to each other.

[0101] By using different metal layers as conductors to connect the read / write control circuit (RW) and the verification circuit, as well as the verification circuits themselves, short circuits between different lines in the memory and coupling effects between circuits can be reduced, thereby improving the performance of the memory.

[0102] In some embodiments, the first-level verification unit 11 and the read / write control circuit RW are connected through at least one first wire 08 in the first metal layer, and the first wire 08 extends along the second direction Y.

[0103] The second-level verification unit 12 is connected to other verification circuits via at least one second wire 09 in the second metal layer, the second wire 09 extending along the first direction X.

[0104] like Figure 4 As shown, in this embodiment, the read / write control circuit RW is located on one side of the storage cell array 10 in the second direction Y, and the first-level verification unit 11 is located on the side of the read / write control circuit RW away from the storage cell array 10. That is, the first-level verification unit 11 is located on one side of the read / write control circuit RW in the second direction Y. Therefore, the first-level verification unit 11 can be connected to the read / write control circuit RW through a wire extending along the second direction Y. In this embodiment, the first-level verification unit 11 and the second-level verification unit 12 are arranged alternately along the first direction X. Therefore, the second verification unit 12-2 can be connected to the first-level verification unit 11 or other second-level verification units 12 through a wire extending along the first direction X.

[0105] In this embodiment, as Figure 4As shown, the first conductive lines 08 extending along the second direction Y are arranged in the first metal layer, the second conductive lines 09 extending along the first direction X are arranged in the second metal layer, the first-level check units 11 are connected with the read-write control circuits RW through one or more first conductive lines 08 in the first metal layer, and the first conductive lines 08 can transmit data read by the read-write control circuits RW or data to be written to the first-level check units 11; the second-level check units 12 are connected with other check circuits (the first-level check units 11 or other second-level check units 12) through one or more second conductive lines 09 in the second metal layer, and the second conductive lines 09 can realize data interaction between the second-level check units 12 and the first-level check units 11 and data interaction between the second-level check units 12.

[0106] In some embodiments, as shown in FIG. 1, the first-level check units 11 are connected with two adjacent read-write control circuits RW. Figure 4

[0107] In this embodiment, the first-level check units 11 can check data in two storage unit arrays 10 at the same time, and each storage unit array 10 transmits data to the first-level check units 11 through one read-write control circuit RW, so that the first-level check units 11 check data in two storage unit arrays 10 at the same time through connecting two read-write control circuits RW.

[0108] In this embodiment, the two read-write control circuits RW connected by the first-level check units 11 are adjacent, which can shorten the connection line between the first-level check units 11 and the read-write control circuits RW and reduce the resistance in the circuit.

[0109] In some embodiments, as shown in FIG. 1, the second-level check units 12 include at least one first check unit 12-1 and at least one second check unit 12-2. Figure 4

[0110] The first check unit 12-1 is connected with at least one first-level check unit 11 and is used for performing first check on the first check result.

[0111] The second check unit 12-2 is connected with at least one first check unit 12-1 and is used for performing second check on the result of the first check and outputting a final check result.

[0112] In this embodiment, as shown in FIG. 1, the first check unit 12-1 is connected with two first-level check units 11, and the second check unit 12-2 is connected with two first check units 12-1. Figure 4 ​​As shown, the check circuit checks the data in the memory cell array 10 through the first-level check unit 11, the first check unit 12-1 and the second check unit 12-2. Specifically, the check circuit first checks the data in the memory cell array 10 through the first-level check unit 11 to obtain a first-level check result; the first-level check unit 11 is connected with the first check unit 12-1 in the second-level check unit 12 through the third data line 07, and transmits the first-level check result to the first check unit 12-1 through the third data line 07, and the first check unit 12-1 performs a first check on the first-level check result; the first check unit 12-1 in the second-level check unit 12 is connected with the second check unit 12-2 through the fifth data line, and transmits the result of the first check to the second check unit 12-2 through the fifth data line, and the second check unit 12-2 performs a second check on the result of the first check and outputs a final check result.

[0113] In some embodiments, as shown in the semiconductor structure, comprising: Figure 4

[0114] 8 memory cell arrays 10 and 8 read-write control circuits RW, each read-write control circuit RW comprising 16 sub-circuits 06; wherein each memory cell array 10 is connected with the sub-circuits 06 of the corresponding read-write control circuit RW through 16 first data lines 04;

[0115] 4 first-level check units 11 and 3 second-level check units 12; wherein the 3 second-level check units 12 comprise two first check units 12-1 and one second check unit 12-2; the first-level check units 11 and the second-level check units 12 are alternately arranged along the first direction X.

[0116] As shown in the semiconductor structure, comprising: Figure 4 ​As shown, the semiconductor structure provided by the embodiment includes eight memory cell arrays 10, eight read-write control circuits RW, four first-level check units 11, and three second-level check units 12. The eight memory cell arrays 10 are arranged side by side along a first direction X, and the eight read-write control circuits RW are arranged side by side along the first direction X on one side of the memory cell arrays 10 in a second direction Y. The four first-level check units 11 and the three second-level check units 12 are located on the side of the read-write control circuits RW away from the memory cell arrays 10, and the first-level check units 11 and the second-level check units 12 are alternately arranged along the first direction X. In the embodiment, the check circuit is arranged on the side of the read-write control circuit RW away from the memory cell array 10, so that each read-write control circuit RW corresponds to one memory cell array 10 in the second direction Y, thereby optimizing the connection line between the read-write control circuit RW and the memory cell array 10, reducing the difficulty of the preparation process of the memory, reducing the resistance of the circuit, reducing the power consumption of the memory in the data transmission process, and improving the speed of data transmission.

[0117] In the embodiment, as shown in Figure 4 The memory cell array 10 transmits data to the read-write control circuit RW through the first data line 04, and the first data line 04 extends along the second direction Y. Figure 5 As shown, each read-write control circuit RW includes 16 sub-circuits 06, and the first data line 04 of the memory cell array 10 and the sub-circuit 06 in the read-write control circuit RW correspond to each other in the second direction Y. Each sub-circuit 06 is connected to a first data line 04 in the corresponding memory cell array 10, that is, each memory cell array 10 is connected to 16 sub-circuits 06 of the corresponding read-write control circuit RW through 16 first data lines 04. In the embodiment, the first data line 04 of the memory cell array 10 and the sub-circuit 06 in the read-write control circuit RW correspond to each other in the second direction Y, so that the memory cell array 10 and the read-write control circuit RW can be connected in a straight line, that is, the memory cell array 10 and the read-write control circuit RW can be directly connected without jumper, thereby optimizing the connection line between the read-write control circuit RW and the memory cell array 10.

[0118] In the embodiment, as shown in Figure 4 The first-level check unit 11 can check the data in two memory cell arrays 10 at the same time, and each memory cell array 10 transmits data to the first-level check unit 11 through a read-write control circuit RW. Therefore, each first-level check unit 11 in the embodiment is connected to two adjacent read-write control circuits RW, and the first-level check unit 11 obtains the data in the corresponding memory cell array 10 through the read-write control circuit RW, checks the data in the two memory cell arrays 10 at the same time, and obtains the first-level check result.

[0119] In the embodiment, as shown in Figure 4 the first check units 12-1 in the second check units 12 can simultaneously perform the first check on the two first check results, and the second check units 12-2 can simultaneously perform the second check on the check results of the two first check units 12-1. In the embodiment, the first check units 12-1 are connected with the two first check units 11, and each first check unit 11 is connected with only one first check unit 12-1; the first check units 12-1 perform the first check on the first check results of the connected first check units 11; the second check units 12-2 are connected with the two first check units 12-1, and perform the second check on the first check results in the two first check units 12-1 to obtain the final check result.

[0120] In some embodiments, the semiconductor structure comprises:

[0121] The first check units 12-1 are connected with the two first check units 11 through the second conductive lines 09 in the second metal layer, and the second conductive lines 09 extend along the first direction X;

[0122] The first check units 12-1 are connected with the two first check units 11 through the second conductive lines 09 in the second metal layer, and the second conductive lines 09 extend along the first direction X;

[0123] The second check units 12-2 are connected with the two first check units 12-1 through the second conductive lines 09 in the second metal layer, and the second conductive lines 09 extend along the first direction X.

[0124] As shown in Figure 4 In the embodiment, the read-write control circuits RW, the first check units 11, the first check units 12-1 and the second check units 12-2 perform data transmission through the conductive lines in the metal layers. The first check units 11 are located on one side of the read-write control circuits RW in the second direction Y, and the first check units 11 can be connected with the read-write control circuits RW through the conductive lines extending along the second direction Y. In the embodiment, the first check units 11, the first check units 12-1 and the second check units 12-2 are arranged side by side along the first direction X, and therefore, the first check units 12-1 can be connected with the first check units 11 through the conductive lines extending along the first direction X, and the second check units 12-2 can be connected with the first check units 12-1 through the conductive lines extending along the first direction X.

[0125] In the embodiment, as shown in Figure 4As shown, the first metal layer is arranged with first conductive lines 08 extending along the second direction Y, and the second metal layer is arranged with second conductive lines 09 extending along the first direction X, so that the first-level check unit 11 is connected to two adjacent read-write control circuits RW through two first conductive lines 08 in the first metal layer, the first check unit 12-1 is connected to two first-level check units 11 through two second conductive lines 09 in the second metal layer, and the second check unit 12-2 is connected to two first check units 12-1 through one second conductive line 09 in the second metal layer. In the embodiment, the second metal layer is located above the first metal layer, and the connection between the read-write control circuit RW and the check circuit and the connection between the check circuits are realized by using the metal layers in different layers as conductors, so that the short circuit between different lines in the memory and the coupling effect between circuits can be reduced, and the performance of the memory can be improved.

[0126] In some embodiments, as Figure 6 shown, the semiconductor structure further comprises: a plurality of sub-word line drivers 13 (SWD);

[0127] The sub-word line drivers 13 are arranged alternately with the memory cell array 10 along the first direction X; the sub-word line drivers 13 are used to control the word lines in the memory cell array 10.

[0128] In a semiconductor device, a word line can be used as a conductor to transmit a gate voltage required to drive one or more cell transistors of a memory cell. The cell transistors can operate in response to a potential state of the word line, so that data can be written to or read from the memory cell through the cell transistors. As the chip size and the memory capacity of the chip increase, the line delay caused by such a word line can be considered as one of the most important delay factors that limit the operating speed of the semiconductor device. In order to minimize the line delay of such a word line, a long word line is divided into a plurality of sub-word lines, and each sub-word line is controlled by a sub-word line driver 13.

[0129] The sub-word line drivers 13 in the embodiment are arranged alternately with the memory cell array 10 along the first direction X, and each sub-word line driver 13 can selectively drive one or more sub-word lines according to a main word line driving signal, which can represent a memory cell driving signal transmitted through a main word line.

[0130] The present disclosure also provides a memory comprising the semiconductor structure of any one of the preceding embodiments.

[0131] By way of example, the memory can be a DRAM, a Static Random-Access Memory (SRAM), a three-dimensional NAND flash memory, a two-dimensional NAND flash memory, a phase change memory, etc.

[0132] The present disclosure also provides a layout structure for manufacturing the semiconductor structure as described above, the layout structure comprising:

[0133] a plurality of memory cell array layouts arranged side by side along a first direction X;

[0134] a plurality of read-write control circuit layouts corresponding to the plurality of memory cell array layouts, the read-write control circuit layouts being located on one side of the memory cell array layouts along a second direction Y perpendicular to the first direction X; Figure One a plurality of read-write control circuit layouts corresponding to the plurality of memory cell array layouts, the read-write control circuit layouts being located on one side of the memory cell array layouts along a second direction Y perpendicular to the first direction X;

[0135] a plurality of first data line patterns extending along the second direction Y, the first data line patterns being located on the side of the read-write control circuit layouts close to the memory cell array layouts, and the memory cell array layouts being connected to the corresponding read-write control circuit layouts through the first data line patterns.

[0136] In some embodiments, the layout structure further comprises:

[0137] a plurality of check circuit layouts arranged side by side along the first direction X; at least one of the check circuit layouts being connected to at least one of the read-write control circuit layouts;

[0138] the check circuit layouts being located on the side of the read-write control circuit layouts away from the memory cell array layouts.

[0139] In some embodiments, the check circuit layouts at least comprise a plurality of first-level check unit layouts connected to at least one of the read-write control circuit layouts, wherein the first-level check unit layouts are arranged along the first direction X on the side of the read-write control circuit layouts away from the memory cell array layouts.

[0140] In some embodiments, the check circuit layouts further comprise at least one second-level check unit layout connected to at least one of the first-level check unit layouts; wherein the second-level check unit layouts are arranged alternately with the first-level check unit layouts along the first direction X, or the second-level check unit layouts are located on the side of the first-level check unit layouts away from the read-write control circuit layouts.

[0141] In some embodiments, the check circuit layouts further comprise a check memory cell layout connected to the second-level check unit layout.

[0142] In some embodiments, the layout structure further comprises a first metal layer layout and a second metal layer layout; the second metal layer layout being located on the upper layer of the first metal layer layout; the first metal layer layout being used to layout conductive lines in the first metal layer, and the second metal layer layout being used to layout conductive lines in the second metal layer.

[0143] In some embodiments, the first-level check unit layout in the layout structure is connected to two adjacent read-write control circuit layouts.

[0144] In some embodiments, the second-level check unit layout in the layout structure includes at least one first check unit layout and at least one second check unit layout; the first check unit layout is connected to at least one first-level check unit layout; and the second check unit layout is connected to at least one first-level check unit layout.

[0145] The above-described embodiments are merely illustrative for the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present disclosure shall be covered by the claims of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Multiple storage cell arrays, the storage cell arrays being arranged side by side along a first direction; Multiple read / write control circuits arranged in parallel along the first direction are located on one side of the storage cell array in the second direction, and each read / write control circuit is connected to a corresponding storage cell array via a first data line. The read / write control circuit is used to control the writing or reading of data to the storage cell array. The second direction is perpendicular to the first direction. A verification circuit is located on the side of the read / write control circuit away from the storage cell array, so that the storage cell array and the read / write control circuit correspond one-to-one in the second direction. The storage cell array and the read / write control circuit are connected through a straight first data line, and the verification circuit is connected to the read / write control circuit through a second data line. The verification circuit is used to verify the data.

2. The semiconductor structure according to claim 1, characterized in that, Each of the memory cell arrays is connected to multiple first data lines extending along the second direction; The read / write control circuit includes multiple sub-circuits, and each sub-circuit is connected to the corresponding storage cell array via a first data line.

3. The semiconductor structure according to claim 2, characterized in that, The verification circuit includes at least: Multiple first-level verification units are provided, each first-level verification unit being connected to at least one of the read / write control circuits, for verifying the data read by the read / write control circuits or the data to be written, and obtaining the first-level verification result. The first-level verification unit is located on the side of the read / write control circuit away from the storage cell array and is arranged along the first direction.

4. The semiconductor structure according to claim 3, characterized in that, The verification circuit also includes: At least one second-level verification unit is connected to at least one first-level verification unit, and is used to verify the first-level verification result to obtain the second-level verification result; The second-level verification unit and the first-level verification unit are arranged alternately along the first direction, or the second-level verification unit is located on the side of the first-level verification unit away from the read / write control circuit.

5. The semiconductor structure according to claim 4, characterized in that, The verification circuit also includes: The verification storage unit is connected to the second-level verification unit and is used to store the final verification result in the second-level verification result.

6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes: a first metal layer and a second metal layer; the second metal layer is located on top of the first metal layer; the first-level verification unit is connected to the read / write control circuit via a wire located on the first metal layer; The second-level verification unit is connected to the other verification circuits via wires located in the second metal layer.

7. The semiconductor structure according to claim 6, characterized in that, The first-level verification unit is connected to the read / write control circuit through at least one first wire in the first metal layer, and the first wire extends along the second direction. The second-level verification unit is connected to other verification circuits via at least one second wire in the second metal layer, the second wire extending along the first direction.

8. The semiconductor structure according to claim 4, characterized in that, The first-level verification unit is connected to two adjacent read / write control circuits.

9. The semiconductor structure according to claim 4, characterized in that, The plurality of second-level verification units include: at least one first verification unit and at least one second verification unit; The first verification unit is connected to at least one first-level verification unit and is used to perform a first verification on the first-level verification result; The second verification unit is connected to at least one of the first verification units, and is used to perform a second verification on the result of the first verification and output the final verification result.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure includes: The storage cell array comprises eight storage cells and eight read / write control circuits, each read / write control circuit comprising 16 sub-circuits; wherein each storage cell array is connected to the corresponding sub-circuit of the read / write control circuit via 16 first data lines. Four first-level verification units and three second-level verification units; wherein the three second-level verification units include two first-level verification units and one second-level verification unit; the first-level verification units and the second-level verification units are arranged alternately along the first direction.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure includes: The first-level verification unit connects two adjacent read / write control circuits through a first wire in the first metal layer, and the first wire extends along the second direction; The first verification unit connects two first-stage verification units through a second wire in the second metal layer, and the second wire extends along the first direction; The second verification unit is connected to two first verification units via a second wire in the second metal layer, and the second wire extends along the first direction.

12. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a plurality of sub-word line drivers; The sub-word line driver and the memory cell array are arranged alternately along the first direction; the sub-word line driver is used to control the word lines in the memory cell array.

13. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 12.

14. A layout structure for a memory, characterized in that, include: A layout of multiple memory cell arrays arranged side-by-side along a first direction; A plurality of read / write control circuit layouts are arranged side-by-side along the first direction, each corresponding to one of the memory cell array layouts. The read / write control circuit layouts are located on one side of the memory cell array in a second direction, which is perpendicular to the first direction. Multiple first data line patterns extending along the second direction, the first data line patterns being located on the side of the read / write control circuit layout close to the memory cell array layout, the memory cell array layout being connected to the corresponding read / write control circuit layout through the first data line patterns; The verification circuit layout is located on the side of the read / write control circuit layout away from the memory cell array layout, so that the memory cell array layout and the read / write control circuit layout correspond one-to-one in the second direction. The memory cell array layout and the read / write control circuit layout are connected by a straight first data line pattern.

15. The layout structure according to claim 14, characterized in that: Multiple verification circuit layouts arranged side-by-side along the first direction; At least one of the verification circuit layouts is connected to at least one of the read / write control circuit layouts.

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