Adapter plate, method of forming the same, and package structure

Abstract

Embodiments of the present disclosure provide a transition board, a forming method thereof and a package structure. The transition board includes a first sub-transition board including a substrate, a substrate via and a first interconnection structure and a first bonding structure located on a first side of the substrate, the substrate via extending through the substrate and electrically connected to the first interconnection structure, the first bonding structure located on a side of the first interconnection structure away from the substrate and electrically connected to the first interconnection structure; a second sub-transition board electrically connected to the first sub-transition board and including a second interconnection structure and a second bonding structure, the second bonding structure bonded to the first bonding structure, and the second interconnection structure located on a side of the second bonding structure away from the first sub-transition board; a first conductive bump disposed on a second side of the substrate and electrically connected to the first interconnection structure through the substrate via; and a second conductive bump disposed on a side of the second interconnection structure away from the second bonding structure and electrically connected to the second interconnection structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an adapter board, a method of forming the same, and a packaging structure. Background Technology

[0002] In semiconductor packaging processes, interposers are used to interconnect semiconductor devices. For example, in a traditional chip-on-wafer-on-substrate (CoWoS) package, the interposer is positioned between multiple dies and the package substrate, interconnecting them. Traditional interposers are typically used for short-distance traces but cannot support long-distance, high-frequency traces. Dies requiring long-distance, high-frequency interconnection must be interconnected via the package substrate. The CoWoS package structure can be further mounted onto a circuit board, for example, by connecting it to a PCB or other circuit board via conductive bumps on the side of the package substrate away from the interposer, with the package substrate positioned between the interposer and the circuit board.

[0003] Traditional CoWoS packaging often uses Ajinomoto Build-up Film (ABF) substrates as the packaging substrate, and the production capacity of traditional packaging substrates (e.g., ABF substrates) directly affects the production capacity of CoWoS packaging. The production capacity of traditional CoWoS packaging may be limited by the limited production capacity of ABF substrates. Summary of the Invention

[0004] This disclosure provides a novel adapter board, a packaging device including the adapter board, and a method for forming the novel adapter board. The novel adapter board not only performs the functions of an adapter board but also functions as a packaging substrate, thereby replacing traditional packaging substrates (e.g., ABF substrates), and thus enabling the production capacity of the packaging device to be free from the production capacity limitations of traditional packaging substrates.

[0005] According to at least one embodiment of the present disclosure, an adapter board is provided, comprising: a first sub-adapter board including a substrate, a substrate via, a first interconnect structure, and a first bonding structure, the substrate having a first side and a second side opposite to each other, the first interconnect structure and the first bonding structure being disposed on the first side of the substrate, the substrate via extending through the substrate and electrically connected to the first interconnect structure, and the first bonding structure being disposed on the side of the first interconnect structure away from the substrate and electrically connected to the first interconnect structure; a second sub-adapter board disposed on the first sub-adapter board and electrically connected to the first sub-adapter board, the second sub-adapter board including a second interconnect structure and a second bonding structure, the second bonding structure being bonded to the first bonding structure, and the second interconnect structure being located on the side of the second bonding structure away from the first sub-adapter board; a first conductive bump disposed on the second side of the substrate of the first sub-adapter board and electrically connected to the first interconnect structure through the substrate via; and a second conductive bump disposed on the side of the second interconnect structure of the second sub-adapter board away from the second bonding structure and electrically connected to the second interconnect structure.

[0006] According to at least one embodiment of the present disclosure, an adapter board is provided, comprising: a substrate; a first interconnect structure disposed on the substrate and including a first conductive line and a first conductive via, the first conductive via being located between and electrically connected to the first conductive line; a second interconnect structure disposed on a side of the first interconnect structure away from the substrate and including a second conductive line and a second conductive via, the second conductive via being located between and electrically connected to the second conductive line; a substrate via extending through the substrate and electrically connected to the first conductive line of the first interconnect structure; a first conductive bump disposed on a side of the substrate away from the first interconnect structure and electrically connected to the substrate via; and a second conductive bump disposed on a side of the second interconnect structure away from the first interconnect structure and electrically connected to the second conductive line, wherein the first conductive line and the second conductive line have different linewidths.

[0007] At least one embodiment of this disclosure provides a packaging structure comprising: an adapter board according to any of the preceding claims; and a plurality of dies arranged side-by-side on the adapter board and connected to the adapter board via a second conductive bump, wherein a second interconnection structure is disposed between the plurality of dies and the first interconnection structure, some of the plurality of dies are interconnected via the first interconnection structure, and others of the plurality of dies are interconnected via the second interconnection structure.

[0008] At least one embodiment of this disclosure provides a packaging structure comprising: an adapter board according to any of the preceding claims; and a plurality of main control dies and a plurality of memory dies arranged side-by-side on the adapter board and connected to the adapter board via a second conductive bump, wherein a first sub-adapter board provides interconnection between at least some of the plurality of main control dies, a second sub-adapter board provides interconnection between at least one of the plurality of main control dies and a corresponding memory die, and a third sub-adapter board provides at least one of interconnection between some of the plurality of main control dies and interconnection between one or more of the plurality of main control dies and a corresponding memory die.

[0009] At least one embodiment of this disclosure provides a method for forming an adapter plate, comprising: providing a first substrate; forming a substrate via in the first substrate; forming a first interconnect structure on a first side of the first substrate, the first interconnect structure being electrically connected to the substrate via; forming a first bonding structure on a side of the first interconnect structure away from the first substrate, the first bonding structure being electrically connected to the first interconnect structure; providing a second substrate; forming a second interconnect structure on the second substrate, and forming a second bonding structure on a side of the second interconnect structure away from the second substrate, the second bonding structure being electrically connected to the second interconnect structure; bonding the second bonding structure on the second substrate to the first bonding structure on the first substrate; removing the second substrate to expose a side of the second interconnect structure away from the second bonding structure; forming a first conductive bump on a second side of the first substrate away from the first interconnect structure; and forming a second conductive bump on the side of the second interconnect structure away from the second bonding structure.

[0010] In various embodiments of this disclosure, a novel adapter board is formed by joining multiple sub-adaptor boards together. These sub-adaptor boards can be configured with conductive layers of the same or different linewidths and / or thicknesses based on product requirements. Alternatively, an interconnect structure with conductive layers of different linewidths can be formed within a single sub-adaptor board. This allows the adapter board of this disclosure to simultaneously possess the functions of a traditional adapter board and a packaging substrate, satisfying interconnection needs between multiple dies and supporting long-distance, high-frequency routing to meet various routing requirements and protocol interface transmission requirements. In this way, the adapter board of this disclosure can replace the combination of a traditional adapter board and a packaging substrate, and the packaging substrate can be omitted in the packaging structure, freeing the packaging structure from the limitations of traditional packaging substrate capacity, thereby improving the packaging structure's capacity and yield. Furthermore, it avoids potential problems in the connection between traditional adapter boards and packaging substrates, thereby improving the device performance of the packaging structure. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0012] Figure 1A A schematic cross-sectional view of an adapter plate according to some embodiments of the present disclosure is shown.

[0013] Figure 1B A schematic cross-sectional view of an adapter plate according to other embodiments of the present disclosure is shown.

[0014] Figure 2A Some embodiments according to this disclosure are shown. Figure 1A An enlarged schematic diagram of a portion of the interconnect structure in the adapter board shown.

[0015] Figure 2B An enlarged schematic diagram of a portion of the interconnect structure in an adapter board according to other embodiments of the present disclosure is shown.

[0016] Figure 2C Some embodiments according to this disclosure are shown. Figure 1A An enlarged schematic diagram of a portion of the joint structure in the adapter plate shown.

[0017] Figures 3A to 3D A schematic cross-sectional view of an adapter plate according to other embodiments of the present disclosure is shown.

[0018] Figures 4A to 4M A schematic cross-sectional view is shown illustrating a method of forming an adapter plate according to some embodiments of the present disclosure.

[0019] Figure 5A A schematic top view of a packaging structure according to some embodiments of the present disclosure is shown.

[0020] Figure 5B and Figure 5C A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0022] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0023] This disclosure provides a novel adapter board that simultaneously functions as both a traditional adapter board and a packaging substrate, thereby replacing traditional packaging substrates (e.g., ABF substrates). This allows the production capacity of the packaging device to be unrestricted by the production capacity of traditional packaging substrates. The adapter board in some embodiments of this disclosure includes a plurality of stacked sub-adaptor boards, which are joined and electrically connected to each other by hybrid bonding or by conductive connectors. Each of the sub-adaptor boards includes an interconnection structure with one or more layers of conductive lines. The interconnection structures of different sub-adaptor boards can be formed with conductive lines having the same or different linewidths / spacings and thicknesses based on product requirements. The number of sub-adaptor boards can be set and adjusted according to product requirements, thereby enabling multiple sub-adaptor boards to provide interconnection between different chips. Other embodiments of this disclosure provide an adapter board including interconnection structures that can provide different routing requirements. The interconnection structures include conductive lines with different linewidths / spacings and thicknesses, thereby meeting the transmission requirements of multiple protocol interfaces.

[0024] Figure 1A This is a schematic cross-sectional view of an adapter plate according to some embodiments of the present disclosure. Figure 2A Some embodiments according to this disclosure are shown. Figure 1A An enlarged schematic diagram of a portion of the interconnect structure MS1 in the adapter board shown. Figure 2B An enlarged schematic diagram of a portion of the interconnect structure in an adapter board according to other embodiments of the present disclosure is shown. Figure 2C Some embodiments according to this disclosure are shown. Figure 1A An enlarged schematic diagram of a portion of the joint structure in the adapter plate shown.

[0025] Reference Figure 1AIn some embodiments, the interposer 500a includes a plurality of stacked sub-interposers electrically connected to each other, and includes, for example, sub-interposers IP1 and IP2. In some embodiments, the interposer 500a may also be referred to as a stacked interposer, sub-interposer IP1 may be referred to as the bottom sub-interposer, and sub-interposer IP2 may be referred to as the top sub-interposer. Sub-interposers IP1 and IP2 are joined and electrically connected to each other through their respective bonding structures. For example, sub-interposer IP1 includes a substrate 100, a through substrate via (TSV) 102, an insulating layer 101, an interconnect structure MS1 and a bonding structure BS1 disposed on a first side of the substrate 100, a conductive structure CS disposed on a second side of the substrate 100, passivation layers 110 and 112, a conductive pad 111, and a conductive connector 120. The first and second sides of the substrate 100 are opposite to each other and may be referred to as the front side and back side of the substrate 100, respectively. The sub-interface IP2 includes an interconnect structure MS2, a bonding structure BS2, passivation layers 210 and 212, a conductive pad 211, and a conductive connector 220.

[0026] In some embodiments, substrate 100 may be a semiconductor substrate, such as a silicon substrate, but may alternatively or additionally include other semiconductor materials. Substrate via 102 extends through substrate 100 and is electrically connected to conductive features (e.g., conductive lines BM1 and conductive layer BL) in interconnect structure MS1 and conductive structure CS. Insulating layer 101 is disposed between substrate via 102 and substrate 100 to physically and electrically isolate substrate via 102 and substrate 100. In some embodiments, insulating layer 101 further extends to cover a surface of substrate 100 near the interconnect structure MS1 (i.e., the front surface).

[0027] The interconnect structure MS1 may include a dielectric structure made of one or more layers of dielectric material and one or more conductive layers embedded in the dielectric structure. The conductive layers may include, for example, conductive lines and / or conductive vias and are electrically connected to the substrate via 102. For example, the interconnect structure MS1 includes dielectric material layers 1051, 1061, 1052, 1062, and 1053, and conductive lines BM1, conductive vias BV1, BM2, BV2, and BM3 respectively embedded in the aforementioned dielectric material layers. It should be understood that the number of dielectric material layers and conductive lines / conductive vias shown in the figures are merely illustrative and are not intended to limit the scope of this disclosure.

[0028] Dielectric material layers 1051, 1052, and 1053 are respectively disposed on the sides of conductive lines BM1, BM2, and BM3 and laterally surround the corresponding conductive lines BM1, BM2, and BM3 in a direction parallel to the main surface of the substrate 100. Dielectric material layers 1061 and 1062 are respectively disposed on the sides of conductive vias BV1 and BV2 and laterally surround the corresponding conductive lines BV1 and BV2 in a direction parallel to the main surface of the substrate 100. Dielectric material layers 1051-1053 and dielectric material layers 1061-1062 may each be a single-layer or multi-layer structure, and the number of dielectric material layers they each include may be the same or different. In some embodiments, dielectric material layers 1051-1053 include substantially the same structure, for example, each including two layers of dielectric material; dielectric material layers 1061-1062 include substantially the same structure, for example, each including four layers of dielectric material. For example, dielectric material layers 1051-1053 each include dielectric layer 105a and dielectric layer 105b. Dielectric layers 105a and 105b are made of different materials and have an etching selectivity in the etching process for forming vias for conductive lines. Dielectric layer 105a acts as an etching stop layer. Therefore, dielectric layer 105a can also be called an etching stop layer. In some embodiments, dielectric material layers 1061-1062 each include dielectric layers 106a1, 106b1, 106a2, and 106b2; dielectric layers 106a1 and 106a2 may comprise the same material, and dielectric layers 106b1 and 106b2 may comprise the same material, but the materials of dielectric layers 106b1 and 106b2 may be different from those of dielectric layers 106a1 and 106a2. In some embodiments, dielectric layers 106a1 and 106a2 act as etch stop layers in the etching process for forming vias for conductive vias, and are therefore also referred to as etch stop layers 106a1 and 106a2. That is, the interconnect structure MS1 includes alternately stacked etch stop layers and dielectric layers.

[0029] In some embodiments, etch stop layers 105a, 106a1, and 106a2 may comprise the same material, such as silicon nitride, and dielectric layers 105b, 106b1, and 106b2 may comprise the same material, such as silicon oxide, but this disclosure is not limited thereto. The thicknesses of the respective etch stop layers may be the same or different, and the thicknesses of the respective dielectric layers may be the same or different. In some embodiments, the thicknesses of the respective dielectric material layers located on the sides of the plurality of conductive lines are substantially the same as each other, the thicknesses of the respective dielectric material layers located on the sides of the plurality of conductive vias are substantially the same as each other, while the thickness of the dielectric material layer located on the sides of the conductive vias may be the same as or different from (e.g., greater than) the thickness of the dielectric material layer located on the sides of the conductive lines.

[0030] Conductive line BM1 extends through dielectric material layer 1051 and is electrically connected to substrate via 102. Conductive via BV1 extends through dielectric material layer 1061 and is electrically connected to conductive line BM1. Conductive line BM2 extends through dielectric material layer 1052 and is electrically connected to conductive via BV1. Conductive via BV2 extends through dielectric material layer 1062 and is electrically connected to conductive line BM2. Conductive line BM3 extends through dielectric material layer 1053 and is electrically connected to conductive via BV2. In other words, conductive lines in adjacent layers are connected to each other through conductive vias.

[0031] In some embodiments, in the interconnect structure MS1, the thickness of each conductive line BM1-BM3 is approximately the same as the thickness of the corresponding dielectric material layers 1051-1053, and the thicknesses of the conductive lines BM1-BM3 may be approximately the same or different; the thickness of each conductive via BV1-BV2 is approximately the same as the thickness of the corresponding dielectric material layers 1061-1062, and the thicknesses of each conductive via BV1-BV2 may be approximately the same or different. It should be understood that, herein, thickness refers to the thickness in the direction perpendicular to the main surface of the substrate 100.

[0032] For example, refer to Figure 1A and Figure 2A Taking conductive lines BM1 and BM2 and the conductive via BV1 between them as an example, in some embodiments, conductive lines BM1 and dielectric material layer 1051, and conductive lines BM2 and dielectric material layer 1052, have approximately the same thickness T1. The conductive via BV1 and dielectric material layer 1061 have a thickness T2, which is approximately equal to the distance between conductive lines BM1 and BM2 in the direction perpendicular to the main surface of the substrate 100. In some embodiments, the thickness T2 of the conductive via BV1 is greater than or at least equal to the thickness T1 of conductive lines BM1 / BM2, that is, the distance between conductive lines BM1 and BM2 is greater than or at least equal to the thickness of the conductive lines, and the thickness of dielectric material layer 1061 is greater than or at least equal to the respective thicknesses of dielectric material layers 1051 and 1052. The conductive via BV1 may include one or more layers of vias. In the case where the conductive via BV1 includes multiple layers of vias, the thickness T2 refers to the overall thickness of the multiple layers of vias in the conductive via BV1.

[0033] In some embodiments, the conductive via BV1 comprises multiple interconnected vias, each of which may be embedded in a different dielectric layer, for example, each may be embedded in a set of dielectric material sublayers formed by an etch stop layer and a dielectric layer. The conductive via BV2 may also have a similar structure. For example, as... Figure 1A and Figure 2AAs shown, conductive via BV1 includes sub-via 1a and sub-via 1b located on sub-via 1a, and conductive via BV2 includes sub-via 2a and sub-via 2b located on sub-via 2a. Sub-vias 1a and 2a are respectively embedded in a dielectric material sublayer composed of an etch stop layer 106a1 and a dielectric layer 106b1; sub-vias 1b and 2b are respectively embedded in a dielectric material sublayer composed of an etch stop layer 106a2 and a dielectric layer 106b2. The structures of conductive via BV2 and conductive via BV1 can be roughly the same; the following description uses conductive via BV1 as an example.

[0034] In some embodiments, the thicknesses of sub-vias 1a and 1b of conductive via BV1 may be substantially the same and may both be greater than the thickness T1 of conductive lines BM1 and BM2, but this disclosure is not limited thereto. In other embodiments, as long as the overall thickness T2 of sub-vias 1a and 1b is greater than or at least equal to the thickness T1, the thicknesses of sub-vias 1a and 1b may be the same or different from each other, and their respective thicknesses may be greater than, substantially equal to, or less than the thickness T1. Sub-vias 1a and 1b may have different widths; for example, the width W1 of sub-via 1a may be less than the width W2 of sub-via 1b, but this disclosure is not limited thereto. In other embodiments, the width W1 of sub-via 1a may also be substantially equal to or greater than the width W2 of sub-via 1b. It should be understood that the width of the vias mentioned above refers to their width in a direction parallel to the main surface of the substrate 100. Furthermore, although an interface is shown between sub-vias 1a and 1b in the figures, this disclosure is not limited thereto. In some embodiments, sub-holes 1a and 1b are formed simultaneously, and there may be no obvious interface between them.

[0035] In some embodiments, the thickness of the etch stop layer formed around each conductive via and conductive line is substantially the same, the thickness of the dielectric layer around each conductive line is substantially the same, the thickness of the dielectric layer around each conductive via is substantially the same, and the thickness of the dielectric layer around each conductive via is greater than or equal to the thickness of the dielectric layer around each conductive line; when the conductive via includes multiple sub-vias, the thickness of the dielectric layer around the conductive via refers to the sum of the thicknesses of the dielectric layers around each sub-via. For example, refer to... Figure 1A and Figure 2AThe etch stop layers 105a in dielectric material layers 1051, 1052, and 1053, and the etch stop layers 106a1 and 106a2 in dielectric material layers 1061 and 1062, have approximately the same thickness; the thickness of dielectric layer 105b in dielectric material layer 1051 is approximately the same as that in dielectric material layer 1052; the sum of the thicknesses of dielectric layers 106b1 and 106b2 in dielectric material layer 1061 is approximately equal to the sum of the thicknesses of dielectric layers 106b1 and 106b2 in dielectric material layer 1062; while the sum of the thicknesses of dielectric layers 106b1 and 106b2 is greater than or equal to the thickness of dielectric layer 105b. Figure 2A As shown, in some examples, the thicknesses of dielectric layers 106b1 and 106b2 may be approximately the same and both greater than the thickness of dielectric layer 105b, but this disclosure is not limited thereto. The thicknesses of dielectric layers 106b1 and 106b2 may be the same or different from each other, and as long as the overall thickness of dielectric material layers 1061 and 1062 is greater than or at least equal to the thickness of dielectric material layers 1051, 1052, and 1053, the thicknesses of dielectric layers 106b1 and 106b2 may be greater than, equal to, or less than the thickness of dielectric layer 105b.

[0036] Reference Figure 2B In other embodiments, the via BV1 may be a single-layer structure, extending continuously between the opposing surfaces of conductive lines BM1 and BM2 in a direction perpendicular to the main surface of the substrate 100. The thickness T2 of the via BV1 is greater than or at least equal to the thickness T1 of conductive lines BM1 and BM2. In this embodiment, the dielectric material layer 1061 surrounding the via BV1 is a two-layer structure including an etch stop layer 106a and a dielectric layer 106b. The thickness of the etch stop layer 106a may be approximately equal to the thickness of the etch stop layer 105a, and the thickness of the dielectric layer 106b is greater than or at least equal to the thickness of the dielectric layer 105b.

[0037] It should be understood that the number of layers of the through-hole BV1 and the number of layers of dielectric material surrounding it shown in the figure are merely illustrative and are not intended to limit the scope of this disclosure. In other embodiments, the number of layers of the through-hole BV1 may be greater than two and may be adjusted according to product requirements.

[0038] In the embodiments of this disclosure, by providing two layers of through holes and / or setting the thickness of the dielectric material layer mentioned above between the conductive lines, the distance between adjacent conductive lines in the direction perpendicular to the main surface of the substrate can be increased. This can avoid signal interference caused by the adjacent conductive lines being too close when transmitting signals as signal lines, thereby improving the performance of the device.

[0039] Continue to refer to Figure 1AThe sub-interface board IP1 includes a bonding structure BS1 disposed on and electrically connected to the interconnect structure MS1. In some embodiments, the bonding structure BS1 includes a bonding dielectric structure 108 and a bonding pad structure 109. The bonding pad structure 109 is embedded in the bonding dielectric structure 108 and extends through the bonding dielectric structure 108 to be electrically connected to the topmost conductive feature (e.g., conductive line BM3) of the interconnect structure MS1. The bonding dielectric structure 108 and the bonding pad structure 109 may each be a single-layer or multi-layer structure. For example, refer to... Figure 1A and Figure 2C In some embodiments, the bonding dielectric structure 108 includes a three-layer structure, and may include, for example, an etch stop layer 108a, a dielectric layer 108b, and a bonding layer 108c. The etch stop layer 108a is located on the dielectric material layer 1053 of the interconnect structure MS1, and the dielectric layer 108b is disposed on the side of the etch stop layer 108a away from the interconnect structure MS1 and is located between the etch stop layer 108a and the bonding layer 108c. In some embodiments, the bonding pad structure 109 includes a via portion 109a and a pad portion 109b. The via portion 109a is, for example, embedded in the etch stop layer 108a and the dielectric layer 108b, and the pad portion 109b is, for example, embedded in the bonding layer 108c and the dielectric layer 108b, but this disclosure is not limited thereto. In some embodiments, the surface of the bonding pad structure 109 away from the interconnect structure MS1 (i.e., the top surface of the bonding pad portion 109b shown in the figure) and the surface of the bonding dielectric structure 108 away from the interconnect structure MS1 (i.e., the top surface of the bonding layer 108c shown in the figure) are substantially coplanar and flush in a direction parallel to the main surface of the substrate 100. In some embodiments, the bonding dielectric structure may include a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and the material of the dielectric layer 108b may be different from the materials of the etch stop layer 108a and the bonding layer 108c. For example, the etch stop layer 108a includes silicon nitride, the dielectric layer 108b includes silicon oxide, and the bonding layer 108c includes another dielectric material different from silicon oxide and silicon nitride. The bonding pad structure 109 includes a conductive material, such as a metallic material including copper. In some embodiments, the through-hole portion 109a and the pad portion 109b may have different dimensions (e.g., width, thickness, etc.), but may also have the same dimensions (e.g., width, thickness, etc.), and there may be an interface between the through-hole portion 109a and the pad portion 109b, but may also be substantially without a visible interface.

[0040] In some embodiments, the sub-interchange board IP2 includes an interconnect structure MS2 and a bonding structure BS2 disposed on the interconnect structure MS2. The bonding structure BS2 is bonded to the bonding structure BS1, such that the sub-interchange board IP2 and the sub-interchange board IP1 are bonded together by the bonding structure BS2 and the bonding structure BS1 engaging with each other; the interconnect structure MS2 is located on the side of the bonding structure BS2 away from the sub-interchange board IP1. The structures of the interconnect structure MS2 and the bonding structure BS2 are similar to, and may be substantially the same as, or different from, the structures of the interconnect structure MS1 and the bonding structure BS1, respectively. In some embodiments, the interconnect structure MS2 and the bonding structure BS2 may be substantially symmetrical to the interconnect structure MS1 and the bonding structure BS1 with respect to the bonding interface of the bonding structure BS2 and the bonding structure BS1, but this disclosure is not limited thereto.

[0041] For example, the interconnect structure MS2 includes dielectric material layers 2051, 2061, 2052, 2062, and 2053, and conductive lines TM1, conductive vias TV1, conductive lines TM2, conductive vias TV2, and conductive lines TM3 respectively embedded in the corresponding dielectric material layers. Conductive lines TM1-TM3 extend through their corresponding dielectric material layers to electrically connect with their corresponding conductive vias. Conductive vias TV1-TV2 extend through their corresponding dielectric material layers and electrically connect with adjacent conductive lines. Conductive vias TV1 and TV2 can each be single-layer or multi-layer vias. Dielectric material layers 2051, 2061, 2052, 2062, and 2053 can each be single-layer or multi-layer structures. For example, dielectric material layers 2051, 2052, and 2053 can each include an etch stop layer 205a and a dielectric layer 205b, and dielectric material layers 2061 and 2062 can each include overlapping etch stop layers 206a1 and 206a2 and dielectric layers 206b1 and 206b2. The thickness of the conductive vias and their corresponding dielectric material layers is greater than or at least equal to the thickness of the conductive lines and their corresponding dielectric material layers.

[0042] Reference Figure 1A and Figure 2CThe bonding structure BS2 includes a bonding dielectric structure 208 and a bonding pad structure 209 embedded in the bonding dielectric structure 208. The bonding pad structure 209 extends through the bonding dielectric structure 208 and is electrically connected to the conductive line BM3 of the interconnect structure MS2. The bonding dielectric structure 208 and the bonding pad structure 209 may each be a single-layer or multi-layer structure. For example, the bonding dielectric structure 208 may include an etch stop layer 208a, a dielectric layer 208b, and a bonding layer 208c; the bonding pad structure 209 may include a via portion 209a and a pad portion 209b; the via portion 209a may be embedded in the etch stop layer 208a and the dielectric layer 208b, and the pad portion 209b may be embedded in the dielectric layer 208b and the bonding layer 208c. The structural positional relationships between the various conductive features and dielectric material layers of the interconnect structure MS2 and between the various conductive features and dielectric structures in the bonding structure BS2 are consistent with the aforementioned reference. Figure 1A and Figure 2A , 2B The interconnection structure MS1 and the junction structure BS1 described in 2C are similar, and will not be described again here.

[0043] Reference Figure 1A and Figure 2C In some embodiments, bonding structures BS1 and BS2 are bonded to each other via hybrid bonding, wherein bonding dielectric structures 108 and 208 are bonded to each other via dielectric-to-dielectric bonding, and bonding pad structures 109 and 209 are bonded to each other via metal-to-metal bonding. A hybrid bonding interface is present between bonding structures BS1 and BS2. For example, the hybrid bonding interface includes a dielectric-to-dielectric bonding interface between bonding dielectric structure 108 (e.g., its bonding layer 108c) and bonding dielectric structure 208 (e.g., its bonding layer 208c), and a metal-to-metal bonding interface between bonding pad structure 109 (e.g., its pad portion 109b) and bonding pad structure 209 (e.g., its pad portion 209b).

[0044] In some embodiments, sub-interface IP1 has a substrate 100 and a substrate via 102 on the side of interconnect structure MS1 away from bonding structure BS1 and sub-interface IP2, while sub-interface IP2 may not have a semiconductor substrate and substrate via on the side of interconnect structure MS2 away from bonding structure BS2 and sub-interface IP1. Sub-interface IP2 may not have a semiconductor substrate, and may not have a semiconductor substrate between interconnect structure MS2 and interconnect structure MS1. In some embodiments, sub-interface IP2 includes passivation layers 210 and 212, conductive pads 211, and conductive connectors 220 disposed on the side of interconnect structure MS2 away from bonding structure BS2 and sub-interface IP1. A passivation layer 210 is disposed on the interconnect structure MS2 and can directly contact the dielectric material layer 2051 of the interconnect structure MS2; a conductive pad 211 is disposed on the side of the passivation layer 210 away from the interconnect structure MS2 and extends through the passivation layer 210 to be electrically connected to the conductive layer (e.g., conductive line TM1) of the interconnect structure MS2, and the conductive pad 211 is in direct contact with the conductive feature (e.g., conductive line TM1) closest to the passivation layer 210 in the interconnect structure MS2; a passivation layer 212 is disposed on the side of the passivation layer 210 and the conductive pad 211 away from the interconnect structure MS2, and a conductive connector 220 extends through the passivation layer 212 and is electrically connected to the conductive pad 211.

[0045] In some embodiments, the sub-interface IP1 includes a conductive structure CS, passivation layers 110 / 120, conductive pads 111, and conductive connectors 120 disposed on the side of the substrate 100 away from the interconnect structure MS1. The conductive structure CS includes one or more dielectric layers and one or more conductive layers embedded in the one or more dielectric layers. The structure of the conductive structure CS may be similar to that of the interconnect structure MS1, and may include the same or different number of conductive layers as in the interconnect structure MS1. For example, the conductive structure CS includes a dielectric material layer having an etch stop layer 55a and a dielectric layer 55b, and a conductive layer BL, the conductive layer BL being embedded in the dielectric material layer and extending through the dielectric material layer to be electrically connected to the substrate via 102. It should be understood that the number of dielectric material layers and conductive layers in the conductive structure CS shown in the figures are merely illustrative and are not intended to limit the scope of this disclosure. A passivation layer 110 is disposed on the side of the conductive structure CS away from the substrate 100. A conductive pad 111 extends through the passivation layer 110 to be electrically connected to the conductive layer BL and the substrate via 102, and is also electrically connected to the conductive layer in the interconnect structure MS1 through the conductive layer BL and the substrate via 102. A passivation layer 112 is disposed on the side of the passivation layer 110 and the conductive pad 111 away from the substrate 100. A conductive connector 120 extends through the passivation layer 112 to be electrically connected to the conductive pad 111. The conductive structure CS is selectively disposed on the back side of the substrate 100; in some embodiments, the conductive structure CS may be omitted, and the conductive pad 111 may be directly connected to the substrate via 102.

[0046] Conductive connectors 120 and 220 are conductive terminals of adapter board 500a for external connections to adapter board 500a. In some embodiments, conductive connectors 120 and 220 may be conductive bumps, and may include, for example, solder balls. Conductive connectors 120 and 220 may be the same type or different types of conductive bumps, and may have the same or different dimensions. In some examples, conductive connectors 120 and 220 may be different types of conductive bumps, and one of conductive connectors 120 and 220 may be larger than the other; for example, conductive connector 120 may be larger than conductive connector 220. For example, conductive connector 120 is a controlled collapsed chip connection (C4) bump, while conductive connector 220 is a micro bump; in other examples, conductive connectors 120 and 220 are the same type of conductive bumps, for example, both are C4 bumps, and have substantially the same size. However, this disclosure is not limited thereto, and the conductive connectors 120 and 220 may be selected according to the appropriate bump type and size as required by the product.

[0047] Figure 1B A schematic cross-sectional view of an adapter plate 500b according to other embodiments of the present disclosure is shown. The adapter plate 500b and... Figure 1A The adapter plate 500a shown is similar, but the difference lies in the way the sub-adapter plates are joined, which is different from that of adapter plate 500a.

[0048] Reference Figure 1B In some embodiments, the adapter plate 500b further includes a conductive connector BP disposed between sub-adapter plates IP1 and IP2 and an underfill layer UF. The conductive connector BP is disposed between bonding pad structures 109 and 209 of bonding structures BS1 and BS2, such that bonding pad structures 109 and 209 are bonded and electrically connected to each other through the conductive connector BP. The underfill layer fills the space between sub-adapter plates IP1 and IP2 and laterally surrounds the conductive connector BP in a direction parallel to the main surface of the substrate 100. The conductive connector BP may be a conductive bump, such as a microbump. In some embodiments, the conductive connector BP is a solder ball. The dimensions (e.g., width, height, volume, etc.) of the conductive connector BP may be smaller than the dimensions (e.g., width, height, volume, etc.) of the conductive connectors 120 and 220; in some embodiments where the conductive connector 220 is a microbump, the dimensions of the conductive connector BP are also approximately equal to or smaller than the dimensions of the conductive connector 220, and smaller than the dimensions of the conductive connector 120. However, this disclosure is not limited thereto. Other structures of the adapter board 500b are similar to those of the adapter board 500a, and will not be described in detail here.

[0049] Reference Figure 1A and Figure 1B In some embodiments, in adapter plates 500a and 500b, the linewidth and / or spacing of the individual conductive lines in the interconnect structures MS1 and MS2 of sub-adapter plates IP1 and IP2 may be substantially the same as each other, for example, less than 20 μm / 20 μm or less than 12 μm / 12 μm. It should be understood that the linewidth here refers to the width of each conductive line in a direction parallel to the main surface of substrate 100 and perpendicular to the direction of extension of the conductive line, and the spacing refers to the distance between adjacent conductive lines located in the same layer in a direction parallel to the main surface of substrate 100. In some embodiments, the thickness of the individual conductive lines in interconnect structures MS1 and MS2 in a direction perpendicular to the main surface of substrate 100 may also be substantially the same as each other, but this disclosure is not limited thereto.

[0050] Figures 3A to 3DSchematic cross-sectional views of adapter plates 500c-500f according to other embodiments of the present disclosure are shown. Adapter plates 500c-500f are structurally similar to the aforementioned adapter plates, differing only in the setting of line width / spacing in the sub-adapter plates and / or the number of sub-adapter plates. The differences between adapter plates 500c-500f and the aforementioned adapter plates will be described in detail below, and parts similar to the aforementioned adapter plates will not be described again. It should be noted that, for the sake of brevity, Figures 3A to 3D The diagram briefly illustrates interconnection structures, joining structures, and other components, and the specific structures of these components can be compared with those mentioned above. Figures 1A to 2C Similar to that described for adapter board 500a. For example, multiple dielectric material layers in interconnect structures MS1 and MS2... Figures 3A-3D The dielectric structures 107 and 207 are briefly shown in the figure, and the dielectric structures 107 and 207 may, for example, include the following: Figure 1A The plurality of dielectric material layers 1051-1053 and 1061-1062 and the plurality of dielectric material layers 2051-2053 and 2061-2062 are shown.

[0051] Reference Figure 3A In some embodiments, in the adapter board 500c, the linewidth / spacing and thickness T1 of the conductive lines BM1-BM3 located on different layers in the interconnect structure MS1 of the sub-adapter board IP1 can be approximately the same, and the linewidth / spacing and thickness T1' of the conductive lines TM1-TM3 located on different layers in the interconnect structure MS2 of the sub-adapter board IP2 can be the same. In some embodiments, the linewidth / spacing of the conductive lines in the interconnect structure MS1 is greater than that of the conductive lines in the interconnect structure MS2. For example, the linewidth / spacing of the conductive lines in the interconnect structure MS1 is 2μm / 2μm, while the linewidth / spacing of the conductive lines in the interconnect structure MS2 is 0.4μm / 0.4μm. It should be understood that this is only illustrative and is not intended to limit the scope of this disclosure. The interconnect structures MS1 and MS2 can be selected with appropriate linewidth / spacing according to product requirements (e.g., the routing requirements of the devices they are connected to). In some embodiments, the thickness T1 of the conductive line in interconnect structure MS1 is greater than the thickness T1' of the conductive line in interconnect structure MS2, and the thickness of the conductive vias BV1 / BV2 can be greater than the thickness of the conductive vias TV1 / TV2; correspondingly, the thickness of the dielectric material layer around the corresponding conductive line / conductive via in interconnect structure MS1 is also greater than the thickness of the dielectric material layer around the corresponding conductive line / conductive via in interconnect structure MS2. In various embodiments of this disclosure, the linewidth range of the conductive line in interconnect structure MS1 in sub-interface IP1 is, for example, 1 μm to 20 μm, and the thickness range is, for example, 2 μm to 3.3 μm, while the linewidth range of the conductive line in interconnect structure MS2 in sub-interface IP2 is, for example, 0.4 μm to 6 μm, and the thickness range is, for example, 0.6 μm to 1 μm. The line spacing of the corresponding conductive line can be the same as or different from its linewidth.

[0052] Reference Figure 3B In some embodiments, the adapter plate may further include two or more sub-adapter plates stacked on top of each other, each sub-adapter plate being individually joined and electrically connected to each other by hybrid bonding or using conductive connectors (e.g., conductive bumps). For example, such as Figure 3B As shown, in some embodiments, the adapter plate 500d includes sub-adapter plates IP1, IP2, and IP3 that are joined and electrically connected to each other. The structures of sub-adapter plates IP1 and IP2 are similar to those in the aforementioned embodiments and will not be described again here. Sub-adapter plate IP3 is located between sub-adapter plates IP1 and IP2, for example, in a direction perpendicular to the main surface of the substrate 100, and is joined to sub-adapter plates IP1 and IP3, for example, by a hybrid bonding method. For example, sub-adapter plate IP3 includes an interconnect structure MS3 and bonding structures BS3 and BS4 disposed on opposite sides of the interconnect structure MS3 in a direction perpendicular to the main surface of the substrate 100. The specific structures of the interconnect structure MS3 and bonding structures BS3-BS4 are similar to the interconnect structures and bonding structures described with respect to sub-adapter plates IP1 and IP2 in the aforementioned embodiments. For example, the interconnect structure MS3 includes a dielectric structure 307 and electrically connected conductive lines M1, conductive vias V1, M2, V2, and M3 embedded in the dielectric structure 307; the bonding structure BS3 may include a bonding dielectric structure 308 and a bonding pad structure 309 embedded in the bonding dielectric structure 308; the bonding structure BS4 may include a bonding dielectric structure 408 and a bonding pad structure 409 embedded in the bonding dielectric structure 408; the bonding pad structure 309 extends through the bonding dielectric structure 308 to be electrically connected to the conductive layer of the interconnect structure MS3 (e.g., conductive line M1), and the bonding pad structure 409 extends through the bonding dielectric structure 408 to be electrically connected to the conductive layer of the interconnect structure MS3 (e.g., conductive line M3). In some embodiments, the sub-interface IP3 does not include a semiconductor substrate and substrate vias, and the bonding pad structures BS1 and BS3 are in direct contact with the interconnect structure MS3, but this disclosure is not limited thereto.

[0053] In this embodiment, sub-interchange boards IP1 and IP3 (e.g., by hybrid bonding) are bonded together by bonding structures BS1 and BS4, and sub-interchange boards IP2 and IP3 (e.g., by hybrid bonding) are bonded together by bonding structures BS2 and BS3. For example, bonding pad structures 408 and 409 of bonding structure BS4 are bonded to bonding dielectric structure 108 and bonding pad structure 109 of bonding structure BS1, respectively; bonding dielectric structure 208 and bonding pad structure 209 of bonding structure BS2 are bonded to bonding dielectric structure 308 and bonding pad structure 309 of bonding structure BS3, respectively. Bonding pad structures 109 and 409 are electrically connected to each other to provide an electrical connection between sub-interchange boards IP1 and IP3, and bonding pad structures 209 and 309 are electrically connected to each other to provide an electrical connection between sub-interchange boards IP2 and IP3. It should be understood that... Figure 3B The bonding method between the various sub-adapter boards is only illustrative and is not limited thereto. In other embodiments, the bonding methods between the various sub-adapter boards may also be as follows: Figure 1B The bonding method shown utilizes conductive bumps.

[0054] Continue to refer to Figure 3BIn some embodiments, the conductive lines located on different layers in the interconnection structures of sub-interchange boards IP1-IP3 may have approximately the same linewidth / spacing and thickness, and the linewidth / spacing and thickness of the conductive lines in the interconnection structures of different sub-interchange boards IP1-IP3 may be the same or different from each other. In some embodiments where the linewidth / spacing and thickness of the conductive lines in sub-interchange board IP2 are greater than those in sub-interchange board IP1, the linewidth / spacing and thickness of the conductive lines in sub-interchange board IP3 located between sub-interchange boards IP1 and IP2 may, for example, be within the range of the linewidth / spacing and thickness of the corresponding conductive lines in sub-interchange board IP2 to the linewidth / spacing and thickness of the corresponding conductive lines in sub-interchange board IP1, and may, for example, be equal to the linewidth / spacing and thickness of the conductive lines in one of sub-interchange boards IP1 and IP2. For example, the line width / spacing of the conductive lines in the interconnect structures MS1 and MS3 of sub-interface boards IP1 and IP3 can be approximately the same, and the thickness T1 of the conductive lines in interconnect structure MS1 can be approximately equal to the thickness T3 of the conductive lines in interconnect structure MS3; however, the conductive lines of sub-interface board IP2 can have different line width / spacing and thickness than those of sub-interface boards IP1 and IP3. For instance, the line width / spacing of the conductive lines in the interconnect structure MS2 of sub-interface board IP2 can be smaller than the line width / spacing of the conductive lines in the interconnect structures MS1 and MS3 of sub-interface boards IP1 and IP3, the thickness T1' of the conductive lines in interconnect structure MS2 can be smaller than the thicknesses T1 and T3 of the conductive lines in interconnect structures MS1 and MS3, and the thickness of the conductive vias in interconnect structure MS2 can be smaller than the thickness of the conductive vias in MS1 ​​and MS3; correspondingly, the thickness of the dielectric material layer around the corresponding conductive lines / conductive vias in interconnect structure MS2 can be smaller than the thickness of the corresponding dielectric material layer in interconnect structures MS1 and MS3.

[0055] Reference Figure 3CIn some embodiments, in the interconnection structure of one or more sub-interchange boards of the adapter board, the conductive lines located on different layers may have different line widths / spacings and thicknesses. For example, in adapter board 500e, in the respective interconnection structures of sub-interchange boards IP1 and IP2, the conductive lines located on different layers may have approximately the same line width / spacing and thickness, and the line width / spacing of the conductive lines in the interconnection structure MS1 of sub-interchange board IP1 may be greater than the line width / spacing of the conductive lines in the interconnection structure MS2 of sub-interchange board IP2, and the thickness T1 of the conductive lines in interconnection structure MS1 may be greater than the thickness T1' of the conductive lines in interconnection structure MS2. In some embodiments, the conductive lines located on different layers in the interconnection structure MS3 of sub-interchange board IP3 may have different line widths / spacings and / or thicknesses, and may be within the range of the corresponding line widths / spacings and / or thicknesses of both interconnection structures MS1 and MS2. For example, in the interconnect structure MS3, the line width / spacing of the conductive line M1 near the sub-interchange board IP2 is less than that of the conductive line M3 near the sub-interchange board IP1. The thickness T32 of the conductive line M1 can be less than the thickness M31 of the conductive line M3. The line width / spacing and thickness of the conductive line M2 can be the same as or different from the line width / spacing and thickness of the conductive lines M1 or M3, for example, it can be between the line width / spacing and thickness values ​​of the two.

[0056] In some embodiments, the line width / spacing of the conductive line M3 in the interconnection structure MS3 of the sub-interchange board IP3, which is closer to the sub-interchange board IP1, can be approximately the same as the line width / spacing of the conductive line in the interconnection structure MS1 of the sub-interchange board IP1, and the thickness T31 of the conductive line M3 can be approximately equal to the thickness T1 of the conductive lines BM1-BM3 in the interconnection structure MS1; the line width / spacing of the conductive line M1 in the interconnection structure MS3 of the sub-interchange board IP3, which is closer to the sub-interchange board IP2, can be approximately the same as the line width / spacing of the conductive line in the interconnection structure MS2 of the sub-interchange board IP2, and the thickness T32 of the conductive line M1 can be approximately equal to the thickness T1' of the conductive lines TM1-TM3 in the interconnection structure MS2, and the thickness T1' can be less than the thickness T1.

[0057] In the above embodiments, the adapter boards 500a-500e include multiple stacked sub-adapter boards. Different sub-adapter boards may include conductive lines with the same or different linewidths / spacings and / or dielectric material layers of the same or different thicknesses, depending on product requirements, thereby meeting the connection requirements between different devices. In some embodiments, some of the multiple sub-adapter boards can provide the function of a conventional adapter board in a conventional CoWoS structure, while others can provide the function of a packaging substrate in a conventional CoWoS structure. For example, the top sub-adapter board IP1 can perform the function of a conventional adapter board, while the bottom sub-adapter board IP2 can perform the function of a packaging substrate. Other sub-adapter boards located between the top and bottom sub-adapter boards (e.g., sub-adapter board IP3) can perform the function of at least one of a conventional adapter board and a packaging substrate. In some embodiments, this disclosure forms an adapter board with a multi-layer interconnect structure by bonding multiple sub-adapter boards together, rather than forming an interconnect structure with more conductive layers in a single adapter board. This allows the adapter board to include more interconnect layers, and the number of sub-adapter boards can be adjusted according to product requirements, thereby meeting the needs of different quantities and types of wiring. Specifically, in a traditional single adapter board, due to stress and process limitations, it is difficult to achieve multi-layer stacking of conductive layers in a single adapter board. For example, when the number of conductive lines reaches a certain number (e.g., greater than 3 or 4), problems such as chip peeling may occur. Therefore, the interconnect structure in a traditional adapter board cannot achieve more conductive layer stacking, making it difficult to meet various wiring requirements, thus requiring the use of a packaging substrate to provide the necessary wiring. Compared to traditional adapter boards, the adapter board of this disclosure stacks multiple sub-adapter boards, and the number of stackable sub-adapter boards is unlimited, thereby achieving more conductive layer stacking, meeting the interconnection requirements of various devices, and replacing traditional packaging substrates.

[0058] Reference Figure 3DIn other embodiments, the adapter board 500f may include only one sub-adapter board IP1', and its interconnect structure MS1 includes multiple conductive layers with different line widths / spacings. For example, the adapter board 500f includes a substrate 100, a substrate via 102, an interconnect structure MS1 located on the substrate 100, conductive pads 211 and conductive connectors 220 located on the side of the interconnect structure MS1 away from the substrate 100, and conductive pads 111 and conductive connectors 120 located on the side of the substrate 100 away from the interconnect structure MS1. In some embodiments, the interconnect structure MS1 includes conductive lines BM1, conductive vias BV1, conductive lines BM2, conductive vias BV2, conductive lines BM3, conductive vias BV3, and conductive lines BM4 embedded in the dielectric structure 107. In some embodiments, conductive lines BM1 and BM2 may have approximately the same linewidth / spacing and thickness, and conductive lines BM3 and BM4 may have approximately the same linewidth / spacing and thickness, but the linewidth / spacing and thickness of conductive lines BM3 and BM4 may differ from those of conductive lines BM1 and BM2. In some embodiments, the linewidth / spacing of conductive lines BM1 and BM2 on the side of interconnect structure MS1 near the substrate 100 and conductive connector 120 is greater than the linewidth / spacing of conductive lines BM3 and BM4 on the side of interconnect structure MS2 near the conductive connector 220, and the thickness T1 of conductive lines BM1 and BM2 is, for example, greater than the thickness T1' of conductive lines BM3 and BM4. Conductive via BV1 connects adjacent conductive lines BM1 and BM2, conductive via BV2 connects adjacent conductive lines BM2 and BM3, and conductive via BV3 connects adjacent conductive lines BM3 and BM4. The thickness of conductive via BV1 can be greater than the thickness of conductive via BV3, and the thickness of conductive via BV2 can be between the thicknesses of conductive vias BV1 and BV3, or equal to the thickness of either conductive via BV1 or BV3. In some embodiments, conductive lines BM1 and BM2 with the same linewidth / spacing and / or thickness, and conductive via BV1 between them, can be referred to as a first interconnect structure. Conductive lines BM3 and BM4 with the same linewidth / spacing and / or thickness, and conductive via BV3 between them, can be referred to as a second interconnect structure. Conductive via BV2 is located between the first and second interconnect structures and is electrically connected to and directly contacts adjacent conductive lines BM2 and BM3 in both structures. The conductive lines / conductive vias in the first and second interconnect structures are located in the same dielectric structure 107. In this embodiment, the interconnect structure MS1 with two types of linewidth / spacing and thickness is used as an example for illustration, but this disclosure is not limited thereto. In other embodiments, the interconnect structure MS1 may include more types of line width / spacing and thickness, and may be adjusted according to product requirements.

[0059] In this embodiment, the second interconnect structure near the conductive connector 220 can, for example, function as a conventional adapter board, while the first interconnect structure near the conductive connector substrate 100, which has a larger linewidth and thickness, can, for example, function as a packaging substrate.

[0060] Figures 4A to 4M A schematic cross-sectional view is shown illustrating a method of forming an adapter plate according to some embodiments of the present disclosure.

[0061] Reference Figure 4A The present disclosure provides a substrate 100, which in some embodiments is a semiconductor substrate, such as a silicon substrate, but is not limited thereto, and the substrate 100 may also include other suitable semiconductor materials. For example, the substrate 100 is a semiconductor wafer and has a plurality of device regions and dicing regions located between the plurality of device regions. Figures 4A to 4M The process flow is shown in only one device area of ​​a semiconductor wafer.

[0062] Reference Figure 4B A patterning process is performed on substrate 100 to form one or more trenches TH in substrate 100. For example, a patterned mask layer (e.g., a patterned photoresist layer formed by photolithography) is formed on substrate 100, and then an etching process is performed on substrate 100 using the patterned mask layer as an etching mask to remove some portions of substrate 100 exposed by the patterned mask layer to form trenches TH. The trenches TH are formed to extend from the main surface (e.g., the top surface shown in the figure) of a first side (e.g., the front side) of substrate 100 toward a second side (e.g., the back side) of substrate 100 into substrate 100. In some embodiments, the trenches TH do not penetrate substrate 100, that is, the depth of trenches TH is less than the thickness of substrate 100 in a direction perpendicular to the main surface of substrate 100.

[0063] Reference Figure 4C An insulating layer 101 is formed on a substrate 100 to cover the main surface of the substrate 100 and fill the trench TH to line the surface of the trench TH. The insulating layer 101 may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed by a suitable deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, the thickness of the portion of the insulating layer 101 located outside the trench TH and covering the main surface of the substrate 100 (e.g., a first portion) may be the same as or different from the thickness of the portion of the insulating layer 101 located in the trench TH (e.g., a second portion), and the thickness of the first portion of the insulating layer 101 may, for example, be greater than the thickness of its second portion.

[0064] Reference Figure 4D A conductive material layer 102' is formed on an insulating layer 101 above a substrate 100. In some embodiments, the conductive material layer 102' includes a seed layer 102a and a conductive layer 102b. The seed layer 102a may be a metal seed layer, such as a copper seed layer, and may include, for example, titanium / copper; the conductive layer 102b may be a metallic material, such as copper. In some embodiments, the seed layer 102a may be formed by a physical vapor deposition (e.g., sputtering) process, followed by the formation of the conductive layer 102b on the seed layer 102a by a plating process such as electroplating. In some embodiments, the conductive material layer 102' may also include a barrier layer (not shown), for example, a barrier layer may be deposited before the formation of the seed layer 102a, and the barrier layer is located between the seed layer 102a and the insulating layer 101. The material of the barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, the like, or a combination thereof.

[0065] Reference Figures 4D to 4E A portion of the conductive material layer 102' located outside the trench TH and above the portion of the main surface of the covering substrate 100 of the insulating layer 101 is removed to form a substrate through-substrate via (TSV) 102 filling the trench TH. In some embodiments, the portion of the conductive material layer 102' can be removed by performing a planarization process (e.g., chemical mechanical polishing, CMP) on the conductive material layer 102', and the planarization process can be performed until the insulating layer 101 is exposed, i.e., the insulating layer 101 can be used as a stop layer for the planarization process. It should be noted that, for the sake of brevity, Figure 4E While the seed layer and conductive layer of the substrate via 102 are not specifically shown in subsequent figures, it should be understood that the substrate via 102 includes a conductive layer and a seed layer located between the conductive layer and the insulating layer 101.

[0066] Reference Figure 4E The substrate via 102 fills the trench TH of the substrate 100, and a portion of the insulating layer 101 is sandwiched between the substrate via 102 and the substrate 100, such that the substrate via 102 and the substrate 100 are physically and electrically isolated. In some embodiments, the surface of the substrate via 102 (e.g., the top surface shown in the figure) protrudes from the main surface of the substrate 100 in a direction perpendicular to the main surface of the substrate 100 and may be substantially flush with the surface of the portion of the insulating layer 101 located on the main surface of the substrate 100 (e.g., the topmost surface shown in the figure).

[0067] Reference Figure 4FAn interconnect structure MS1 is formed above a substrate 100. The interconnect structure MS1 includes one or more dielectric material layers and one or more conductive layers embedded within the dielectric material layers, wherein the conductive layers are electrically connected to a substrate via 102. The dielectric material layers may include, for example, alternately stacked etch stop layers and dielectric layers, and the conductive layers may include one or more conductive lines and conductive vias, with conductive lines located on different layers electrically connected to each other through conductive vias. For example, the interconnect structure MS1 includes multiple dielectric material layers 1051, 1061, 1052, 1062, and 1053, and conductive lines BM1, conductive vias BV1, conductive lines BM2, conductive vias BV2, and conductive lines BM3 embedded within the multiple dielectric material layers. Conductive lines BM1, BM2, and BM3 are formed in dielectric material layers 1051, 1052, and 1053, respectively, and conductive vias BV1 and BV2 are formed in dielectric material layers 1061 and 1062, respectively. The plurality of dielectric material layers may each be a single layer or a multilayer structure, and may include suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. Conductive lines and conductive vias may include metallic materials, such as copper, tungsten, aluminum, their alloys, the like, or combinations thereof, but this disclosure is not limited thereto.

[0068] In some embodiments, dielectric material layers 1051, 1052, and 1053 are each a two-layer structure and may each include an etch stop layer 105a and a dielectric layer 105b. Dielectric material layers 1061 and 1062 may each be a four-layer structure and may each include four alternately stacked etch stop layers and dielectric layers, for example, including an etch stop layer 106a1, a dielectric layer 106b1, an etch stop layer 106a2, and a dielectric layer 106b2. The aforementioned etch stop layers and dielectric layers comprise different materials and have an etch selectivity ratio in the etching process used to form the conductive layer openings. In some examples, the etch stop layer comprises silicon nitride, and the dielectric layer comprises silicon oxide, but this disclosure is not limited thereto.

[0069] The aforementioned dielectric material layer can be formed by deposition processes such as CVD, and multiple conductive lines and conductive vias can be formed in the corresponding dielectric material layer by an inlay process. The inlay process may include single-damascene, dual-damascene, or a combination thereof.

[0070] Although the figures show clear interfaces between the conductive lines and vias, this disclosure is not limited thereto. In some embodiments, such as those formed by a dual damascene process, some adjacent conductive vias and conductive lines in the interconnect structure may be formed simultaneously, and there may be no interface between them. In some embodiments, a conductive via may include one or more sub-vias. Taking conductive via BV1 as an example, in some embodiments, forming conductive via BV1 includes forming a sub-via 1a in an etch stop layer 106a1 and a dielectric layer 106b1, and forming a sub-via 1b on the sub-via 1a in an etch stop layer 106a2 and a dielectric layer 106b2. The sub-vias 1a and 1b are electrically connected to each other and may have the same or different dimensions (e.g., height, width, etc.). Sub-vias 1a and 1b may be formed simultaneously by a dual damascene process and there may be no interface between them, or they may be formed separately by a single damascene process and there may be an interface between them. Similarly, the sub-vias 2a and 2b included in the conductive via BV2 can be formed simultaneously or separately. It should be understood that the number of dielectric material layers, conductive lines, and conductive vias shown in the figures are for illustrative purposes only, and this disclosure is not limited thereto.

[0071] Reference Figure 4G A bonding structure BS1 is formed on the interconnect structure MS1. The bonding structure BS1 includes a bonding dielectric structure 108 and a bonding pad structure 109. The bonding pad structure 109 is embedded in the bonding dielectric structure 108 and surrounded by the bonding dielectric structure 108 in a direction parallel to the main surface of the substrate 100. The bonding dielectric structure 108 may be a single-layer or multi-layer structure and may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. The bonding pad structure 109 includes conductive materials, such as metallic materials including copper, aluminum, tungsten, gold, nickel, the like, or combinations thereof. The bonding dielectric structure 108 may be formed by a deposition process such as CVD, and the bonding pad structure 109 may be formed in the bonding dielectric structure 108 by a damascene process (e.g., single damascene or double damascene).

[0072] For example, the bonding dielectric structure 108 includes three layers of dielectric material. After forming the interconnect structure MS1, an etch stop layer 108a, a dielectric layer 108b, and a bonding layer 108c are sequentially formed on the interconnect structure MS1 to constitute the bonding dielectric structure 108. The etch stop layer 108a, dielectric layer 108b, and bonding layer 108c can be formed from different dielectric materials. For example, the etch stop layer 108a includes silicon oxide, the dielectric layer 108b includes silicon nitride, and the bonding layer 108c includes a dielectric material different from silicon oxide and silicon nitride, and has good bonding interface conditions to facilitate subsequent bonding processes. A bonding pad structure 109 is formed to extend through the bonding dielectric structure 108 and electrically connect to the topmost conductive feature of the interconnect structure MS1, such as a conductive line BM3. In some embodiments, the bonding pad structure 109 includes a via portion 109a and a pad portion 109b located on the via portion 109b. The via portion 109a may be formed in a dielectric layer 108b and an etch stop layer 108a, while the pad portion 109b may be formed in a dielectric layer 108b and a bonding layer 108c. In some embodiments, the surface of the bonding pad structure 109 on the side away from the substrate 100 (i.e., the top surface shown in the figure) and the surface of the bonding dielectric structure 108 on the side away from the substrate 100 (i.e., the top surface shown in the figure) are substantially coplanar and flush with each other, such that the bonding structure BS1 has a substantially flat surface on the side away from the substrate 100 to facilitate subsequent bonding.

[0073] Thus, a sub-semiconductor structure IS1' is formed, which includes a substrate 100, an insulating layer 101, a substrate via 102, an interconnect structure MS1, and a bonding structure BS1. In some embodiments, the sub-semiconductor structure IS1' is a wafer structure and may be referred to as a sub-interface structure.

[0074] Reference Figure 4H A substrate 200 is provided, and the material of the substrate 200 may be the same as or different from that of the substrate 100. For example, the substrate 200 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 200 is a semiconductor wafer and may include multiple device regions and dicing regions located between the device regions. The figure only shows the process flow in one device region of the semiconductor wafer.

[0075] Next, interconnect structure MS2 and bonding structure BS2 are formed on substrate 200. The materials and formation processes of interconnect structure MS2 and bonding structure BS2 are the same as those of reference. Figure 4F and Figure 4GThe materials and forming processes of the interconnect structure MS1 and the bonding structure BS1 are similar and will not be described again here. The characteristics (e.g., number of layers, size, etc.) of the dielectric material layer, conductive lines, and conductive vias in the interconnect structure MS2 are similar to those of the interconnect structure MS1, and may be the same or different. The characteristics (e.g., number of layers, size, etc.) of the dielectric structure and bonding pads in the bonding structure BS2 are similar to those of the interconnect structure MS1, and may be the same or different.

[0076] Thus, a sub-semiconductor structure IS2' is formed, which includes a substrate 200 and an interconnect structure MS2 and a bonding structure BS2 formed on the substrate 200. In some embodiments, the sub-semiconductor structure IS2' is a wafer structure and may be referred to as a sub-interface structure. In some embodiments, the sub-semiconductor structure IS2' is similar in structure to the sub-semiconductor structure IS1', except that no substrate vias are formed in the substrate 200 of the sub-semiconductor structure IS2', and correspondingly, no insulating layer is formed between the substrate vias and the substrate.

[0077] Reference Figure 4I ,Will Figure 4G The sub-semiconductor structure IS1' and Figure 4H The sub-semiconductor structures IS2' are joined together, for example, by... Figure 4H The sub-semiconductor structure IS2' is flipped so that the bonding structure BS2 faces and aligns with the bonding structure BS1 of the sub-semiconductor structure IS1'; then a bonding process is performed to bond the bonding structure BS2 to the bonding structure BS1, thereby bonding the sub-semiconductor structure IS2' to the sub-semiconductor structure IS1'. In some embodiments, the bonding process includes a hybrid bonding process, and may include metal-to-metal bonding and dielectric-to-dielectric bonding. For example, bonding pad structure 109 (e.g., its pad portion 109b) and bonding pad structure 209 (e.g., its pad portion 209b) are bonded together by metal-to-metal bonding and have a metal-to-metal bonding interface between them; bonding dielectric structure 108 (e.g., its bonding layer 108c) and bonding dielectric structure 208 (e.g., its bonding layer 208c) are bonded together by dielectric-to-dielectric bonding and have a dielectric-to-dielectric bonding interface between them. In some embodiments, the structure in which the sub-semiconductor structures IS2' and IS1' are bonded together is called a wafer bonding structure.

[0078] Reference Figure 4I and Figure 4JThe substrate 200 of the sub-semiconductor structure IS2' is removed to expose the side of the interconnect structure MS2 away from the bonding structure BS2, for example, exposing the surface of the conductive line TM1 away from the bonding structure BS2 and the sub-semiconductor structure IS1'. In some embodiments, the substrate 200 may be removed by at least one of a planarization process such as CMP and an etching process.

[0079] Reference Figure 4K Next, a passivation layer 210 is formed on the side of the interconnect structure MS2 away from the junction structure BS2 and the sub-semiconductor structure IS1' using a deposition process such as CVD. The passivation layer 210 is then patterned to form at least one via exposing a portion of the surface of the conductive line TM1. A conductive pad 211 is formed on the passivation layer 210 and filled into the via to electrically connect with the conductive line TM1. The conductive pad 211 may include a metal material such as aluminum. A passivation layer 212 is formed on the passivation layer 210 and the conductive pad 211 using a deposition process such as CVD, and the passivation layer 212 is patterned to form openings in the passivation layer 212 that expose a portion of the surface of the conductive pad 211. The materials of the passivation layer 210 and the passivation layer 212 may be selected from silicon oxide, silicon nitride, silicon oxynitride, etc., respectively. The passivation layer 210 may include inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, while the passivation layer 212 may include polymer materials such as polyimide (PI). However, this disclosure is not limited thereto. After forming an opening in the passivation layer 212, a conductive connector 220 is formed on the passivation layer 212. The conductive connector 220 is filled into the opening in the passivation layer 212 to electrically connect to the conductive pad 212. In some embodiments, the conductive connector 220 may be or include a conductive bump, such as a solder bump or solder ball, and may be formed by a ball-planting process. In some embodiments, prior to forming the conductive connector 220 through the ball-mounting process, an under-bump metallurgy (UBM) layer is formed on the passivation layer 212. The UBM layer fills the openings in the passivation layer 212 to electrically connect to the conductive pad 212, and the conductive connector 220 is formed on the UBM layer. The type and size of the conductive connector 220 can be adjusted according to product requirements. For example, the conductive connector 220 can be a microbump, a C4 bump, or other types of conductive bumps, but this disclosure does not limit the type and size of the conductive connector 220.

[0080] Reference Figures 4K to 4LAfter forming the conductive interconnect 220 on the sub-semiconductor structure IS2', a portion of the substrate 100 and a portion of the insulating layer 101 of the sub-semiconductor structure IS1' are removed to expose the surface of the substrate via 102 away from the interconnect structure MS1. In some embodiments, after forming the conductive interconnect 220, the substrate can be... Figure 4K The structure shown is flipped and attached to a carrier (not shown), for example, via an adhesive layer, such as a glass carrier, ceramic carrier, etc., which can provide structural support for the semiconductor structure in subsequent processes. Then, for example, a removal process is performed on the side of the substrate 100 away from the interconnect structure MS1 (i.e., the back side of the substrate 100) to remove portions of the substrate 100 and insulating layer 101 located on the side of the substrate via 102 away from the interconnect structure MS1, thereby exposing the surface of the substrate via 102 away from the interconnect structure MS1. This removal process may include planarization processes such as CMP and / or etching processes. In some embodiments, a portion of the seed layer of the substrate via 102 is also removed, exposing the conductive layer of the substrate via 102, and the remaining seed layer is located between the conductive layer and the insulating layer 101 in a direction parallel to the main surface of the substrate 100. However, this disclosure is not limited to this, and the seed layer of the substrate via 102 may not be removed.

[0081] Reference Figure 4M A conductive structure CS is formed on the side of substrate 100 away from interconnect structure MS1 (i.e., the back side). This structure can be referred to as the back-side conductive structure. The formation method of the back-side conductive structure is similar to that of interconnect structure MS1, and may also include one or more conductive layers embedded in a dielectric structure. The dielectric structure may include a single layer or multiple layers of dielectric material. For example, a dielectric material layer including an etch stop layer 55a and a dielectric layer 55b is formed on the back side of substrate 100; then, a conductive layer BL is formed in the dielectric material layer by an inlay process. The conductive layer BL extends through the dielectric material layer 55 to be electrically connected to the substrate via 102. The materials and formation methods of the dielectric material layer 55 and the conductive layer BL are similar to those of the dielectric material layer and conductive layer in interconnect structure MS1, and will not be described again here. It should be understood that the number of dielectric material layers and conductive layers in the back-side conductive structure of substrate 100 shown in the figure is only illustrative and is not limited thereto.

[0082] In some embodiments, prior to forming the back-side conductive structure, an insulating layer (not shown) is further formed on the back side of the substrate 100, such that the conductive layer BL is isolated from the substrate 100 through the insulating layer. The insulating layer may be located on the side of the substrate via 102 in a direction parallel to the main surface of the substrate 100 and between the substrate 100 and the conductive structure CS in a direction perpendicular to the main surface of the substrate 100.

[0083] Continue to refer to Figure 4M A passivation layer 110, conductive pad 111, passivation layer 112, and conductive connector 120 are formed on the conductive structure CS. The materials and forming methods of passivation layers 110, 112, conductive pad 111, and conductive connector 120 are similar to those of passivation layers 220, 212, conductive pad 211, and conductive connector 220, and will not be described again here. The conductive connector 120 can be selected with a suitable type of conductive bump according to product requirements, such as a C4 bump.

[0084] It should be understood that Figures 4L to 4M The process performed on the back side of substrate 100 can be completed with the back side of substrate 100 facing upwards, and after forming conductive connector 120, the carrier plate attached to one side of conductive connector 220 can be removed. In some embodiments, a singulation process is then performed on the wafer bonding structure to form one or more separate connectors 500a, including a first sub-connector IP1 and a second sub-connector IP2. Sub-connector IP1 is formed from the aforementioned sub-semiconductor structure IS1', and sub-connector IP2 is formed from the aforementioned sub-semiconductor structure IS2'. The singulation process may include, for example, a dicing process along a dicing region of the wafer bonding structure. The dicing process may include mechanical dicing, laser dicing, other types of dicing processes, or combinations thereof. In some embodiments, the sidewalls of sub-connector IP1 and sub-connector IP2 are aligned with each other in a direction perpendicular to the main surface of substrate 100. The sidewalls of sub-interchange board IP1 include the substrate 100, interconnect structure MS1, bonding structure BS1, conductive structure CS, and passivation layers 110 and 112. The sidewalls of sub-interchange board IP2 include the interconnect structure MS2, bonding structure BS2, and passivation layers 210 and 212. That is, the sidewalls of the above-mentioned components of sub-interchange boards IP1 and IP2 are aligned with each other in a direction perpendicular to the main surface of the substrate 100.

[0085] Figures 4A to 4M The method for forming an adapter board according to an embodiment of this disclosure will be described using adapter board 500a as an example. The method for forming adapter boards 500b to 500f can be similar to the method for forming adapter board 500a.

[0086] For example, Figure 1B The method of forming the adapter plate 500b shown is the same as Figures 4A-4M The formation methods shown are similar, the difference lies in... Figures 4H to 4IDuring the bonding process, the sub-semiconductor structure IS2' is bonded to the sub-semiconductor structure IS1' through the conductive connector BP. After the sub-semiconductor structures IS2' and IS1' are bonded to each other, a bottom filler layer UF is formed in the space between the sub-semiconductor structures IS2' and IS1' to surround and protect the conductive connector BP.

[0087] Figure 3A The method of forming the adapter board 500c shown is similar to that of forming the adapter board 500a. The difference is that when forming the interconnect structures MS1 and MS2, the thickness and line width / spacing of the corresponding dielectric material layer and conductive layer are adjusted according to product requirements, so that the thickness and line width / spacing of the dielectric material layer and conductive layer in the formed interconnect structure are different.

[0088] Figure 3B and Figure 3C The forming methods of the adapter plates 500d and 500e shown are similar to those of the adapter plate 500a. The difference lies in the additional sub-semiconductor structure formed, including providing an additional substrate, and sequentially forming a bonding structure BS3, an interconnect structure MS3, and a bonding structure BS4 on the additional substrate. The linewidth / spacing / thickness of each conductive layer in the interconnect structure MS3 can be adjusted according to product requirements. The additional sub-semiconductor structure is then bonded to... Figure 4G The sub-semiconductor structure IS1' shown is, for example, joined by the bonding structure BS4 of the additional sub-semiconductor structure via hybrid bonding (or via conductive connector BP) to the bonding structure BS1 of the sub-semiconductor structure IS1'; then (e.g., via a planarization process such as CMP) the additional substrate of the additional sub-semiconductor structure is removed to expose the bonding structure BS3; Figure 4H The sub-semiconductor structure IS2' shown is bonded to an additional sub-semiconductor structure, for example, by bonding the bonding structure BS2 of the sub-semiconductor structure IS2' to the bonding structure BS3 of the additional sub-semiconductor structure via hybrid bonding (or via conductive connector BP); subsequently, [further details are needed]. Figures 4I to 4M A similar process is used to complete the formation of the adapter boards 500d and 500e.

[0089] Figure 3D The method for forming the adapter plate 500f shown is similar to the aforementioned method for forming the adapter plate, except that the bonding process for the bonding structure and the sub-semiconductor structure is omitted. For example, in Figure 4F In the process steps, by adjusting the thickness and linewidth / spacing of different dielectric material layers and conductive layers, an interconnect structure MS1 comprising conductive layers with different linewidths / spacings and thicknesses is formed; passivation layers 210 and 212, conductive pads 211 electrically connected to the conductive lines in the interconnect structure MS1, and conductive connectors 220 are formed on the side of the interconnect structure MS1 away from the substrate 100; subsequently, the process is carried out... Figures 4K to 4M A similar process is used to form components such as conductive structure 55, passivation layers 110 and 112, conductive pads 111, and conductive connectors 120 on the back side of substrate 100.

[0090] Figure 5A A schematic top view of a packaging structure according to some embodiments of the present disclosure is shown. Figure 5B and Figure 5C A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown. Figure 5B and Figure 5C It is along Figure 5A The cross-sectional views of package structures 1000 and 1100 taken from line I-I'.

[0091] Reference Figure 5A and Figure 5B In some embodiments, the packaging structure 1000 includes an adapter board 500 and a plurality of dies disposed on the adapter board 500, such as dies 10a, 20a, 21a, 22a, 23a, 10b, 20b, 21b, 22b, and 23b. The adapter board 500 can be any one of the adapter boards 500a to 500f described in the above embodiments of this disclosure. It should be understood that, for the sake of brevity, Figure 5B The specific structure of the adapter plate 500 is not shown in the figure, and the specific structure of the adapter plate 500 can be referred to. Figures 1A to 3DAs described above with reference to the relevant diagrams. Multiple dies 10a-23b may comprise chips of the same or different types, and may each be a system-on-chip (SoC), a deep computing unit (DCU) chip, a graphics processing unit (GPU) chip, a central processing unit (CPU) chip, an application-specific integrated circuit (ASIC) chip, or a memory chip, such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a high bandwidth memory (HBM) chip, a similar chip, or any other suitable type of chip. In some examples, dies 10a and 10b are chips including logic circuits, such as SoC chips or DCU chips, and may be referred to as main dies, while dies 20a-23a and dies 20b-23b are memory chips, such as HBM chips, and may be referred to as memory dies. It should be understood that the number of main control dies and / or memory dies shown in the figures is merely illustrative and is not intended to be limiting. In other embodiments, more or fewer dies may be provided on the adapter board 500.

[0092] Multiple dies 10a-23b are electrically connected to an adapter plate 500 via conductive connectors 220, and the adapter plate 500 provides interconnection between the multiple dies 10a-23b. For example, the adapter plate 500 provides electrical connections and signal transmission between dies 10a and dies 20a-23a, between dies 10b and dies 20b-23b, and also provides electrical connections and signal transmission between dies 10a and dies 10b. In some embodiments, the adapter plate 500 (e.g., adapter plates 500a-500e) includes multiple sub-adapter plates bonded to each other, and different sub-adapter plates can provide interconnection between different dies.

[0093] For example, while referring to Figure 1A , 1B and Figure 3AIn some embodiments of the adapter board 500 that include sub-adapter board IP1 and sub-adapter board IP2, sub-adapter board IP2 provides interconnection between the main die and the memory die, while sub-adapter board IP1 provides interconnection between the main dies. For example, the electrical connection and signal transmission between die 10a and dies 20a-23a, and the electrical connection between die 10b and dies 20b-23b, can be achieved through sub-adapter board IP2 located near the dies in adapter boards 500a-500c; that is, die 10a is electrically connected to dies 20a-23a through sub-adapter board IP2; and die 10b is electrically connected to dies 20b-23b through sub-adapter board IP2. The electrical connection and signal transmission between the main dies 10a and 10b are achieved through sub-adapter board IP2 in adapter board 500 and sub-adapter board IP1 located on the side of sub-adapter board IP2 away from the dies. In some embodiments, interconnections between different dies may have different routing requirements. For example, the interconnection between die 10a and dies 20a-23a, and the interconnection between die 10b and dies 20b-23b, may require finer linewidth traces, while the interconnection between die 10a and die 10b may require long-distance high-frequency traces and may require thicker linewidth traces and / or thicker dielectric material layers between adjacent traces to avoid signal crosstalk. In this case, [the following can be used] Figure 3A The adapter board 500c shown is used to meet the wiring requirements between different dies. For example, the sub-adapter board IP2 in the adapter board 500c is located on one side close to multiple dies. Dies 10a and 20a-23a, as well as 10b and 20b-23b, are electrically connected to each other through the sub-adapter board IP2 in the adapter board 500c, which has a thinner conductive line width. Dies 10a and 10b are electrically connected to each other through the sub-adapter board IP2 in the adapter board 500c and the sub-adapter board IP1, which has a thicker conductive line width.

[0094] In other embodiments, the adapter board 500 (e.g., Figure 3B and Figure 3CThe adapter boards 500d and 500e shown have two or more sub-adapter boards. In these embodiments, at least one sub-adapter board (e.g., a top sub-adapter board) in the adapter board 500 that is closest to one of the plurality of dies is used for interconnection between the main die and the memory die (e.g., die 10a and dies 20a-23a and die 10b and dies 20b-23b), while at least one sub-adapter board (e.g., a bottom sub-adapter board) that is furthest from one of the plurality of dies is used for interconnection between the main die (e.g., die 10a and die 10b), and the sub-adapter board located between the top sub-adapter board and the bottom sub-adapter board can be used for at least one of interconnection between the main die and the memory die and interconnection between the main dies, such as at least one of interconnection between die 10a and die 20a-23a, interconnection between die 10b and die 20b-23b, and interconnection between die 10a and die 10b.

[0095] For example, when using Figure 3B In the adapter board 500d shown, the top sub-adapter board IP2 with a thinner linewidth is used for interconnection between main main die and memory die, such as between die 10a and dies 20a-23a and between die 10b and dies 20b-23b. The bottom sub-adapter board IP1 with a thicker linewidth is used for interconnection between main main dies, such as between die 10a and die 10b. The sub-adapter board IP3, located between sub-adapter boards IP1 and IP2 and with a thicker linewidth, can be used together with sub-adapter board IP1 for interconnection between main main dies, such as between die 10a and die 10b.

[0096] In other examples, when using Figure 3C In the adapter board 500e shown, the top sub-adapter board IP2, with a thinner linewidth, is used for interconnection between main body dies and memory dies, such as between dies 10a and dies 20a-23a and / or between dies 10b and dies 20b-23b. The bottom sub-adapter board IP1, with a thicker linewidth, is used for interconnection between main body dies, such as between dies 10a and dies 10b. The sub-adapter board IP3, located between sub-adapter boards IP1 and IP2 and having a different type of linewidth, can be used simultaneously for main body interconnection. Interconnections between main chips and memory chips, as well as interconnections between main chips, for example, conductive lines M1 and M2 with a thinner linewidth in sub-interchange board IP3 near sub-interchange board IP2 can be used for interconnection between main chip 10a and memory chips 20a-20a and main chip 10b and memory chips 20b-23b, while conductive line M3 with a thicker linewidth in sub-interchange board IP3 near sub-interchange board IP1 can be used for interconnection between main chips (e.g., between chips 10a and 10b).

[0097] In embodiments where the adapter board includes multiple sub-adapter boards, the multiple sub-adapter boards enable interconnections between more dies (e.g., more main dies and / or more memory dies), and more dies can be arranged on the adapter board to achieve the integration of more chips. Moreover, the number of sub-adapter boards in the adapter board of this disclosure embodiment can be adjusted based on the number of dies to be interconnected and routing requirements.

[0098] In embodiments where the adapter board 500 in the package structure 1000 includes multiple sub-adapter boards, the package structure 1000 may also be referred to as a chip on stacking wafer (CoSW) package.

[0099] In other embodiments, when the adapter board 500 adopts Figure 3D In the example of the adapter board 500f shown, conductive lines with different linewidths located in different layers of the adapter board 500f can be used for interconnection between different dies. For example, in the interconnection structure of the adapter board 500f, conductive lines BM4 and BM3 (or top conductive layers) with a thinner linewidth located near the conductive connector 220 can be used for interconnection between main dies and memory dies, such as between dies 10a and dies 20a-23a, and between dies 10b and dies 20b-23b; while conductive lines BM1 and BM2 (or bottom conductive layers) with a thicker linewidth located near the substrate 100 can be used for interconnection between main dies, such as between dies 10a and dies 10b.

[0100] Reference Figures 5A to 5CIn some embodiments, the package structure 1000, including the adapter board 500 and multiple dies, may be further connected to other components, such as a circuit board 600, to form a package structure 1100. The circuit board may be a printed circuit board (PCB), such as a high-density interconnect board. In the package structure 1000, interconnection between multiple dies can be achieved through the adapter boards 500a-500f in various embodiments of this disclosure, thus omitting the package board. The package structure 1000 can be directly mounted to the circuit board 600 without first bonding to the package board (ABF substrate) and then connecting to the circuit board 600 through the package board. In some embodiments, the adapter boards 500a-500f may also include conductive traces for providing electrical connections between the multiple dies and the circuit board 600. For example, the package structure 1000 can be electrically connected to the circuit board 600 via the conductive connector 120 of the adapter plates 500a-500f. The conductive connector 120 is located between the adapter plates 500 and the circuit board 600 to provide an electrical connection between them. The conductive connector 120 is directly connected to and in contact with the circuit board 600. Multiple dies are electrically connected to the circuit board 600 via the conductive connector 220, the adapter plates 500, and the conductive connector 120. In some embodiments, conductive bumps are not provided on the side of the circuit board 600 away from the conductive connector 120, but this disclosure is not limited thereto.

[0101] Although the adapter board of this disclosure can replace the packaging substrate of a conventional CoWoS structure, the adapter board of this disclosure can also be applied to a conventional CoWoS structure and can also be used in conjunction with the packaging substrate. For example, the packaging structure 1000 can be first bonded to the packaging substrate, and then connected to the circuit board 600 through the packaging substrate. That is to say, in the packaging structure of this disclosure, the packaging substrate can be used selectively. Since the adapter board of this disclosure can replace the packaging substrate, the use of the packaging substrate is not necessary, thereby freeing the production capacity of the packaging structure from the limitation of the packaging substrate production capacity.

[0102] In various embodiments of this disclosure, a novel adapter board is formed by joining multiple sub-adapter boards together. These sub-adapter boards can have conductive layers with the same or different linewidths and / or thicknesses, depending on product requirements. Alternatively, an interconnect structure with conductive layers of different linewidths can be formed within a single sub-adapter board. This allows the adapter board of this disclosure to simultaneously possess the functions of a conventional adapter board and a packaging substrate, satisfying interconnection between multiple dies and supporting long-distance high-frequency routing to meet various routing requirements and protocol interface transmission requirements. Furthermore, compared to a combination of a conventional adapter board and a packaging substrate, the sub-adapter boards in this disclosure, which can replace the packaging substrate (e.g., an ABF substrate), can have smaller linewidths and spacing than ABF substrates while meeting the requirements of long-distance high-frequency routing, and can reduce signal loss, thereby reducing the overall package size and improving the performance of the packaging mechanism. By replacing the combination of a conventional adapter board and a packaging substrate with the adapter board of this disclosure, the production capacity of the packaging structure is not limited by the production capacity of the packaging substrate, thereby improving the production capacity and yield of the packaging structure. On the other hand, there may be some problems with the connection between the traditional adapter board and the ABF substrate. However, the adapter board of this disclosure has each sub-adapter board joined together or uses a single adapter board, and the ABF substrate can be omitted. The sub-adapter boards can be connected to each other better, and the problems that may occur when the adapter board and the ABF substrate are joined can be avoided, thereby improving the device performance of the packaging structure.

[0103] The following points need to be explained:

[0104] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0105] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0106] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An adapter board, comprising: The first sub-interface board includes a substrate, a substrate via, a first interconnect structure, and a first bonding structure. The substrate has a first side and a second side opposite to each other. The first interconnect structure and the first bonding structure are disposed on the first side of the substrate. The substrate via extends through the substrate and is electrically connected to the first interconnect structure. The first bonding structure is disposed on the side of the first interconnect structure away from the substrate and is electrically connected to the first interconnect structure. The second sub-adapter board is disposed on the first sub-adapter board and electrically connected to the first sub-adapter board. The second sub-adapter board includes a second interconnection structure and a second bonding structure. The second bonding structure is bonded to the first bonding structure, and the second interconnection structure is located on the side of the second bonding structure away from the first sub-adapter board. A first conductive bump is disposed on the second side of the substrate of the first sub-interface plate and is electrically connected to the first interconnect structure through a through-hole in the substrate; as well as The second conductive bump is disposed on the side of the second interconnect structure of the second sub-interface plate away from the second bonding structure, and is electrically connected to the second interconnect structure. The adapter plate includes a single substrate, which is the substrate of the first sub-adapter plate. The second sub-adapter plate does not include a substrate or substrate vias. The second interconnect structure and the first interconnect structure are located on the same side of the single substrate and are directly connected to each other through the first bonding structure and the second bonding structure.

2. The adapter plate of claim 1, wherein the first bonding structure and the second bonding structure are configured to be bonded to each other by hybrid bonding or by conductive connectors.

3. The adapter board according to claim 2, wherein the first bonding structure and the second bonding structure each include a bonding dielectric structure and a bonding pad structure embedded in the bonding dielectric structure, and the bonding pad structures of the first bonding structure and the second bonding structure respectively pass through the bonding dielectric structure to electrically connect the conductive layers in the first interconnect structure and the second interconnect structure.

4. The adapter board of claim 3, wherein the first bonding structure and the second bonding structure are bonded to each other by hybrid bonding, and the bonding interface between the first bonding structure and the second bonding structure includes a dielectric-to-dielectric bonding interface between the bonding dielectric structures and a metal-to-metal bonding interface between the bonding pad structures.

5. The adapter plate according to claim 3, further comprising: A conductive connector is disposed between the first sub-adapter plate and the second sub-adapter plate, and the bonding pad structures of the first bonding structure and the second bonding structure are electrically connected to each other through the conductive connector.

6. The adapter plate according to claim 5 further includes: A bottom filler layer fills the space between the first bonding structure of the first sub-interface plate and the second bonding structure of the second sub-interface plate, and surrounds the conductive connector in a direction parallel to the main surface of the substrate.

7. The adapter board according to claim 1, wherein the second interconnect structure includes a second dielectric structure and a second conductive line and a second conductive via embedded in the second dielectric structure, the second conductive via being located between the second conductive lines and electrically connected to the second conductive lines in a direction perpendicular to the main surface of the substrate.

8. The adapter board according to claim 7, wherein the first interconnect structure of the first sub-adapter board includes a first dielectric structure and a first conductive line and a first conductive via embedded in the first dielectric structure, the first conductive via being located between and electrically connected to the first conductive line in the direction perpendicular to the main surface of the substrate, wherein the thickness of the first conductive via is greater than or at least equal to the thickness of the first conductive line, and the thickness of the first conductive via and the first conductive line refers to their thickness in the direction perpendicular to the main surface of the substrate.

9. The adapter plate according to claim 8, wherein the first conductive via includes a first sub-via and a second sub-via located on the first sub-via, the widths of the first sub-via and the second sub-via being the same or different from each other in a direction parallel to the main surface of the substrate.

10. The adapter plate according to claim 9, wherein the first sub-via and the second sub-via are respectively embedded in different dielectric material sub-layers.

11. The adapter plate of claim 8, wherein the first conductive via comprises a conductive via that extends continuously between opposite surfaces of the first conductive line in a direction perpendicular to the main surface of the substrate.

12. The adapter plate according to claim 8, wherein the first conductive line and the second conductive line have the same or different line widths.

13. The adapter board according to claim 12, wherein the line width of the second conductive line is smaller than the line width of the first conductive line.

14. The adapter plate of claim 12, wherein the thickness of the second conductive line in the direction perpendicular to the main surface of the substrate is less than the thickness of the first conductive line.

15. The adapter plate according to claim 12, further comprising a third sub-adapter plate disposed between the first sub-adapter plate and the second sub-adapter plate, and comprising a third interconnection structure, a third bonding structure and a fourth bonding structure, wherein the third bonding structure and the fourth bonding structure are disposed on opposite sides of the third interconnection structure in a direction perpendicular to the main surface of the substrate, and are respectively bonded to the second bonding structure of the second sub-adapter plate and the first bonding structure of the first sub-adapter plate.

16. The adapter board according to claim 15, wherein the third interconnect structure includes a third dielectric structure and a third conductive line, a fourth conductive line and a third conductive via embedded in the third dielectric structure, wherein the third conductive line and the fourth conductive line are connected to each other through the third conductive via.

17. The adapter board according to claim 16, wherein the line width of the third conductive line is the same as the line width of the fourth conductive line, and is equal to the line width of the first conductive line or equal to the line width of the second conductive line.

18. The adapter plate according to claim 16, wherein the line width of the third conductive line is different from the line width of the fourth conductive line.

19. The adapter board of claim 18, wherein the fourth conductive line is close to the first interconnect structure and the line width of the fourth conductive line is equal to the line width of the first conductive line, and the third conductive line is close to the second interconnect structure and the line width of the third conductive line is equal to the line width of the second conductive line.

20. An adapter board, comprising: The first sub-interface board includes a substrate, a substrate via, a first interconnect structure, and a first bonding structure. The first interconnect structure is disposed on the substrate and includes a first conductive line and a first conductive via. The first conductive via is located between the first conductive lines and electrically connected to the first conductive lines. The first bonding structure is located on the side of the first interconnect structure away from the substrate. The substrate via extends through the substrate and is electrically connected to the first conductive line of the first interconnect structure. The second sub-interface board is electrically connected to the first sub-interface board and includes a second interconnect structure and a second bonding structure. The second interconnect structure and the first interconnect structure are disposed on the same side of the substrate. The second interconnect structure is disposed on the side of the first interconnect structure away from the substrate and includes a second conductive line and a second conductive via. The second conductive via is located between the second conductive lines and is electrically connected to the second conductive lines. The second bonding structure is located on the side of the second interconnect structure closer to the first sub-interface board and is bonded to the first bonding structure. A first conductive bump is disposed on the side of the substrate away from the first interconnect structure and is electrically connected to a through-hole in the substrate; as well as The second conductive bump is disposed on the side of the second interconnect structure away from the first interconnect structure and is electrically connected to the second conductive line. The first conductive line and the second conductive line have different line widths. The adapter plate includes a single substrate, which is the substrate of the first sub-adapter plate. The second sub-adapter plate does not include a substrate or substrate vias, and the second interconnect structure and the first interconnect structure are directly connected to each other through the first bonding structure and the second bonding structure.

21. The adapter plate according to claim 20, wherein the line width of the first conductive line is greater than the line width of the second conductive line.

22. The adapter plate according to claim 20, wherein the thickness of the first conductive wire is greater than the thickness of the second conductive wire.

23. The adapter board according to any one of claims 1-22, wherein there is no semiconductor substrate between the second interconnect structure and the second conductive bump and between the second interconnect structure and the first interconnect structure.

24. The adapter plate according to any one of claims 1-22, further comprising a conductive pad and a passivation layer disposed between the second conductive bump and the second interconnect structure, wherein the conductive pad passes through the passivation layer to be electrically connected to and in direct contact with the conductive layer in the second interconnect structure.

25. A packaging structure, comprising: The adapter plate according to any one of claims 1-24; as well as Multiple dies are arranged side-by-side on the adapter plate and connected to the adapter plate via the second conductive bump. The second interconnection structure is disposed between the plurality of dies and the first interconnection structure, some of the plurality of dies are interconnected through the first interconnection structure, and others of the plurality of dies are interconnected through the second interconnection structure.

26. The packaging structure of claim 25, wherein the plurality of dies includes a first main control die, a first memory die, a second main control die, and a second memory die, the first interconnect structure providing an electrical connection between the first main control die and the second main control die, and the second interconnect structure providing an electrical connection between the first main control die and the first memory die and between the second main control die and the second memory die.

27. A packaging structure, comprising: The adapter plate according to any one of claims 15-19; as well as Multiple main control dies and multiple memory dies are arranged side-by-side on the adapter plate and connected to the adapter plate via the second conductive bump. The first sub-interchange board provides interconnection between at least some of the plurality of master master chips, the second sub-interchange board provides interconnection between at least one of the plurality of master master chips and the plurality of memory chips and a corresponding memory chip, and the third sub-interchange board provides at least one of interconnection between some of the plurality of master master chips and interconnection between one or more of the plurality of master master chips and the corresponding memory chip.

28. A method for forming an adapter plate, comprising: Provide a first substrate; A substrate through-hole is formed in the first substrate; A first interconnect structure is formed on a first side of the first substrate, and the first interconnect structure is electrically connected to a through-hole in the substrate; A first bonding structure is formed on the side of the first interconnect structure away from the first substrate. The first bonding structure is electrically connected to the first interconnect structure. The first substrate, the substrate via, the first interconnect structure, and the first bonding structure constitute at least a portion of the first sub-interface plate. Provide a second substrate; A second interconnect structure is formed on the second substrate, and a second bonding structure is formed on the side of the second interconnect structure away from the second substrate, the second bonding structure being electrically connected to the second interconnect structure; The second bonding structure on the second substrate is bonded to the first bonding structure on the first substrate; Remove the second substrate to expose the side of the second interconnect structure away from the second bonding structure, the second interconnect structure and the second bonding structure forming at least a portion of the second sub-interface plate; A first conductive bump is formed on the second side of the first substrate away from the first interconnect structure; and; A second conductive bump is formed on the side of the second interconnect structure away from the second bonding structure. The adapter plate formed therein includes a single substrate, which is the first substrate of the first sub-adapter plate. The second sub-adapter plate does not include a substrate or substrate vias. The second interconnect structure and the first interconnect structure are located on the same side of the single substrate and are directly connected to each other through the first bonding structure and the second bonding structure.

29. The method of forming an adapter plate according to claim 28, wherein joining the second joining structure to the first joining structure comprises: The second bonding structure is bonded to the first bonding structure using a hybrid bonding process; Alternatively, a conductive connector may be formed so that the second bonding structure is bonded to the first bonding structure via the conductive connector.

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