Variable gain phase current balanced multiphase switching regulator based on ramp compensated analog phase current signals

Abstract

A multiphase current mode hysteretic modulator uses slope compensated analog phase current signals and individual phase control signals for each phase to achieve phase current balancing among multiple power stages. In some embodiments, the slope compensated analog phase current signals for all phases are averaged and compared to the slope compensated analog phase current signals for each phase to generate a phase current balancing control signal for each phase. The phase current balancing control signal is combined with a voltage control loop error signal to generate a phase control signal for each phase, where a phase control signal is generated for multiple phases to control the phase current delivered by each power stage.

Description

Technical Field

[0001] The present invention relates to multiphase current-mode hysteresis modulators, and in particular, to circuits and methods for providing phase current balance in multiphase current-mode hysteresis modulators. Background Technology

[0002] Electronic systems containing integrated circuits typically use voltage regulators to convert the main bus voltage from the power supply system to one or more voltages required to drive the integrated circuits. For example, a 5-volt power supply to an electronic system might need to be reduced to 1.8 volts to drive the integrated circuits. Embedded systems, such as Internet of Things (IoT) devices, contain a processor (or microcontroller) and local memory coupled to the components, and execute embedded software to perform certain tasks. In practice, the processor power is provided by a voltage regulator that converts the input voltage of the power supply to a voltage value specified by the processor. In some cases, the microcontroller or processor used in these embedded systems implements mobile voltage positioning to allow the processor to control or select its own operating voltage (Vcc). The processor generates a multi-bit voltage identification code that informs the regulator of the instantaneous output voltage. In this way, the processor can dynamically adjust the processor power supply voltage (Vcc) based on processor activity to reduce processor power consumption. For example, the processor can adjust the processor power supply voltage to maintain a high processor clock speed at a given power consumption, or the processor can adjust the processor power supply voltage to reduce power consumption at a given clock frequency.

[0003] A switch-mode power supply, or switching regulator, also known as a DC-DC converter, is a voltage regulator typically used to convert an input supply voltage to the desired output voltage at a voltage level selected for an integrated circuit. In one example, a 12V or 5V supply voltage can be reduced to 1V to power an embedded processor. Switching regulators provide power through low-loss components such as capacitors, inductors, and transformers, as well as power switches that turn on and off to transfer energy from the input to the output, sometimes in discrete packets. Feedback control circuitry is used to regulate energy transfer to maintain a constant output voltage within the circuit's desired load limits.

[0004] The operation of a conventional switching regulator is well-known and can be summarized as follows. For a buck (or step-down) switching regulator, the regulator comprises a pair of power switches that turn on and off to regulate the output voltage to be equal to a reference voltage, where the output voltage is less than the input voltage. More specifically, the power switches alternately turn on and off to generate a switching output voltage at the switching output node (also called the switching node). The switching node is coupled to an LC filter circuit containing an output inductor and an output capacitor to generate an output voltage with a substantially constant amplitude. This output voltage can then be used to drive a load.

[0005] Switching regulators can employ various control methods. One type of switching regulator control scheme is current-mode control, in which the switching regulator adjusts the peak or valley current in the output inductor to deliver the necessary energy to the load to maintain the required output voltage. In current-mode control, the inductor or power switch current is sensed and compared with a current loop error signal to control the opening or closing of the high-voltage side power switch. In some cases, slope compensation is employed in the current control loop to improve operational stability.

[0006] Some switching regulators use pulse width modulation (PWM) to control the duty cycle of the power switch. That is, by adjusting the pulse width, the on-time of the power switch can be controlled at a given fixed or variable frequency. PWM-controlled switching regulators include a PWM controller or modulator to drive a power block containing the power switch, the power switch drive circuitry, and the LC filter circuitry.

[0007] In some cases, switching regulators are single-phase converters, where the PWM controller generates a single-phase PWM clock signal to drive a single-phase power block. In other cases, switching regulators are multi-phase converters, where the multi-phase PWM controller generates clock signals with different phase shifts to drive multi-phase power blocks, with each clock signal driving a corresponding power block unit. Multi-phase PWM controllers are required when voltage regulators must provide highly accurate regulated output voltage under a wide range of load conditions. Summary of the Invention

[0008] To achieve the above objectives, the present invention provides a multiphase current-mode hysteresis modulator for generating multiple pulse width modulation (PWM) signals to drive multiple power stages in multiple phases. Each power stage receives an input voltage and transmits a phase current to an output node through its respective inductor. An output capacitor and a load are connected to the output node. The multiple PWM signals are generated in response to a feedback voltage signal indicating a regulated output voltage at the output node. The current-mode hysteresis modulator includes: a voltage control loop coupled to receive a feedback voltage signal indicating a regulated output voltage and a target voltage, and generating a voltage control loop error signal indicating the difference between the feedback voltage signal and the target voltage; and a phase current balancing control loop coupled to receive a slope generated for the multiple phases. The compensated analog phase current signal, each slope-compensated analog phase current signal indicating the expected current level of the phase current delivered by the corresponding power stage, and includes a slope compensation signal. The phase current balance control loop determines the difference between the slope-compensated analog phase current signal and the average phase current signal for each phase to generate a phase current balance control signal for each phase. The phase current balance control signal for each phase is combined with the voltage control loop error signal to generate a phase control signal for each phase. The phase control signal for each phase is compared with the slope-compensated analog phase current signal for the corresponding phase to generate a duty cycle control signal, controlling the duty cycle of the PWM signal for the corresponding phase. Duty cycle control signals are generated for multiple phases to control the phase current delivered by multiple power stages.

[0009] Preferably, the voltage control loop includes: a first error amplifier that receives a feedback voltage signal indicating an regulated output voltage and a target voltage, the first error amplifier generating a voltage control loop signal at its output terminal indicating the difference between the feedback voltage signal and the target voltage; a plurality of modulation comparators, each modulation comparator associated with its respective phase and having a first input terminal receiving a combined signal of the voltage control loop signal and a phase current balance control signal for its respective phase and a second input terminal receiving a slope-compensated analog phase current signal for its respective phase, each modulation comparator generating a phase control signal for its corresponding phase, the phase control signal being a reset signal; and a plurality of latching circuits, each latching circuit associated with its respective phase and having a reset input terminal coupled to receive a reset signal from the modulation comparator for its respective phase, a setting input terminal coupled to receive a clock signal for its respective phase, and an output terminal that generates a PWM signal for the corresponding phase to drive the corresponding power level, the PWM signal having an on-duty period and an off-duty period defining the duty cycle of the PWM signal, wherein the setting signal initiates the on-duty period of the PWM signal, and the reset signal terminates the on-duty period of the PWM signal.

[0010] Preferably, the phase current balance control loop includes: multiple ramp signal generator circuits, each ramp signal generator circuit being associated with a corresponding phase and receiving a PWM signal of the corresponding phase, and each ramp signal generator circuit including a switched capacitor circuit for implementing charge scaling to generate a ramp-compensated analog phase current signal of the corresponding phase.

[0011] Preferably, the phase current balance control loop further includes: a signal averaging circuit that receives slope-compensated analog phase current signals of the plurality of phases and generates an average phase current signal indicating the average current value of the slope-compensated analog phase current signals of all phases; and a plurality of amplifier circuits, each amplifier circuit being associated with a corresponding phase and receiving the average phase current signal and the slope-compensated analog phase current signal of the corresponding phase, each amplifier circuit generating a phase current balance control signal for each phase indicating the difference between the slope-compensated analog phase current signal and the average phase current signal for each phase.

[0012] Preferably, the plurality of amplifier circuits comprises: a plurality of operational transconductance amplifiers, each operational transconductance amplifier having a non-inverting input terminal coupled to receive an average phase current signal and an inverting input terminal coupled to receive a slope-compensated analog phase current signal for the corresponding phase, each operational transconductance amplifier generating an output current signal indicating the difference between the slope-compensated analog phase current signal and the average phase current signal for each phase; and a plurality of current-to-voltage conversion circuits, each current-to-voltage conversion circuit being coupled to receive the output current signal from the corresponding operational transconductance amplifier for the corresponding phase and providing a voltage signal as a phase current balance control signal, wherein the phase current balance control signal is added to or subtracted from a voltage control loop signal to generate a combined signal for each phase.

[0013] Preferably, each of the plurality of current-to-voltage conversion circuits includes a parallel resistor-capacitor circuit.

[0014] Preferably, the modulator includes a peak current buck modulator, each of a plurality of ramp signal generators generating a ramp-compensated analog phase current signal having a rising ramp proportional to the input voltage during the on-time of the corresponding phase of the PWM signal, and a falling ramp proportional to the output voltage during the off-time of the PWM signal.

[0015] Preferably, the modulator comprises one of a peak current buck modulator, a peak current boost modulator, a valley current buck modulator, and a valley current boost modulator.

[0016] A method for controlling phase current in a multiphase voltage regulator, the method comprising: generating a plurality of pulse width modulation (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and transmitting a phase current to an output node through its respective inductor, an output capacitor and a load connected to the output node, wherein the plurality of PWM signals are generated in response to a feedback voltage signal indicating an regulated output voltage at the output node; generating a voltage control loop signal indicating a difference between the feedback voltage signal and a target voltage; and generating a plurality of slope-compensated analog phase current signals for the plurality of phases, each slope-compensated analog phase current... The signal indicates the expected current level of the phase current delivered by the corresponding power stage and includes a slope compensation signal; a phase current balance control signal is generated for each phase, indicating the difference between the slope compensation analog phase current signal and the average phase current signal for each phase; and the phase current balance control signal for each phase is combined with the voltage control loop signal, and the combined signal is compared with the slope compensation analog phase current signal for the corresponding phase to generate a phase control signal for the corresponding phase, which controls the duty cycle of the PWM signal for the corresponding phase, wherein phase control signals are generated for multiple phases to control the phase current delivered by each power stage.

[0017] Preferably, the voltage control loop signal that indicates the difference between the feedback voltage signal and the target voltage includes: generating the voltage control loop signal that indicates the difference between the feedback voltage signal and the target voltage using an error amplifier.

[0018] Preferably, generating the phase control signal includes: providing a plurality of modulation comparators to generate phase control signals for a plurality of phases; at each modulation comparator associated with a corresponding phase, coupling a combination signal of a voltage control loop signal and a phase current balance control signal of the corresponding phase to a first input terminal, and coupling a slope-compensated analog phase current signal of the corresponding phase to a second input terminal; and generating a phase control signal at the output of each modulation comparator as a reset signal for the corresponding phase.

[0019] Preferably, generating the plurality of slope-compensated analog phase current signals for the plurality of phases includes: generating slope-compensated analog phase current signals using a plurality of ramp signal generator circuits in response to the PWM signal of each phase, each ramp signal generator circuit including a switched capacitor circuit that performs charge scaling to generate the slope-compensated analog phase current signal for each phase.

[0020] Preferably, generating phase current balance control signals for multiple phases includes: generating an average phase current signal by averaging the slope-compensated analog phase current signals of all phases; and for each phase, generating a current signal indicating the difference between the slope-compensated analog phase current signal and the average phase current signal of each phase; and for each phase, converting the current signal into a voltage signal as the phase current balance control signal for the corresponding phase.

[0021] Preferably, the step of converting the current signal into a voltage signal as a phase current balance control signal for each phase includes: for each phase, using a parallel resistor-capacitor circuit to convert the current signal into a voltage signal as a phase current balance control signal for the corresponding phase.

[0022] Preferably, the multiphase voltage regulator implements peak current buck current mode control and uses multiple ramp signal generator circuits to generate ramp-compensated analog phase current signals, comprising: receiving a pulse width modulation signal having an on-time duration and an off-time duration at each ramp signal generator in each phase; generating a rising ramp of the ramp signal during the on-time duration of the pulse width modulation signal, the slope of which is proportional to the input voltage; generating a falling ramp of the ramp signal during the off-time duration of the pulse width modulation signal, the slope of which is proportional to the output voltage; and providing the rising ramp and falling ramp as ramp-compensated analog phase current signals for the corresponding phases.

[0023] Preferably, the multiphase voltage regulator implements peak current buck current mode control, peak current boost current mode control, valley current buck current mode control, and valley current boost current mode control.

[0024] In summary, compared with the prior art, the present invention provides a multiphase current-mode hysteresis modulator and a method for controlling phase current in a multiphase voltage regulator, which achieves phase current balance among multiple power stages by using a slope-compensated analog phase current signal and a separate phase control signal for each phase. Attached Figure Description

[0025] The following detailed description and accompanying drawings illustrate various embodiments of the present invention.

[0026] Figure 1 This is a schematic diagram of a voltage regulator that includes a multiphase current-mode hysteresis modulator in some examples.

[0027] Figure 2 This represents the operating signal in a current-mode hysteresis modulator in some examples.

[0028] Figure 3The diagram illustrates a voltage modulator in an embodiment of the present invention, which incorporates a multi-phase current-mode hysteresis modulator configured with a phase current balance control loop.

[0029] Figure 4 This diagram illustrates a multi-phase current-mode hysteresis modulator configured with a phase current balancing circuit in an embodiment of the present invention.

[0030] Figure 5 This is a simplified schematic diagram of one phase of a phase current balancing circuit in some embodiments.

[0031] Figure 6 Include Figure 6 (a) and 6(b) represent typical signal averaging circuits that can be introduced into a phase current balancing circuit in an embodiment of the invention.

[0032] Figure 7 In an embodiment of the present invention, a schematic diagram of a ramp signal generator is shown, wherein ramp compensation is incorporated into a peak current mode buck modulator, and the peak current mode buck modulator can be incorporated into a current mode control modulator.

[0033] Figure 8(a) and 8(b) The included signal waveforms demonstrate the operating characteristics of voltage regulators that incorporate four-phase current-mode hysteresis modulators in some examples. Detailed Implementation

[0034] The following will be combined with the appendix in the embodiments of the present invention. Figure 1 Figure 8 illustrates in detail the technical solutions, structural features, objectives, and effects achieved in the embodiments of the present invention.

[0035] According to embodiments of the present invention, a multi-phase current-mode hysteresis modulator achieves phase current balance among multiple power stages using slope-compensated analog phase current signals and individual phase control signals for each phase. In some embodiments, the slope-compensated analog phase current signals for all phases are averaged and compared with the slope-compensated analog phase current signals for each phase to generate a phase current balance control signal for each phase. The phase current balance control signal is combined with a voltage control loop error signal to generate a phase control signal for each phase, wherein phase control signals are generated for multiple phases to control the phase current delivered by each power stage.

[0036] With this configuration, the multiphase current-mode hysteresis modulator of the present invention provides a fast phase current balance control loop to maintain proper current balance between phases and keep the different phases of the power stage operating synchronously with each other during fast transient events of the load.

[0037] In some embodiments, a multiphase current-mode hysteresis modulator (also referred to herein as a multiphase current-mode controlled modulator) is applied in a switching regulator or voltage regulator to generate a regulated output voltage from an input voltage. The current-mode controlled modulator generates a set of pulse-width modulated signals, each with a given duty cycle and at a different phase. The current-mode controlled modulator can be applied in buck switching regulators, boost switching regulators, or buck-boost switching regulators. Furthermore, in embodiments of the invention, the multiphase current-mode controlled modulator can be applied in modulators that implement peak current-mode control or valley current-mode control.

[0038] In embodiments of the invention, a multiphase current-mode control modulator uses analog or synthesized phase current signals to implement a phase current balance control loop. The phase current balance control loop generates a separate phase control signal for each phase of the voltage regulator. In some embodiments, a ramp signal generator is used to generate analog or synthesized phase current signals, incorporating ramp compensation into each analog phase current signal. In one example, a current-mode hysteresis modulator implements peak current control, and the current-mode hysteresis modulator uses the phase current signal to terminate the on-time of the modulator's PWM signal. In other control topologies, the phase current signal can be used to initiate the on-time of the PWM signal.

[0039] Figure 1 This diagram illustrates a voltage regulator that includes a multiphase current-mode hysteresis modulator in some examples. (Reference) Figure 1 The voltage regulator 10 includes a multiphase current-mode hysteresis modulator 12 (“Modulator 12”) coupled to drive the multiphase power block 13. In this example, the voltage regulator 10 is implemented using a multiphase modulator to enable the voltage regulator to provide a regulated output voltage with high accuracy under a wide range of load conditions. In this example, the multiphase modulator 12 includes three phases, and the power block 13 includes three power stages 20-1 to 20-3, each having an associated output inductor L1 to L3 and an output capacitor C. OUT .

[0040] More specifically, voltage regulator 10 receives input voltage V at input node 21. IN And generate an regulated output voltage V at output node 28. OUT To supply load 29. The multiphase power block 13 comprises power stages 20-1 to 20-3 driven by their respective PWM signals PWM1 to PWM3. Each power stage 20 includes a pair of power switches connected in series, which are turned on and off by a corresponding PWM signal to regulate the output voltage V with reference to a target voltage. OUTThe power switches in each power stage 20 are alternately turned on and off to generate a switching output voltage at the switching output node, which serves as the output terminal of each power stage. The switching output node of each power stage 20 is coupled to its respective output inductors L1 to L3. Inductors L1 to L3 are coupled to the output capacitor C. OUT This forms an LC circuit to supply current to output node 28 while maintaining a substantially constant output voltage V. OUT Then, the output voltage V OUT It can be used to drive load 29.

[0041] The current-mode hysteresis modulator 12 receives the feedback voltage V. FB The feedback voltage V FB Indicates the regulated output voltage V on output ode 28 OUT In one example, the feedback voltage V FB It is the output voltage V OUT The step-down voltage. For example, a resistor divider containing resistors R11 and R12 coupled to the output voltage node 28 can be used to generate the feedback voltage V. FB The current-mode hysteresis modulator 12 also receives a target voltage V indicating the voltage value required to regulate the output voltage. TARG In some examples, the target voltage can be indicated by a voltage identification code representing the desired regulator output voltage. For example, when applied to mobile voltage positioning, modulator 12 can receive a voltage identification (VID) code that tells the modulator what output voltage it should provide. Each VID code is associated with a voltage value. The decoder decodes the code to generate the target voltage.

[0042] Modulator 12 implements a voltage regulation loop or voltage control loop, wherein the feedback voltage V is converted at error amplifier 14. FB With target voltage V TARG A comparison is made to generate the voltage control loop error signal V. COMP Error signal V COMP This can be a voltage signal or a current signal. In this example, error amplifier 14 generates an output current, which is converted into a voltage signal by loop filter 15. Therefore, in this example, the error signal V COMP It is a voltage signal. Error signal V COMPA set of modulation comparators 16-1 to 16-3 are provided with inverting input terminals, each corresponding to one phase of the multiphase voltage regulator. In this example, each modulation comparator 16 receives a sensed current signal ILn from the respective power stage 20 at its non-inverting input terminal. Specifically, a voltage signal V(ILn) indicates the inductor current ILn at the respective power stage 20-n. For example, the first modulation comparator 16-1 receives a voltage signal V(IL1) at its non-inverting input terminal, where the voltage signal V(IL1) indicates the current flowing through the output inductor L1. In some conventional voltage regulators, the voltage signal V(IL1) is generated by sensing the inductor current of the output inductor for each phase.

[0043] Each of the modulation comparators 16-1 to 16-3 generates a reset voltage signal V. RST This is coupled to the reset input terminal of the corresponding latch circuits 18-1 to 18-3. In this embodiment, latch circuits 18-1 to 18-3 are triggers. Each setting input terminal of latch circuits 18-1 to 18-3 receives a setting voltage signal V. SET The voltage signal V is set. SET These are corresponding clock signals CLK1-CLK3 with corresponding phases. Latch circuits 18-1 to 18-3 generate multi-phase PWM signals PWM1 to PWM3 to drive the various power levels 20-1 to 20-3 in the multi-phase power block 13. Each power level 20-1 to 20-3 is driven in stages.

[0044] In one example, voltage-controlled oscillator (VCO) 22 receives the voltage-controlled loop error signal V. COMP The clock signal CLK (node ​​24) is generated in response to changes in the error signal. In the multiphase modulator 12, the clock signal CLK is provided to the clock sequencer 26 to separate it into multiple clock signals CLK1 to CLK3 with different phases. In some examples, the VCO 22 operates to provide variable switching frequency control in the modulator 12, enabling the voltage regulator to be more responsive to load changes.

[0045] With this configuration, the current-mode hysteresis modulator 12 uses the feedback voltage V FB Implement a voltage control loop, and implement a current control loop using the sensed current signal ILn. (Reference) Figure 2 This indicates the operation of modulator 12 in generating PWM signals PWM1-3. Figure 2 This represents the operating signal in a current-mode hysteresis modulator with a single-phase clock signal, as seen in some examples. Specifically, Figure 2 This describes the operation of a current-mode hysteresis modulator that implements peak current control. (Reference) Figure 2 The clock signal CLK (curve 32) responds to the error signal V.COMP (Curve 34) is generated to determine the frequency of the PWM signal. That is, the clock signal CLK is used as the error signal V. COMP The frequency determined by the function is triggered or asserted. When the clock signal CLK is asserted, the PWM signal begins a new duty cycle. That is, as the set voltage signal V... SET The clock signal CLK triggers the PWM signal for its on-time duration. The induced current IL is measured and compared with the error signal V. COMP Comparisons are made. For example, the voltage signal V(IL) indicating the sensing current IL (curve 36) is used to compare it with the error voltage signal V. COMP A comparison is made. When the sensed current IL (or the voltage V(IL) indicating it) reaches the error signal V... COMP When the reset voltage signal V is triggered. RST This terminates the on-time of the PWM signal. In this way, the duty cycle of the PWM signal is controlled by the clock signal CLK and the sensed current signal. Specifically, the clock signal CLK determines the PWM signal frequency, and the sensed current signal determines the PWM signal duty cycle, which is the percentage of the total switching cycle that the power stage switch is on. By controlling the duty cycle of the power stage switch, the switching voltage regulator can adjust the output voltage.

[0046] In this specification, the reference to "on-duration" of a PWM signal refers to the logic state of the PWM signal associated with the charging phase of the output inductor, where the inductor current increases or rises (i.e., the inductor is charged by the power switch of the switching regulator). In other words, the on-duration of the PWM signal is related to the charging phase or the rising slope of the inductor current. Similarly, the reference to "off-duration" of a PWM signal refers to the logic state of the PWM signal associated with the discharging phase of the output inductor, where the inductor current decreases or falls (i.e., the inductor is discharged by the current flowing to the load). In other words, the off-duration of the PWM signal is related to the discharging phase or the falling slope of the inductor current. In a peak current mode modulator, the modulator monitors the rising slope of the inductor current to adjust the end of the PWM signal on-duration. In a valley current mode modulator, the modulator monitors the falling slope of the inductor current to adjust the PWM signal off-duration.

[0047] In current-mode controlled voltage regulators, the difference between the DC value of the average inductor current and the sensed inductor current can lead to instability under certain operating conditions. This instability, sometimes referred to as subharmonic oscillation, occurs under steady-state load conditions when the inductor ripple current fails to return to its initial value at the start of the next switching cycle. This instability is particularly problematic when the duty cycle exceeds 50%, i.e., when the power switch is on for more than 50% of a given switching cycle. To ensure stability, a slope compensation ramp is added to the current sensing signal to prevent or eliminate subharmonic oscillations. In some examples, this is derived from the error signal V... COMP Subtract the slope compensation ramp. For example, by adding a compensation ramp signal to the sensed current signal, the tendency for subharmonic oscillations can be suppressed within a switching cycle.

[0048] Examples of slope compensation techniques applicable to the current-mode controlled voltage regulator of the present invention are described in commonly assigned U.S. Patent No. 10,833,661 (published November 10, 2020, entitled "Slope Compensation for Peak Current-Mode Controlled Modulator") and commonly assigned U.S. Patent Application No. 17 / 035012, filed September 28, 2020 ("012 Application"), entitled "Slope Compensation for Current-Mode Controlled Modulator," which are incorporated herein by reference for all purposes.

[0049] More specifically, in Figure 1 In the middle, the current-mode hysteresis modulator 12 is fed back by the feedback voltage V. FB A voltage control loop is implemented, while a current control loop is achieved through a sensed current signal ILn. Figure 1 In the example shown, the current control loop is implemented by receiving a sensed current signal ILn indicating the inductor current at the inductor Ln of each power stage 20. In the '661 patent and '012 application, the current control loop of the current-mode control modulator is implemented using an analog or synthetic current signal. That is, the modulator does not necessarily receive the sensed inductor current value of the current control loop. Instead, the modulator generates an analog current signal indicating the expected inductor current waveform of the current control loop. In this specification, the expected inductor current waveform is referred to as the current-mode signal or the current loop signal, and indicates the expected inductor current behavior at the corresponding power stage of the voltage regulator. In one example, the current loop signal is a synthetic ramp signal that replicates the expected inductor current waveform. Furthermore, the '661 patent and '012 application describe various circuits and methods for generating synthetic ramp signals with integrated ramp compensation.

[0050] For example, '661 and '012 patents describe various configurations of ramp signal generators for generating synthetic ramp signals with integrated ramp compensation, for various topologies of current-mode hysteresis modulators, including peak current modes and valley current modes, each in a buck, boost, or buck-boost configuration. The circuits and methods described in '661 and '012 patents generate analog current signals indicating the expected inductor current waveform, incorporating ramp compensation. More specifically, '661 and '012 patents describe a ramp signal generator implemented using a switched-capacitor circuit with appropriate charge scaling to generate a ramp signal with optimal ramp compensation. Embodiments of the present invention incorporate the ramp signal generators described in '661 and '012 patents, which will be described in more detail below.

[0051] Multiphase switching power supplies require both static and dynamic current sharing between each phase for optimal operation. Static current sharing between phases, also known as DC accuracy, is typically achieved through a slow-regulating loop that monitors the current of each phase relative to the others and modifies the pulse-width modulation (PWM) signal of each phase to correct for its respective current, thereby balancing or equalizing the phase currents between phases. Dynamic current sharing, also known as AC accuracy, is typically achieved by selecting the switching architecture. For example, in buck DC-DC converters (“buck”), the hysteresis current-mode architecture provides relatively good dynamic current balancing. However, AC accuracy can degrade over a wide range of systems and compensation values, especially at the fastest corners of dynamic operation.

[0052] Back Figure 1 Traditional voltage regulators contain a voltage control loop, which is based on the voltage control loop error signal V. COMP Adjusting the duty cycle of the PWM signal to maintain a constant output voltage V OUT Therefore, based on the feedback voltage V FB and expected target V TARG The measurement error between phases is used to achieve pulse width modulation. In some examples, in order to maintain the current balance between phase 1 (IL1), phase 2 (IL2), and phase 3 (IL3), a conventional voltage regulator may include a phase current balancing loop that senses the inductor current of the phase, also known as the phase current, and generates another control signal to adjust the duty cycle of the PWM signal.

[0053] Because these two control loops operate on the same control variable—the PWM duty cycle—one of the control loops must be dominant. This is because the ultimate goal of the voltage regulator is to maintain a constant V. OUTTherefore, the voltage control loop typically controls the response. That is, compared to the phase current balancing loop, the voltage control loop has higher gain and bandwidth. Thus, the voltage regulator can achieve good phase-to-phase current balance at lower frequencies, where the phase current balancing loop has sufficient gain. However, at higher frequencies, the gain of the phase current balancing loop decreases, the current balance becomes unregulated, and it diverges under large dynamic operation of the system.

[0054] More specifically, during large load transient events, the voltage regulator's modulator response changes the duty cycle of the phase PWM signal to match the new voltage regulation level. For a period after the load transient event, the phase currents may become unbalanced. Ideally, the modulator will drive the phase currents to restore balance as quickly as possible. In one example, as the load gradually increases from 0A to 120A, the ideal operating condition is for the modulator to increase the phase currents of all three phases together, so that each phase outputs 40A. However, during large transients, conventional control schemes are often insufficient to maintain phase current balance. Therefore, during large transient events, the phases become unbalanced, with some phases carrying more current than others, and the modulator and phases become out of sync. Conventional control schemes may take a long time to restore a balanced state where the phase currents are equal.

[0055] Embodiments of the present invention provide a multiphase current-mode control modulator that implements a phase current balance control loop, enabling rapid current balancing in a voltage regulator, including during large transient load changes. The phase current balance control loop of the present invention is used to maintain phase current balance and phase synchronization during rapid transient load changes. That is, during transient load events, the phase current balance control loop of the present invention can be used to maintain the phase current at approximately the same current load and can also control the phase to return to a regular phase interval very quickly after the transient event.

[0056] Figure 3 This diagram illustrates a voltage regulator in an embodiment of the invention, which includes a multiphase current-mode hysteresis modulator that implements a phase current balance control loop. For simplicity of discussion, Figure 1 and Figure 3 Similar elements within the same text use similar reference numbers. (Reference) Figure 3 The voltage regulator 50 includes a multiphase current-mode hysteresis modulator 52 (“modulator 52”) coupled to drive the multiphase power block 13. In this embodiment, the multiphase modulator 52 includes three phases (phase 1, phase 2, and phase 3), and the power block 13 includes three power stages 20-1 to 20-3, each phase having an associated output inductor L1 to L3. Output capacitor C OUT Connect to output terminal 28 to provide an regulated output voltage V to the output terminal. OUTPower stages 20-1 to 20-3 receive input voltage V. IN (Node 21), and operates under the control of the PWM signal generated by modulator 52 to provide an output voltage V at output terminal 28. OUT This provides power to load 29.

[0057] The multiphase current-mode hysteresis modulator 52 includes an error amplifier 14, which receives the feedback voltage V. FB and target voltage V TARG To generate the voltage control loop error signal V ERR (Node 17). Error signal V ERR Coupled to a voltage-controlled oscillator (VCO) 22 to generate a clock signal CLK (node ​​24), the clock signal CLK is divided into three clock phases CLK1, CLK2, and CLK3 by a clock sequencer 26. Clock signals CLK1-CLK3 serve as the setpoint signal V. SET1 To V SET3 Coupled to a set of latch circuits 18-1 to 18-3. In this example, each of latch circuits 18-1 to 18-3 is a reset trigger circuit. Modulator 52 includes a set of modulation comparators 16-1 to 16-3, each modulation comparator 16 corresponding to one phase of the multiphase voltage regulator. Modulation comparators 16-1 to 16-3 generate a reset signal V for each of the latch circuits 18-1 to 18-3. RST The latching circuits 18-1 to 18-3 generate multiphase PWM signals PWM1 to PWM3 to drive the various power stages 20-1 to 20-3 in the multiphase power block 13. Each power stage 20-1 to 20-3 is driven in stages.

[0058] In an embodiment of the present invention, the current-mode hysteresis modulator 52 uses a feedback voltage V FB A voltage control loop is implemented, and a current control loop is implemented using a synthesized current loop signal generated in modulator 52. Implementing the current control loop does not require inductor current. According to an embodiment of the invention, the current-mode hysteresis modulator 52 includes a ramp signal generator 54 to generate a ramp signal as a current loop signal indicating the expected inductor current waveform for each phase of the current control loop. Furthermore, the ramp signal generator 54 generates a ramp signal that includes ramp compensation, thus eliminating the need for a separate ramp compensation circuit. In the multi-phase modulator 52, separate ramp signal generators 54-1 to 54-3 are provided for each phase of the modulator. Specifically, for each phase n, ramp signal generator 54n receives a corresponding pulse width modulation signal PWMn and generates a ramp signal VILn, which is provided to the non-inverting input terminal of the corresponding modulation comparator 16n to form the current control loop.

[0059] In embodiments of the invention, the current-mode hysteresis modulator 52 can be configured as a buck modulator for reducing the input voltage or a boost modulator for increasing the input voltage, or a buck-boost modulator that performs both boost and buck functions. Furthermore, in embodiments of the invention, the current-mode hysteresis modulator can be configured for peak current-mode control or valley current-mode control. The exact topology of the modulator 52 is not critical to the implementation of the invention.

[0060] In some embodiments, ramp signal generators 54-1 to 54-3 are implemented using the circuits and methods described in the aforementioned '661 patent and '012 application. Specifically, the '661 patent and '012 application describe various configurations of ramp signal generators for generating analog ramp signals with integrated ramp compensation for various topologies of current-mode hysteresis modulators, including peak current modes and valley current modes, each in a buck, boost, or buck-boost configuration. In some embodiments, ramp signal generators 54-1 to 54-3 in modulator 52 are each configured as switched-capacitor circuits with appropriate charge scaling to generate ramp signals with optimal ramp compensation. Each ramp signal generator 54n generates a ramp signal with integrated ramp compensation as an analog phase current signal VILn of phase n of modulator 52. In other embodiments, other circuits and methods for generating analog phase current signals with ramp compensation may be used. The circuits and methods in the '661 patent and '012 application are illustrative only and are not intended to be limiting.

[0061] In an embodiment of the invention, the modulator 52 includes a phase current balancing circuit 56 to implement a phase current balancing control loop for ensuring rapid current balancing between phases. Specifically, the phase current balancing control loop implemented by the phase current balancing circuit 56 implements a control loop orthogonal to the voltage control loop. Thus, when each phase attempts to correct its phase current relative to other phases, the voltage control loop is not excessively disturbed.

[0062] A significant feature of the phase current balancing circuit 56 of the present invention is that the phase current balancing control loop generates a separate phase current balancing control signal V for each phase. COMPn In some embodiments, the phase control signal V COMPn It includes "equal and opposite" control inputs for the phase current based on phase n relative to the real-time instantaneous average current of all phases. The average or total effect of each individual phase control signal on the voltage control loop is still equivalent to a single combined phase control signal. However, each phase control signal V COMPn It is now able to drive its phase current to balance with other phases.

[0063] In an embodiment of the invention, the phase current balancing circuit 56 receives analog phase current signals VIL1, VIL2, and VIL3 generated by ramp signal generators 54-1 to 54-3. For each phase of the modulator 52, the phase current balancing circuit 56 generates a phase current balancing signal V indicating the difference between each phase current VILn and the average value of all phase currents. PHBALn (Node 64). Current balance signal V for each phase. PHBALn With voltage control loop error signal V ERR Combined to generate the corresponding phase control signal V COMPn Then, each phase control signal V COMPn The phase current balancing circuit 56 generates a phase control signal V coupled to the inverting input terminal of each modulation comparator 16-1 for phase 1. COMP1 For phase 2, the phase current balancing circuit 56 generates a phase control signal V coupled to the inverting input terminal of the modulation comparator 16-2. COMP2 For phase 3, the phase current balancing circuit 56 generates a phase control signal V coupled to the inverting input terminal of the modulation comparator 16-3. COMP3 The modulator 52 of this invention differs from conventional modulators, in which the same voltage control loop error signal (sometimes referred to as V) is used. ERR or V COMP Modulation comparators applicable to all phases, such as Figure 1 The example is shown in the image.

[0064] Another significant feature of the phase current balancing circuit 56 of the present invention is that it uses an analog phase current signal with integrated slope compensation to perform phase current balancing. In this way, the phase current balancing control loop achieves greater stability.

[0065] The detailed structure of the phase current balancing circuit 56 is as follows: Figure 4 and Figure 5 As shown. Figure 4 This diagram illustrates a multiphase current-mode hysteresis modulator that implements a phase current balancing circuit in an embodiment of the present invention. Figure 5 This is a simplified schematic diagram of one phase of a phase current balancing circuit in some embodiments. For the sake of simplicity, Figure 3 , 4 Similar reference numerals were used for elements similar to those in 5. In the description below, Figure 4 This is an illustration of a modulator containing three phases (phase 1, phase 2, and phase 3), and... Figure 5 Indicates representative Figure 4 One of the phases (phase n) of any given phase. (Reference) Figure 4 and Figure 5 The phase current balancing circuit 56 receives analog phase current signals VIL1, VIL2, and VIL3 generated by ramp signal generators 54-1, 54-2, and 54-3. The phase current balancing circuit 56 includes a signal averaging circuit 60, which receives the analog phase current signals VIL1, VIL2, and VIL3 and provides an average phase current signal V. ILAVG This is the average value of the analog phase current signals VIL1, VIL2, and VIL3. In some embodiments, the signal averaging circuit 60 provides a real-time average of the analog phase current signals VIL1, VIL2, and VIL3. In one embodiment, the average phase current signal V... ILAVG It is the quotient of the sum of N analog phase current signals divided by N.

[0066] The phase current balancing circuit 56 includes a set of amplifier circuits 62 for comparing the average phase current signal with individual analog phase current signals. Specifically, amplifier 62n receives the average phase current signal V at its inverting input terminal. ILAVG It receives an analog phase current signal VILn with phase n at the non-inverting input terminal. Amplifier circuit 62n generates signals representing the analog phase current signal VILn and the average phase current signal V. ILAVG The phase current balance signal V between the differences PHBALn (Node 64n). This difference can be amplified by amplifier circuit 62n. In an embodiment of the invention, the phase current balance signal V PHBALn (Node 64n) can be a voltage signal or a current signal. In this embodiment, the set of amplifier circuits 62-1 to 62-3 are each operational transconductance amplifiers (OTA), which provide an indication of the analog phase current signal VILn and an average phase current signal V. ILAVG The difference between the output currents is calculated. At the parallel resistor-capacitor circuit 66n, the output currents indicating different currents are converted into voltage signals. Therefore, in this embodiment, the resulting phase current balance signal V... PHBALn It is a voltage signal.

[0067] Furthermore, in embodiments of the present invention, for each phase n, the phase current balance signal V PHBALn With voltage control loop error signal V ERR Combination (node ​​17). In other words, the phase current balanced signal V PHBALn It can be added to the voltage control loop error signal V ERR Add or subtract from it. The combined signal is the phase control signal V of each phase n. COMPn In this embodiment, the voltage control loop error signal V ERR (Node 17) and the phase current balance signal V at each phase of the parallel resistor-capacitor circuit 66n.PHBALn Combination. Specifically, each parallel resistor-capacitor circuit 66n includes a resistor R66 and a capacitor C66 connected in parallel. Voltage control loop error signal V ERR (Node 17) is connected to one end of the parallel circuit, while the phase current balance signal V PHBALn Connect to the other end of the parallel circuit.

[0068] Phase current balancing circuit 56 generates phase control signals V for each phase of modulator 52. COMPn Each phase control signal is provided to each modulation comparator to complete the phase current balance control loop. Through this configuration, the phase current balance control loop generates the phase control signal V. COMPn This forces the simulated phase current signal VILn of each phase to reach the average phase current value.

[0069] For example, amplifier circuit 62-1 generates a phase current balance signal V. PHBAL1 (Node 64-1) This signal is converted by the parallel resistor-capacitor circuit 66-1 into an error signal V. ERR The combined voltage signals. The resulting phase control signal V. COMP1 The signal is supplied to the inverting input terminal 58-1 of the modulator comparator 16-1 for phase 1. Simultaneously, the amplifier circuit 62-2 generates the phase current balance signal V. PHBAL2 (Node 64-2) This signal is converted by the parallel resistor-capacitor circuit 66-2 into an error signal V. ERR The combined voltage signals. The resulting phase control signal V. COMP2 The signal is supplied to the inverting input terminal 58-2 of the modulator comparator 16-2 for phase 2. The amplifier circuit 62-3 generates the phase current balance signal V. PHBAL3 (Node 64-3) This signal is converted by the parallel resistor-capacitor circuit 66-3 into an error signal V. ERR The combined voltage signals. The resulting phase control signal V. COMP3 The inverting input terminal 58-3 of the modulator comparator 16-3 for phase 3 is provided.

[0070] In modulator 52, each phase receives a separate phase control signal V. COMPn This is to control the phase current of that phase and achieve current balance. More specifically, each phase control signal V... COMPn(Node 58n) is coupled to the inverting input terminal of modulation comparator 16n for comparison with the analog phase current signal VILn coupled to the non-inverting input terminal. Modulation comparator 16n generates a duty cycle control signal for controlling the duty cycle of the PWM signal PWMn for the corresponding phase. In this embodiment, the duty cycle control signal is the reset voltage signal V. RSTn It is coupled to the reset input terminal of latch circuit 18n to generate PWM signal PWMn. The duty cycle control signal or reset voltage signal V... RSTn The operation terminates the on-time of the PWM signal, thereby controlling the duty cycle of the PWM signal.

[0071] In an embodiment of the invention, the phase current balancing circuit achieves variable gain control of the phase current balancing control loop by adjusting the gain of the amplifier circuit 62n through a tuned amplifier circuit. In this embodiment, the gain of the tunable operational transconductance amplifier 62n is used to achieve the desired gain level of the phase current balancing control loop. For example, the gain of the OTA can be tuned by coupling a given resistor value at the output of the OTA.

[0072] Figure 6 Include Figure 6 (a) and Figure 6 (b) indicates that, in embodiments of the present invention, an exemplary signal averaging circuit can be incorporated into the phase current balancing circuit. Reference Figure 6 (a) The signal averaging circuit 70 includes two operational transconductance amplifiers (OTAs) 72 and 73, which receive the individual phase current signals to be averaged, such as analog phase currents VIL1 and VIL2. OTAs 72 and 73 have the same gain value K. The output terminals of OTAs 72 and 73 are connected to a common node 74. A resistor R70 is connected between the common node 74 and ground potential to generate a voltage Vx indicating the average current value of the analog phase currents VIL1 and VIL2.

[0073] refer to Figure 6 (b) The signal averaging circuit 75 includes two amplifiers 76 and 78, which receive the phase current signals to be averaged, such as analog phase currents VIL1 and VIL2, respectively. Amplifiers 76 and 78 are configured in a unity-gain configuration. The output of amplifier 76 is coupled to a common node 79 via resistor R75-1. The output of amplifier 78 is coupled to a common node 79 via resistor R75-2. Resistors 75-1 and 75-2 have the same resistance value. A voltage Vx is generated at node 79, indicating the average current value of the analog phase currents VIL1 and VIL2.

[0074] In this example, the voltage Vx is expressed as:

[0075] Vx=Avg(VIL1,VIL2)=0.5*(VIL1+VIL2).

[0076] exist Figure 6 The signal averaging circuit shown illustrates a circuit for calculating the average of two signals. Those skilled in the art will understand that a signal averaging circuit for N signals can be constructed accordingly. Furthermore, Figure 6 (a) and Figure 6 The signal averaging circuit in (b) is for illustrative purposes only and is not intended to be limiting. Other circuits may be used to generate the average of two signals.

[0077] Figure 7 It copied '661 patent' Figure 7 The diagram shows a ramp signal generator. Ramp compensation is incorporated into the peak current mode buck modulator. In an embodiment of the present invention, the peak current mode buck modulator can be incorporated into the current mode control modulator. Figure 7 This illustrates an example of a ramp signal generator, which can be used to generate analog phase current signals with ramp compensation. (Reference) Figure 7 A ramp signal generator 90 is incorporated into a current-mode controlled hysteresis modulator 80. In embodiments of the invention, the current-mode controlled hysteresis modulator 80 refers to a modulator containing a current control loop, typically combined with a voltage control loop. In this embodiment, the current-mode controlled hysteresis modulator is a peak current-mode hysteresis buck modulator, also referred to herein as a peak current-mode buck modulator. The peak current-mode modulator controls the duty cycle of the power switch in response to the peak value of the current loop signal, which indicates the expected inductor current waveform of the current control loop. Furthermore, in this embodiment, the peak current-mode modulator 80 uses the synthesized current loop signal for the current control loop and does not require feedback of the sensed inductor current signal to the modulator.

[0078] Specifically, the modulator 80 includes a receive feedback voltage V. FB and target voltage V TARG Error amplifier 14 is used to generate error signal V at node 82. COMP In one example, error amplifier 14 is a transconductance amplifier and generates an output current signal, which is converted into a voltage signal by a loop filter 15 coupled to output node 82. Therefore, in this example, the error signal V at node 82... COMP It is a voltage signal. Error signal V COMP Coupled to the inverting input terminal of modulation comparator 84. Ramp signal generator 90 generates ramp signal V. RAMP (Node 92) is provided to the non-inverting input terminal of the modulation comparator 84. The modulation comparator 84 generates a reset signal V coupled to the reset input terminal of the latch circuit 86.RST The latch circuit 86 receives the error signal V from the voltage-controlled oscillator (not shown). COMP The generated clock signal CLK serves as the setting signal V coupled to the setting input terminal of the latch circuit 86. SET In one example, latch circuit 86 is a flip-flop circuit. Latch circuit 86 generates a pulse width modulation (PWM) signal at output node 88. In the case where modulator 80 is a multiphase modulator, Figure 7 The schematic diagram in the image represents a single-phase n of modulator 80. Modulation comparator 84 receives the ramp signal V. RAMPn The latch circuit 86 generates a reset signal for the latch circuit 86. The latch circuit 86 also receives a clock signal CLKn as a setting signal. At the output node 88, the latch circuit 86 generates a pulse width modulation signal PWMn for the phase n of the multi-phase modulator.

[0079] In an embodiment of the present invention, the ramp signal generator 90 uses a switched capacitor circuit to generate a ramp signal V. RAMP (Node 92). When combined with the voltage at node 92, the resulting ramp signal V RAMP It includes information about the expected inductor current waveform and also incorporates slope compensation. Therefore, the slope signal generator 90 integrates slope compensation while generating the slope signal as a current loop signal. No additional slope compensation circuitry is required.

[0080] The ramp signal generator 90 includes a capacitor C1 coupled between nodes 96 and 94 and a capacitor C2 coupled between nodes 92 and 94. Node 94 is biased to a reference voltage VREF, for example, via a voltage source V1. A switch S1 is coupled between capacitors C1 and C2 (i.e., between nodes 96 and 92) to form a switched capacitor circuit. Switch S1 is controlled by a signal indicating a pulse width modulation (PWM) signal. Specifically, switch S1 is inversely controlled by the PWM signal, such that switch S1 opens in response to the on-duration of the PWM signal and closes in response to the off-duration of the PWM signal.

[0081] The ramp signal generator 90 includes a signal generator that provides input voltage V. IN A first current source I1 provides a current proportional to the input voltage V. In one embodiment, the first current source I1 provides a current proportional to the input voltage V. IN The current is proportional to K times the input voltage V, where K is a number greater than 0. A first current source I1 is connected to node 92 via a switch S2 controlled by a pulse width modulation (PWM) signal to provide current to node 92 during the on-time of the PWM signal. The ramp signal generator 90 also includes a current source that provides current proportional to the input voltage V. IN A second current source I2 provides a proportional current and supplies the output voltage V.OUT A first current receiver I3 provides a current proportional to twice the input voltage V. In one embodiment, a second current source I2 provides a current proportional to K times the input voltage V. IN The proportional current, the first current receiver I3 provides with 2K times the output voltage V OUT A proportional current source I2 is connected to node 96 via a switch S3 controlled by a pulse width modulation (PWM) signal to supply current to node 96 during the on-time of the PWM signal. Simultaneously, a first current receiver I3 is directly connected to node 96 to receive current from node 96.

[0082] In some embodiments, the ramp signal generator 90 further includes a resistor R2 coupled between nodes 92 and 94, i.e., in parallel with capacitor C2. Resistor R2 removes the DC component of the ramp signal at node 92, leaving only the AC component (or triangular ripple) of the ramp signal, where the AC component tracks the upper and lower ramps of the inductor current waveform. Resistor R2 is optional and may be omitted in other embodiments of the invention. The use of resistor R2 improves DC bias and transient performance.

[0083] In some embodiments, capacitor C1 and capacitor C2 have the same capacitance value. In other embodiments, capacitors C1 and C2 may have different capacitance values ​​to adjust the amount of slope compensation provided, as described in more detail below.

[0084] In operation, the ramp signal generator 90 uses a switched-capacitor circuit with capacitors C1 and C2 and switch S1 to generate a ramp-compensated ramp signal V. RAMP When the ramp signal rises or increases, the ramp signal V... RAMP It has an ascending ramp portion. The ramp signal V decreases or drops as the ramp signal descends. RAMP It has a descending ramp portion. In this embodiment, for the peak current mode buck modulator 80, the ramp signal generator 90 generates the ramp signal V by dividing or splitting the charge of the expected current mode signal in the upper ramp portion by the two capacitors C1 and C2 and sharing the charge between the two capacitors C1 and C2 in the lower ramp portion. RAMP .

[0085] More specifically, optimal slope compensation is achieved when the slope compensation slope equals the slope of the current-mode signal (the inductor current waveform to be replicated). For example, for a peak current-mode buck modulator, the current-mode signal has a slope of -gm*V. OUT / C represents the descent rate or descent ramp. To achieve optimal ramp compensation control, the ramp signal descent ramp should be set to -gm*V. OUT / C.

[0086] In this embodiment, the ramp signal generator 90 generates a ramp signal with optimal ramp compensation by subtracting a given amount of signal during the PWM on-time and then during the PWM off-time. The ramp signal generator 90 ensures that the ramp signal returns to the desired position with the desired ramp.

[0087] To replicate the inductor current waveform in peak current mode operation of the buck converter, without slope compensation, the current ramp (or ramp) of the ramp signal during the PWM on-time should be equal to (V... IN -V OUT The current downslope (or descent) during the PWM off-time should be proportional to -V. OUT Proportional. In other words, the ramp signal without slope compensation should match the ramp rate of the current-mode signal (inductor current waveform).

[0088] In the peak current-mode buck modulator of the present invention, the ramp signal generator achieves ramp compensation by matching the downward slope of the ramp signal with the downward current slope of the current-mode signal during the PWM off-duration. With this configuration, the amount by which the PWM on-duration is shortened is equal to the amount of V removed from the ramp. OUT The situation regarding the term. Therefore, in order to introduce slope compensation into the slope signal, the uphill slope of the slope signal and V... IN Proportional, rather than as in the case without slope compensation, the slope signal uphill is proportional to (V IN -V OUT Proportional.

[0089] The ramp signal generator 90 achieves ramp signal generation and ramp compensation by using a switched capacitor circuit to divide the charge associated with the current-mode signal during the rising ramp between two capacitors and to share the charge associated with the current-mode signal during the falling ramp, while maintaining the total charge over a given switching cycle. In this configuration, capacitor C2 provides the rising ramp of the ramp signal, and capacitors C1 and C2 in parallel provide the falling ramp. During the PWM on-time when switch S1 is open and switches S2 and S3 are closed, capacitor C2 removes V... OUT The current charges the phase. That is, during the PWM on-time, capacitor C2 is charged by K*V. IN Proportional current charging. When switch S1 is open, the ramp signal V... RAMP (Node 92) is the voltage VC2 across capacitor C2. In this way, the ramp signal V... RAMP (Node 92) has an ascending slope that includes slope compensation. Slope signal V RAMP The ramp rises during the PWM on-time to provide a ramp with ramp compensation to the modulation comparator 84.

[0090] Furthermore, during the PWM on-time, capacitor C1 accumulates missing charge, which will be applied to capacitor C2 when slope compensation is not implemented. Specifically, capacitor C1 is charged to K*V by the second current source I2 (via switch S3) and the first current receiver I3. IN -2K*V OUT A proportional voltage. When switch S1 is open, the voltage VC1 across capacitor C1 rises to store the charge not contained in capacitor C2.

[0091] Under the peak current control scheme, when the ramp signal V RAMP Arrival error signal V COMP At node 82, modulation comparator 84 is triggered and the PWM signal is reset. The PWM on-time ends and the PWM off-time begins. Accordingly, switch S1 closes and switches S2 and S3 open. Therefore, capacitors C1 and C2 are connected in parallel and disconnected from current source I1 or I2. That is, nodes 92 and 96 are shorted together. The charge accumulated on capacitors C1 and C2 is shared, and the ramp signal V... RAMP This becomes the average of the capacitor voltages VC1 and VC2. Due to charge sharing, the ramp signal V... RAMP Without slope compensation, the descent begins at the point where it should be located. That is, the slope of the descent slope of the slope signal is -K*V. OUT In the ramp signal generator 90, the effective capacitance is doubled by using capacitors C1 and C2 in parallel, but the first current receiver I3 provides the output voltage V. OUT The current is twice that of the signal, thus maintaining the ramp rate. The ramp signal V RAMP The clock signal decreases until the next switching cycle is indicated by the CLK instruction.

[0092] In an embodiment of the present invention, Figure 7 The ramp signal generator 90 can be used to generate an analog phase current signal VILn for each phase of the multiphase current mode control modulator 52 in the above embodiment. It is worth noting that... Figure 7 This illustrates the structure of an exemplary ramp signal generator circuit. Figure 7 The remaining circuit connections of the modulator 80 are for illustrative purposes only and are not necessarily applicable to the modulator 52 of this invention. Specifically, Figure 7 The modulator 80 does not include the implementation of a phase current balance control loop, therefore the error signal V COMP Instead of being combined with the phase current balance signal to generate the phase control signal for each phase, it is provided to the modulation comparator 84, as in the case of the modulator 52 described above.

[0093] In the above embodiments, single-ended signaling is used to implement the current-mode control modulator. In other embodiments, differential signaling can be used to implement the current-mode control modulator. The specific signaling scheme employed is not critical to the practice of this invention.

[0094] Figure 8(a) and 8(b) The included signal waveforms illustrate the operating characteristics of voltage regulators in some examples that incorporate a four-phase current-mode hysteresis modulator. Specifically, Figure 8(a) shows the signal waveform of a four-phase modulator without current balancing, and Figure 8(b) shows the signal waveform of a four-phase modulator achieving fast current balancing using the phase current balancing control loop of the present invention described above. Referring to Figure 8(a), curve 102a shows the error signal V caused by a load step or step load change. COMP Curve 103a shows voltages VL1 to VL4, indicating the inductor current in response to a load step change in four phases. Curve 104a represents the output voltage V of the voltage regulator. OUT Curve 106a illustrates the behavior of the four-phase inductor currents IL1 to IL4 in response to a load step change. As shown in Figure 8(a), without rapid current balancing, the current difference between the four phases can reach as high as 20A. In other words, in response to a load step change, the four phases of the modulator can operate for extended periods under large differences in current load. This operating mode is undesirable.

[0095] Referring to Figure 8(b), when the modulator achieves fast current balancing, due to a load step or step load change, the modulator generates a set of error signals V. COMP1 To V COMP4 (Curve 102b). Curve 103b represents voltages VL1 to VL4, indicating the inductor current in response to the four phases of a load step. Curve 104b represents the output voltage V of the voltage regulator. OUT Curve 106ba illustrates the behavior of the four-phase inductor currents IL1 to IL4 using fast current balancing in response to a load step. As shown in Figure 8(b), by using fast current balancing, the current difference between the four phases due to the load change is less than 5A. That is, due to the load step change, the four phases in the modulator are only unbalanced for a short time, and the modulator can quickly return to a stable operating state where the four phases share the load current equally. Note that Figures 8(a) and 8(b) are not on the same time scale. Figure 8(b) has been enlarged to show the small current difference between the phases.

[0096] This invention can be implemented in various ways, including as a process; an apparatus; a system; and / or a composition of matter. In this specification, these implementations or any other form of the invention that may take place may be referred to as techniques. Generally, within the scope of this invention, the order of the steps of the disclosed methods can be changed.

[0097] The foregoing provides a detailed description of one or more embodiments of the present invention, along with accompanying drawings illustrating the principles of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims, and includes numerous alternatives, modifications, and equivalents. Numerous specific details are set forth in the specification to provide a thorough understanding of the invention. These details are provided for illustrative purposes and the invention may be practiced according to the claims without the need for some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so that the invention is not unnecessarily obscured.

[0098] The above detailed description is provided to illustrate specific embodiments of the invention and is not intended to limit the invention. Many modifications and variations are possible within the scope of this invention. The invention is defined by the appended claims.

Claims

1. A multiphase current mode hysteresis modulator for generating a plurality of pulse width modulated (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and delivering a phase current through a respective inductor to an output node to which an output capacitor and a load are connected, said plurality of PWM signals being generated in response to a feedback voltage signal indicative of a regulated output voltage at the output node, characterized by, The current mode hysteretic modulator includes: a voltage control loop coupled to receive feedback voltage signals indicative of the regulated output voltage and a target voltage, and to generate a voltage control loop error signal indicative of a difference between the feedback voltage signals and the target voltage; and a phase current balance control loop coupled to receive slope compensated analog phase current signals generated for the plurality of phases, each slope compensated analog phase current signal indicative of an expected current level of a phase current delivered by a corresponding power stage and including a slope compensation signal, the phase current balance control loop determining a difference between the slope compensated analog phase current signal and an average phase current signal for each phase to generate a phase current balance control signal for each phase, wherein the phase current balance control signal for each phase is combined with the voltage control loop error signal to generate a phase control signal for each phase, and the phase control signal for each phase is compared to the slope compensated analog phase current signal for the corresponding phase to generate a duty cycle control signal, the duty cycle control signal controlling a duty cycle of a PWM signal for the corresponding phase, the duty cycle control signals generated for the plurality of phases to control the phase currents delivered by the plurality of power stages.

2. The multiphase current mode hysteresis modulator of claim 1, wherein, The voltage control loop includes: a first error amplifier receiving the feedback voltage signals indicative of the regulated output voltage and the target voltage, the first error amplifier generating the voltage control loop signal indicative of the difference between the feedback voltage signals and the target voltage at an output terminal; a plurality of modulation comparators, each modulation comparator associated with a respective phase and having a first input terminal receiving a combined signal of the voltage control loop signal and the phase current balance control signal for the respective phase and a second input terminal receiving the slope compensated analog phase current signal for the respective phase, each modulation comparator generating a phase control signal for the corresponding phase, the phase control signal being a reset signal; and a plurality of latch circuits, each latch circuit associated with a respective phase and having a reset input terminal coupled to receive the reset signal from the modulation comparator for the respective phase, a set input terminal coupled to receive a clock signal for the respective phase, and an output terminal generating a PWM signal for the corresponding phase to drive the corresponding power stage, the PWM signal having an on duration and an off duration defining a duty cycle of the PWM signal, wherein the clock signal initiates the on duration of the PWM signal as a set signal and the reset signal terminates the on duration of the PWM signal.

3. The multiphase current mode hysteresis modulator of claim 1, wherein, The phase current balance control loop includes: a plurality of ramp signal generator circuits, each ramp signal generator circuit associated with a respective phase and receiving the PWM signal for the respective phase, each ramp signal generator circuit including a switched capacitor circuit implementing charge scaling to generate the slope compensated analog phase current signal for the respective phase.

4. The multiphase current mode hysteresis modulator of claim 3, wherein, The phase current balance control loop further includes: a signal averaging circuit that receives the slope-compensated analog phase current signals of the plurality of phases and generates an average phase current signal indicative of an average current value of the slope-compensated analog phase current signals of all phases; a plurality of amplifier circuits, each amplifier circuit associated with a respective phase and receiving the average phase current signal and the slope-compensated analog phase current signal of the respective phase, each amplifier circuit generating a phase current balance control signal for the respective phase indicative of a difference between the slope-compensated analog phase current signal and the average phase current signal of the respective phase.

5. The multiphase current mode hysteresis modulator of claim 4, wherein, The plurality of amplifier circuits includes: a plurality of operational transconductance amplifiers, each operational transconductance amplifier having a non-inverting input terminal coupled to receive the average phase current signal and an inverting input terminal coupled to receive the slope-compensated analog phase current signal of the respective phase, each operational transconductance amplifier generating an output current signal indicative of a difference between the slope-compensated analog phase current signal and the average phase current signal of the respective phase; a plurality of current-to-voltage conversion circuits, each current-to-voltage conversion circuit coupled to receive the output current signal from the respective operational transconductance amplifier of the respective phase and provide a voltage signal as the phase current balance control signal, wherein the phase current balance control signals are summed or subtracted from the voltage control loop signal to generate a combined signal for each phase.

6. The multiphase current mode hysteresis modulator of claim 5, wherein, Each of the plurality of current-to-voltage conversion circuits includes a parallel resistance-capacitance circuit.

7. The multiphase current mode hysteresis modulator of claim 3, wherein, The modulator includes a peak current buck modulator, each of the plurality of ramp signal generators generates a slope-compensated analog phase current signal having a rising slope proportional to the input voltage during an on duration of the PWM signal of the respective phase and a falling slope proportional to the output voltage during an off duration of the PWM signal of the respective phase.

8. The multiphase current mode hysteresis modulator of claim 3, wherein, The modulator includes one of a peak current buck modulator, a peak current boost modulator, a valley current buck modulator, and a valley current boost modulator.

9. A method of controlling phase current in a multiphase voltage regulator, characterized by, The method includes: generating a plurality of pulse width modulated (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and delivering a phase current to an output node through a respective inductor, an output capacitor and a load connected to the output node, wherein the plurality of PWM signals are generated in response to a feedback voltage signal indicative of a regulated output voltage at the output node; generating a voltage control loop signal indicative of a difference between the feedback voltage signal and a target voltage; generating a plurality of slope-compensated analog phase current signals for the plurality of phases, each slope-compensated analog phase current signal indicative of an expected current level of a phase current delivered by a respective power stage and including a slope compensation signal; generating a phase current balance control signal for each phase indicative of a difference between the slope-compensated analog phase current signal and the average phase current signal of the respective phase; and combining the phase current balance control signal for each phase with the voltage control loop signal, and comparing the combined signal with the slope compensated analog phase current signal for the corresponding phase to generate the phase control signal for the corresponding phase, the phase control signal controlling the duty cycle of the PWM signal for the corresponding phase, wherein the phase control signals are generated for the plurality of phases to control the phase current delivered by each power stage.

10. The method of claim 9, wherein, The generating the voltage control loop signal indicative of a difference between the feedback voltage signal and the target voltage includes: The generating the voltage control loop signal indicative of a difference between the feedback voltage signal and the target voltage includes using an error amplifier.

11. The method of claim 10, wherein, The generating the phase control signal includes: providing a plurality of modulation comparators to generate the phase control signals for the plurality of phases; at each modulation comparator associated with a corresponding phase, coupling a combined signal of the voltage control loop signal and the phase current balance control signal for the corresponding phase to a first input terminal, and coupling the slope compensated analog phase current signal for the corresponding phase to a second input terminal; and generating the phase control signal at an output of each modulation comparator as a reset signal for the corresponding phase.

12. The method of claim 9, wherein, The generating the plurality of slope compensated analog phase current signals for the plurality of phases includes: generating the slope compensated analog phase current signals in response to the PWM signals for the respective phases using a plurality of ramp signal generator circuits, each ramp signal generator circuit including a switched capacitor circuit that implements charge scaling to generate the slope compensated analog phase current signal for the respective phase.

13. The method of claim 12, wherein, The generating the phase current balance control signal for each phase includes: generating an average phase current signal by averaging the slope compensated analog phase current signals for all phases; and for each phase, generating a current signal indicative of a difference between the slope compensated analog phase current signal for the respective phase and the average phase current signal; and for each phase, converting the current signal to a voltage signal as the phase current balance control signal for the corresponding phase.

14. The method of claim 13, wherein, The converting the current signal to a voltage signal as the phase current balance control signal for the respective phase includes: for each phase, converting the current signal to a voltage signal using a parallel resistor-capacitor circuit as the phase current balance control signal for the corresponding phase.

15. The method of claim 12, wherein, The multi-phase voltage regulator implements peak current buck current mode control and generates the slope compensated analog phase current signals using a plurality of ramp signal generator circuits includes: at each ramp signal generator for the respective phase, receiving a pulse width modulated signal having an on duration and an off duration; during the on duration of the pulse width modulated signal, generating an up ramp of a ramp signal, the slope of the ramp signal being proportional to an input voltage; during the off duration of the pulse width modulated signal, generating a down ramp of the ramp signal, the slope of the ramp signal being proportional to an output voltage; and providing the up ramp and the down ramp as the slope compensated analog phase current signal for the corresponding phase.

16. The method of claim 12, wherein, The multi-phase voltage regulator implements peak current buck current mode control, peak current boost current mode control, valley current buck current mode control, and valley current boost current mode control.

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