Holding time detection sensor, method, chip, chip module and electronic device

Abstract

The present application provides a hold time detection sensor, method, chip, chip module, and electronic device. In the hold time detection sensor, a first adjustable delay module is used to adjust a first transmit clock delay from a signal source to a clock end of a first transmit register and a second transmit clock delay from a signal source to a clock end of a second transmit register; a second adjustable delay module is used to adjust a first capture clock delay from a signal source to a clock end of a first capture register and a second capture clock delay from a signal source to a clock end of a second capture register; and a third adjustable delay module is used to adjust a first data delay from an output end of the first transmit register to a data end of the first capture register and a second data delay from an output end of the second transmit register to a data end of the second capture register, thereby achieving register hold time detection.

Description

Technical Field

[0001] The present application relates to chip technology, and in particular to a retention time detection sensor, method, chip, chip module and electronic device. Background Art

[0002] In chip design, designers need to use simulation program with integrated circuit emphasis (SPICE) files provided by semiconductor manufacturers to implement circuit design and circuit simulation. Before chip tape-out, they need to complete timing circuit analysis and verification through SPICE files to ensure that the chip timing can meet the design requirements so that the produced chips can operate normally.

[0003] Hold time refers to the time after the rising edge of the register's clock signal arrives, during which the data remains stable and unchanged. In other words, the time during which the data remains unchanged so that it can be read stably. As a key parameter of register timing information in digital circuits, if a reasonable hold time cannot be met during timing verification, the designed chip will fail. Because the information described in the SPICE file may deviate from the actual chip, there is no guarantee that the design verified by SPICE simulation will be completely consistent with the actual chip produced. Therefore, while the chip meets the SPICE simulation verification, some peripheral logic needs to be added to meet the operating timing requirements that may be brought about by the actual chip. Therefore, actual testing is necessary to obtain the hold time of the registers on the chip. Summary of the Invention

[0004] The present application provides a hold time detection sensor, method, chip, chip module and electronic equipment, which realize accurate detection of hold time.

[0005] In a first aspect, the present application provides a hold time detection sensor, comprising: a signal source, a first adjustable delay module, a second adjustable delay module, a third adjustable delay module, a first transmitting register, a first capturing register, a second transmitting register, and a second capturing register;

[0006] The signal source is used to provide a pulse signal to the first adjustable delay module, the second adjustable delay module, the first transmitting register, and the first transmitting register;

[0007] The first adjustable delay module is used to adjust a first transmit clock delay from the signal source to a clock end of the first transmit register, and is used to adjust a second transmit clock delay from the signal source to a clock end of the second transmit register;

[0008] The second adjustable delay module is used to adjust a first capture clock delay from the signal source to the clock end of the first capture register, and is used to adjust a second capture clock delay from the signal source to the clock end of the second capture register;

[0009] The third adjustable delay module is used to adjust a first data delay from the output end of the first transmit register to the data end of the first capture register, and is used to adjust a second data delay from the output end of the second transmit register to the data end of the second capture register;

[0010] The output of the first capture register, the output of the second capture register, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine a hold time of the first capture register.

[0011] In one embodiment, the first adjustable delay module, the second adjustable delay module and the third adjustable delay module are all adjustable delay ring oscillators;

[0012] The adjustable delay ring oscillator includes a first ring oscillator, a first selector, a second ring oscillator and a second selector;

[0013] The input end of the first ring oscillator is the first input end of the adjustable delay ring oscillator, the first selector is used to delay the signal of the first input end by a first preset time and then output it through the first output end, the input end of the second ring oscillator is the second input end of the adjustable delay ring oscillator, the second selector is used to delay the signal of the second input end by a second preset time and then output it through the second output end, and the first preset time and the second preset time are both adjustable.

[0014] In one embodiment, the signal source is connected to the first input end and the second input end of the first adjustable delay module respectively, the first output end of the first adjustable delay module is connected to the clock end of the first transmitting register, and the second output end of the first adjustable delay module is connected to the clock end of the second transmitting register.

[0015] In one embodiment, the signal source is respectively connected to the first input end and the second input end of the second adjustable delay module, the first output end of the second adjustable delay module is connected to the clock end of the first capture register, and the second output end of the second adjustable delay module is connected to the clock end of the second capture register.

[0016] In one embodiment, the output terminal of the first transmitting register is connected to the first input terminal of the third adjustable delay module, and the first output terminal of the third adjustable delay module is connected to the data terminal of the first capturing register;

[0017] The output end of the second transmitting register is connected to the second input end of the third adjustable delay module, and the second output end of the third adjustable delay module is connected to the data end of the second capturing register.

[0018] In one embodiment, the invention further comprises: an XOR gate;

[0019] The output end of the first capture register and the output end of the second capture register are connected to the XOR gate, and the output of the XOR gate, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine the hold time of the first capture register.

[0020] In one embodiment, the invention further comprises: a first register and a second register;

[0021] The output end of the XOR gate is connected to the data end of the first register, the clock end of the first register is connected to the signal source, the output end of the first register is connected to the clock end of the second register, and the data end of the second register is connected to a high level or ground;

[0022] The output of the second register, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine a hold time of the first capture register.

[0023] In one embodiment, the invention further comprises: a third register;

[0024] The clock end of the third register is connected to the signal source, the output end of the third register is connected to the data end of the third register through an inverter, and the output end of the third register is connected to the data end of the first transmitting register and the data end of the second transmitting register.

[0025] In a second aspect, the present application provides a hold time detection method, applied to the hold time detection sensor as described in the first aspect, the method comprising:

[0026] Setting the second transmit clock delay, the second capture clock delay, and the second data delay to maximum values;

[0027] Traversing all value combinations of the first transmit clock delay, the first capture clock delay, and the first data delay, and respectively obtaining an exclusive OR value of the output of the first capture register and the output of the second capture register corresponding to each value combination;

[0028] The holding time of the first capture register is determined according to the XOR value and the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to the XOR value.

[0029] In one embodiment, determining the hold time according to the XOR value and the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to the XOR value includes:

[0030] Sort the XOR values ​​in descending order of the first transmit clock delay, the first capture clock delay, and the first data delay, and determine at least one target XOR value that is adjacent to the XOR value having a value of 1 and is not 1;

[0031] The hold time is determined according to a first transmit clock delay, a first capture clock delay, and a first data delay corresponding to each of the at least one target XOR value.

[0032] In one embodiment, determining the hold time according to the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to each of the at least one target XOR value includes:

[0033] The first data delay corresponding to each of the at least one target XOR values ​​is added to the first transmission clock delay and then subtracted from the first capture clock delay, and the minimum value of the obtained results is determined as the hold time.

[0034] In a third aspect, the present application provides a chip comprising the holding time detection sensor as described in the first aspect above.

[0035] In a fourth aspect, the present application provides a chip module, comprising the chip as described in the third aspect above.

[0036] In a fifth aspect, the present application provides an electronic device, comprising: a memory, a processor, and a transceiver;

[0037] The memory is used to store computer programs;

[0038] The processor is configured to implement the method described in the second aspect above when the computer program is executed.

[0039] In a sixth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the second aspect above is implemented.

[0040] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the method described in the second aspect above.

[0041] The present application provides a hold time detection sensor, method, chip, chip module and electronic device. The aging sensor includes a signal source, a first adjustable delay module, a second adjustable delay module, a third adjustable delay module, a first transmitting register, a first capture register, a second transmitting register and a second capture register; the signal source is used to provide a pulse signal to the first adjustable delay module, the second adjustable delay module, the first transmitting register and the first transmitting register; the first adjustable delay module is used to adjust the first transmitting clock delay from the signal source to the clock end of the first transmitting register, and is used to adjust the second transmitting clock delay from the signal source to the clock end of the second transmitting register; the second adjustable delay module is used to The first capture clock delay from the signal source to the clock end of the first capture register is adjusted, and the second capture clock delay from the signal source to the clock end of the second capture register is adjusted; the third adjustable delay module is used to adjust the first data delay from the output end of the first transmit register to the data end of the first capture register, and is used to adjust the second data delay from the output end of the second transmit register to the data end of the second capture register; the output of the first capture register, the output of the second capture register, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine the hold time of the first capture register, thereby realizing register hold time detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0043] Figure 1 A schematic diagram of the structure of a holding time detection sensor provided in an embodiment of the present application Figure 1 ;

[0044] Figure 2 A schematic diagram of the structure of a ring oscillator with adjustable delay provided in an embodiment of the present application;

[0045] Figure 3 A schematic structural diagram of a submodule of an adjustable delay ring oscillator provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of the structure of a holding time detection sensor provided in an embodiment of the present application Figure 2 ;

[0047] Figure 5A schematic diagram of a flow chart of a hold time detection method provided in an embodiment of the present application;

[0048] Figure 6 A signal timing of a holding time detection sensor provided in an embodiment of the present application Figure 1 ;

[0049] Figure 7 A signal timing of a holding time detection sensor provided in an embodiment of the present application Figure 2 ;

[0050] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] In some related technologies, in order to test the hold time of registers in a chip, the chip base and substrate are disassembled so that the internal circuit structure of the chip can be observed through a transmission electron microscope (TEM) for testing. This testing method is destructive to the chip. To this end, the embodiments of the present application provide a hold time detection sensor and method that autonomously measures the hold time through the internal structure of the chip, and can then dynamically adjust the chip's peripheral logic to meet the operating timing, achieving accurate hold time detection without disassembling the chip.

[0053] The holding time detection sensor and method provided by the present application will be described in detail below through specific embodiments. It is understood that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0054] Figure 1 This is a schematic diagram of the structure of a holding time detection sensor provided in an embodiment of the present application. The holding time detection sensor is set in a chip. Figure 1As shown, the hold time detection sensor includes: a signal source 100, a first adjustable delay module 101, a second adjustable delay module 102, a third adjustable delay module 103, a first launch register 104, a first capture register 105, a second launch register 106, and a second capture register 107.

[0055] The signal source 100 is used to provide a rectangular pulse signal to the first adjustable delay module 101 , the second adjustable delay module 102 , the first transmitting register 104 , and the first transmitting register 104 .

[0056] The first adjustable delay module 101 is used to adjust a first transmit clock delay from the signal source 100 to the clock end of the first transmit register 104 , and to adjust a second transmit clock delay from the signal source 100 to the clock end of the second transmit register 106 .

[0057] The second adjustable delay module 102 is used to adjust a first capture clock delay from the signal source 100 to the clock end of the first capture register 105 , and to adjust a second capture clock delay from the signal source 100 to the clock end of the second capture register 107 .

[0058] The third adjustable delay module 103 is used to adjust a first data delay from the output of the first transmit register 104 to the data terminal of the first capture register 105 , and to adjust a second data delay from the output of the second transmit register 106 to the data terminal of the second capture register 107 .

[0059] The output of the first capture register 105 , the output of the second capture register 107 , the first transmit clock delay, the first capture clock delay, and the first data delay are used to determine the hold time of the first capture register 105 .

[0060] like Figure 1 As shown in FIG, the hold time detection sensor has two paths, wherein one path is composed of a signal source 100, a first adjustable delay module 101, a second adjustable delay module 102, a third adjustable delay module 103, a first transmit register 104, and a first capture register 105, and the other path is composed of a signal source 100, a first adjustable delay module 101, a second adjustable delay module 102, a third adjustable delay module 103, a second transmit register 106, and a second capture register 107. The first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 can be adjustable delay modules with the same or similar structures. Each adjustable delay module can have two submodules therein for adjusting the delays in the two paths, respectively.

[0061] For a path formed by the signal source 100, the first adjustable delay module 101, the second adjustable delay module 102, the third adjustable delay module 103, the first transmit register 104, and the first capture register 105, the first transmit clock delay from the signal source 100 to the clock end of the first transmit register 104, the first capture clock delay from the signal source 100 to the clock end of the first capture register 105, and the first data delay from the output end of the first transmit register 104 to the data end of the first capture register 105 are respectively adjusted by the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 to adjust the time during which the data in the first capture register 105 remains stable after the rising edge of the clock signal arrives. The time during which the data in the first capture register 105 remains stable after the rising edge of the clock signal arrives is the first data delay plus the first transmit clock delay minus the first capture clock delay.

[0062] For another path formed by the signal source 100, the first adjustable delay module 101, the second adjustable delay module 102, the third adjustable delay module 103, the second transmit register 106, and the second capture register 107, the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 respectively adjust a second transmit clock delay from the signal source 100 to the clock end of the second transmit register 106, a second capture clock delay from the signal source 100 to the clock end of the second capture register 107, and a second data delay from the output end of the second transmit register 106 to the data end of the second capture register 107, so as to adjust the time during which the data in the second capture register 107 remains stable after the rising edge of the clock signal. The time during which the data in the second capture register 107 remains stable after the rising edge of the clock signal arrives is the second data delay plus the second transmit clock delay minus the second capture clock delay.

[0063] In these two paths, if the time period during which the data in first capture register 105 and second capture register 107 remain stable after the rising edge of the clock signal both meets the corresponding hold time period, then the output of first capture register 105 and the output of second capture register 107 should be consistent. If the time period during which the data in one of first capture register 105 and second capture register 107 remain stable after the rising edge of the clock signal meets the corresponding hold time period, while the other does not meet the hold time period, then the output of first capture register 105 and the output of second capture register 107 are inconsistent.

[0064] Therefore, the hold time can be tested by adjusting the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103. For example, the time during which the data of the second capture register 107 remains stable after the rising edge of the clock signal arrives is always set to the maximum value, while the time during which the data of the first capture register 105 remains stable after the rising edge of the clock signal arrives is changed. When the output of the first capture register 105 and the output of the second capture register 107 are inconsistent, it can be determined that the time during which the data of the first capture register 105 remains stable after the rising edge of the clock signal arrives does not meet the hold time. By determining the critical point at which the output of the first capture register 105 and the output of the second capture register 107 are consistent and inconsistent, the hold time of the first capture register 105 can be determined. Correspondingly, the time during which the data of the first capture register 105 remains stable after the rising edge of the clock signal arrives is always the maximum value, while the time during which the data of the second capture register 107 remains stable after the rising edge of the clock signal arrives changes. When the output of the second capture register 107 is inconsistent with the output of the first capture register 105, it can be determined that the time during which the data of the second capture register 107 remains stable after the rising edge of the clock signal arrives does not meet the holding time. By determining the critical point where the output of the first capture register 105 and the output of the second capture register 107 are consistent and inconsistent, the holding time of the second capture register 107 can be determined.

[0065] The holding time detection sensor of the above embodiment will be further described below with reference to a circuit schematic diagram.

[0066] First, the first adjustable delay module 101, the second adjustable delay module 102 and the third adjustable delay module 103 are described. Optionally, the first adjustable delay module 101, the second adjustable delay module 102 and the third adjustable delay module 103 are all adjustable delay ring oscillators (RO). Figure 2 An adjustable delay ring oscillator is described.

[0067] like Figure 2 The figure shows an adjustable-delay ring oscillator, which includes a first ring oscillator 201, a first selector 202, a second ring oscillator 203, and a second selector 204. The first ring oscillator 201 and the second ring oscillator 203 are both ring-shaped devices formed by connecting the output and input ends of three inverters or an odd number of inverters end to end. Their output oscillates at a certain frequency to produce two levels. Figure 2The first ring oscillator 201 is connected end to end by a solid line, and the second ring oscillator 203 is connected end to end by a dotted line. The first ring oscillator 201 and the first selector 202 are referred to as a first submodule, and the second ring oscillator 203 and the second selector 204 are referred to as a second submodule. The first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 all include two submodules: the first submodule and the second submodule.

[0068] The input end of the first ring oscillator 201 is the first input end CLKA_IN of the adjustable delay ring oscillator. The first selector 202 is used to delay the signal of the first input end CLKA_IN by a first preset time and output it through the first output end SELA_OUT. The input end of the second ring oscillator 203 is the second input end CLKB_IN of the adjustable delay ring oscillator. The second selector 204 is used to delay the signal of the second input end by a second preset time and output it through the second output end SELB_OUT. The first preset time is adjustable through the first selector 202, and the second preset time is adjustable through the second selector 204. Figure 2 In the figure, only two lines are used to schematically represent the connection between the first ring oscillator 201 and the first selector 202, and two lines are used to represent the connection between the second ring oscillator 203 and the second selector 204. The two lines here are only for schematic representation of the connection relationship and do not represent the actual specific connection method of the lines. The connection between the first ring oscillator 201 and the first selector 202 and the connection between the second ring oscillator 203 and the second selector 204 can be found in the subsequent Figure 3 Description.

[0069] The first input terminal CLKA_IN is used to receive an excitation source and provide an initial input for the first ring oscillator 201. The second input terminal CLKB_IN is used to receive an excitation source and provide an initial input for the second ring oscillator 203. The first ring oscillator 201 also has an output terminal RO_A_CLK_OUT for outputting a waveform of the first ring oscillator 201, from which the oscillation frequency of the first ring oscillator 201 can be calculated. The second ring oscillator 203 also has an output terminal RO_B_CLK_OUT for outputting a waveform of the second ring oscillator 203, from which the oscillation frequency of the second ring oscillator 203 can be calculated.

[0070] The first ring oscillator 201 and the second ring oscillator 203 are both composed of N-order inverters, where N is a prime number and an odd number, such as Figure 2As shown in the figure, the first ring oscillator 201 and the second ring oscillator 203 are symmetrically arranged, which helps to offset the effects of harmonic oscillation and layout-dependent effects (LDE). The selector connected to the first input terminal CLKA_IN and the second input terminal CLKB_IN is used to control the type of output data of the first ring oscillator 201 and the second ring oscillator 203. For example, when the control signals RO_A_EN and RO_B_EN are high, the selector selects the output of the previous inverter as the valid input. In this state, the rectangular waves generated by the corresponding ring oscillators can be obtained from the output terminals RO_A_CLK_OUT and RO_B_CLK_OUT, respectively, and their oscillation frequencies can be calculated. When the control signals RO_A_EN and RO_B_EN are low, the selector selects the signals from the first input terminal CLKA_IN and the second input terminal CLKB_IN as the valid input, and the first output terminal SELA_OUT and the second output terminal SELB_OUT respectively output the corresponding delayed signals.

[0071] Combine Figure 3 The principle of implementing delay through the first ring oscillator 201 , the first selector 202 , the second ring oscillator 203 and the second selector 204 is described. Figure 3 Only one submodule is illustrated, taking the first ring oscillator 201 and the first selector 202 as an example, and the principle of the other submodule is the same.

[0072] like Figure 3 As shown, the input port SELA of the first selector 202 is 3 bits (3 bits are used in this embodiment for illustration, but it is not limited thereto and can be set to any number of bits according to actual application conditions), which can control 8 inputs and 1 output (the number of selections of the selector is related to the number of input port bits, that is, related to the port SELA). This means that there are 8 adjustable delay gears, and each value of the input port SELA corresponds to a delay gear, such as Figure 3As shown, the ring oscillator includes 15 inverters, each of which is a delay cell. The outputs of every two delay cells are connected to the first selector 202, meaning that the accuracy of each delay level is 2 delay cells (similarly, the accuracy of each delay level is not limited to 2 delay cells and can be any integer number of delay cells). For example, when the value of the 3-bit input port SELA[0:2] is 010, the first selector 202 outputs the information transmitted by port I_2 through the output port SELA_OUT. This causes the information transmitted from the input port to the output port to pass through 4 delay cells. This slows down the output waveform flipping by 4 times the delay of a single delay cell compared to when the value of port I_0, i.e., SELA[0:2], is 000. In this way, dynamic adjustment of the output delay is achieved through the input port SELA.

[0073] The hold time detection sensor is described in conjunction with the above-mentioned adjustable delay ring oscillator.

[0074] like Figure 4 As shown, the signal source 100 is respectively connected to the first input terminal CLKA_IN and the second input terminal CLKB_IN of the first adjustable delay module 101, the first output terminal SELA_OUT of the first adjustable delay module 101 is connected to the clock terminal of the first transmit register 104, and the second output terminal SELB_OUT of the first adjustable delay module 101 is connected to the clock terminal of the second transmit register 106.

[0075] The signal source 100 is connected to the first input terminal CLKA_IN and the second input terminal CLKB_IN of the second adjustable delay module 102 respectively, the first output terminal SELA_OUT of the second adjustable delay module 102 is connected to the clock terminal of the first capture register 105, and the second output terminal SELB_OUT of the second adjustable delay module 102 is connected to the clock terminal of the second capture register 107.

[0076] An output terminal of the first transmitting register 104 is connected to a first input terminal CLKA_IN of the third adjustable delay module 103 , and a first output terminal SELA_OUT of the third adjustable delay module 103 is connected to a data terminal of the first capturing register 105 .

[0077] An output terminal of the second transmitting register 106 is connected to a second input terminal CLKB_IN of the third adjustable delay module 103 , and a second output terminal SELB_OUT of the third adjustable delay module 103 is connected to a data terminal of the second capturing register 107 .

[0078] Optionally, the hold time detection sensor further includes an exclusive OR gate XOR.

[0079] The output of the first capture register 105 and the output of the second capture register 107 are connected to an XOR gate. The output of the XOR gate, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine the hold time of the first capture register 105.

[0080] Optionally, the holding time detection sensor further includes: a first register 401 and a second register 402 .

[0081] The output end of the XOR gate is connected to the data end of the first register 401, the clock end of the first register 401 is connected to the signal source 100, the output end of the first register 401 is connected to the clock end of the second register 402, and the data end of the second register 402 is connected to a high level or ground.

[0082] The output of the second register 402 , the first transmit clock delay, the first capture clock delay, and the first data delay are used to determine the hold time of the first capture register 105 .

[0083] Optionally, the holding time detection sensor further includes: a third register 403 .

[0084] The clock terminal of the third register 403 is connected to the signal source 100 , the output terminal of the third register 403 is connected to the data terminal of the third register 403 through an inverter, and the output terminal of the third register 403 is connected to the data terminal of the first transmitting register 104 and the data terminal of the second transmitting register 106 .

[0085] Optionally, for the first adjustable delay module 101 and the second adjustable delay module 102 , a DCCK type standard cell may be selected as the delay unit, and for the third adjustable delay module 13 , a DEL type standard cell may be selected as the delay unit.

[0086] The signal from signal source 100 is output to the clock terminal of first capture register 105 through the first submodule of first adjustable delay module 101, then to the clock terminal of second capture register 107 through the second submodule of first adjustable delay module 101, then to the clock terminal of first capture register 105 through the first submodule of second adjustable delay module 102, and finally to the clock terminal of second capture register 107 through the second submodule of second adjustable delay module 102. The output of first transmit register 104 is output to the data terminal of first capture register 105 through the first submodule of third adjustable delay module 103, and the output of second transmit register 106 is output to the data terminal of second capture register 107 through the second submodule of third adjustable delay module 103. The delay duration of each submodule can be independently adjusted via its respective input ports SELA and SELB.

[0087] The output of the first capture register 105 and the output of the second capture register 107 are connected to an XOR gate. When the output of the first capture register 105 and the output of the second capture register 107 are consistent, the output of the XOR gate is 0. When the output of the first capture register 105 and the output of the second capture register 107 are inconsistent, the output of the XOR gate is 1. The first register 401 and the second register 402 form a deglitching circuit to remove the glitch from the XOR value signal output by the XOR gate and output it as a CFAIL signal to indicate pass or fail, where a pass means that the output of the first capture register 105 and the output of the second capture register 107 are consistent, and a fail means that the output of the first capture register 105 and the output of the second capture register 107 are inconsistent.

[0088] The following further explains how to determine the holding time.

[0089] Figure 5 This is a flow chart of a holding time detection method provided in an embodiment of the present application. This method is applied to the aforementioned holding time detection sensor, such as Figure 5 As shown, the method includes:

[0090] S501: Set the second transmit clock delay, the second capture clock delay, and the second data delay to maximum values.

[0091] 502. Traverse all value combinations of the first transmit clock delay, the first capture clock delay, and the first data delay, and respectively obtain the XOR value of the output of the first capture register 105 and the output of the second capture register 107 corresponding to each value combination.

[0092] S503 : Determine the holding time of the first capture register 105 according to the XOR value and the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to the XOR value.

[0093] Similar to the above, the first transmit clock delay, the first capture clock delay, and the first data delay are set to maximum values; all value combinations of the second transmit clock delay, the second capture clock delay, and the second data delay are traversed, and the XOR value of the output of the first capture register 105 and the output of the second capture register 107 corresponding to each value combination is obtained respectively; the hold time of the second capture register 107 is determined according to the XOR value and the second transmit clock delay, the second capture clock delay, and the second data delay corresponding to the XOR value.

[0094] Before this, the delay of one delay unit in two submodules of each of the first adjustable delay module 101 , the second adjustable delay module 102 and the third adjustable delay module 103 may be predetermined.

[0095] Set the control signals RO_A_EN and RO_B_EN in each submodule of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 to 1, and test the frequencies of the output signals RO_A_CLK_OUT and RO_B_CLK_OUT of the two submodules in each of the above adjustable delay modules, as shown in FIG. Figure 6 As shown, Figure 6 The 1, 2, and 3 in the signal names correspond to the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103, respectively. The delay of a delay unit in the submodule is then determined in combination with the number of stages (the number of inverters) of each submodule. Afterwards, RO_A_EN and RO_B_EN are set to 0, and the SELA and SELB ports of each submodule in the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 are set to the maximum value. Afterwards, the SELB ports of the second submodules of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 are kept at the maximum value, and the value combinations of the SELA ports of the first submodules of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 are traversed, as shown in FIG. Figure 7 As shown, Figure 7 1, 2, and 3 in the signal name correspond to the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103, respectively. All value combinations of the first transmit clock delay, the first capture clock delay, and the first data delay are traversed. After each value combination of the SELA port of the first submodule of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 is set, RESETB is reset. RESETB is an asynchronous reset signal used to initialize each module, thereby obtaining an output result CFAIL corresponding to the exclusive OR value of the output of the first capture register 105 and the output of the second capture register 107 corresponding to each value combination.

[0096] For example, taking the SELA and SELB ports as 3 bits as an example, the SELB port of the second submodule of the first adjustable delay module 101, the second adjustable delay module 102 and the third adjustable delay module 103 is kept at 7, and the value combination of the SELA port of the first submodule of the first adjustable delay module 101, the second adjustable delay module 102 and the third adjustable delay module 103 is traversed. The value of each SELA port traverses 0-7. For example, the SELA port of the first submodule of the first adjustable delay module 101 is 7, and the SELA port of the first submodule of the second adjustable delay module 102 is 0. The SELA port of the first submodule of the third adjustable delay module 103 takes the value of 7. Then, the SELA port of the first submodule of the first adjustable delay module 101 takes the value of 7, the SELA port of the first submodule of the second adjustable delay module 102 takes the value of 7, and the SELA port of the first submodule of the third adjustable delay module 103 takes the value of 6, and so on, until the SELA port of the first submodule of the first adjustable delay module 101 takes the value of 7, the SELA port of the first submodule of the second adjustable delay module 102 takes the value of 7, and the SELA port of the first submodule of the third adjustable delay module 103 takes the value of 0. Afterwards, the SELA port value of the first submodule of the first adjustable delay module 101 is 7, the SELA port value of the first submodule of the second adjustable delay module 102 is 6, and the SELA port value of the first submodule of the third adjustable delay module 103 is 7. Afterwards, the SELA port value of the first submodule of the first adjustable delay module 101 is 7, the SELA port value of the first submodule of the second adjustable delay module 102 is 6, and the SELA port value of the first submodule of the third adjustable delay module 103 is 6, and so on, until the SELA port value of the first submodule of the first adjustable delay module 101 is 7, the SELA port value of the first submodule of the second adjustable delay module 102 is 6, and the SELA port value of the first submodule of the third adjustable delay module 103 is 0. This process is repeated in this way until, when the SELA port value of the first submodule of the first adjustable delay module 101 is 7, the SELA port values ​​of the first submodule of the second adjustable delay module 102 and the SELA port values ​​of the first submodule of the third adjustable delay module 103 are all traversed. Then, the SELA port value of the first submodule of the first adjustable delay module 101 is 6 until it reaches 0. It should be noted that the traversal order of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103 can be reversed. For example, according to the same method as above, the traversal order can be performed in the order of the second adjustable delay module 102, the first adjustable delay module 101, and the third adjustable delay module 103.

[0097] After 8^3=512 traversals, 512 XOR values ​​and the first transmit clock delay, first capture clock delay, and first data delay corresponding to each XOR value are obtained. The first transmit clock delay corresponding to each XOR value is the value of the SELA port of the first submodule of the first adjustable delay module 101 multiplied by the precision of each delay gear and then multiplied by the delay of one delay unit. The first capture clock delay is the value of the SELA port of the first submodule of the third adjustable delay module 103 multiplied by the precision of each delay gear and then multiplied by the delay of one delay unit. The first data delay is the value of the SELA port of the first submodule of the second adjustable delay module 102 multiplied by the precision of each delay gear and then multiplied by the delay of one delay unit.

[0098] Optionally, the XOR values ​​are sorted in the order of descending traversal of the first transmission clock delay, the first capture clock delay and the first data delay to determine at least one target XOR value adjacent to the XOR value with a value of 1 and not 1; and the hold time is determined based on the first transmission clock delay, the first capture clock delay and the first data delay corresponding to each of the at least one target XOR value.

[0099] For example, the following Table 1 shows a portion of the sorting results of the XOR value, namely CFAIL:

[0100] Table 1

[0101]

[0102] Among them, SELA1, SELA2, and SELA3 represent the values ​​of the SELA ports of the first submodule of the first adjustable delay module 101, the second adjustable delay module 102, and the third adjustable delay module 103, respectively. For one path in the hold time detection sensor (the path where the first capture register 105 is located), there are a total of eight results similar to Table 1, which respectively count the results when the SELA port of the first submodule of the third adjustable delay module is set to 0 to 7. The other path (the path where the second capture register 107 is located) is similar. In Table 1, PASS represents an XOR value of 0, and FAIL represents an XOR value of 1. The Pass at the intersection of Pass and Fail is selected as the target XOR value for hold time calculation. For example, the three PASS at the intersection of Pass and Fail in Table 1 are the target XOR values. The target XOR values ​​are determined in the same way for the other tables. The first data delay corresponding to each target XOR value is added to the first transmit clock delay and then subtracted from the first capture clock delay. The minimum value of the obtained results is determined as the hold time. That is, it is calculated according to the following formula:

[0103]

[0104] in, Delay is the first data delay. CKLA_RO Delay is the first transmission clock delay, CKCA_RO Delay the first capture clock; calculate for each target XOR value according to the above formula, and determine the minimum value in the results as the hold time.

[0105] The hold time detection sensor and method of the embodiments of the present application dynamically adjust the clock delay and data delay of the register through a wake-up oscillator with adjustable delay to obtain a controllable hysteresis output, and then measure the hold time of the register by traversing all clock delays and data delays without disassembling the chip, thereby achieving non-destructive and accurate hold time detection.

[0106] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 8 As shown, the electronic device 800 includes: a memory 801, a processor 802, and a transceiver 803. The memory 801 and the processor 802 communicate with each other. Exemplarily, the memory 801, the processor 802, and the transceiver 803 can communicate via a communication bus 804. The memory 801 is used to store a computer program, and the processor 802 executes the computer program to implement the above-mentioned communication method. For example, the processor 802 executes the relevant steps of the above-mentioned method embodiment.

[0107] Optionally, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), or application-specific integrated circuits (ASIC). A general-purpose processor may be a microprocessor or any conventional processor. The steps in the method embodiments disclosed in this application may be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.

[0108] An embodiment of the present application also provides a chip including the above-mentioned holding time detection sensor.

[0109] An embodiment of the present application also provides a chip module, including the above chip.

[0110] An embodiment of the present application further provides a computer-readable storage medium, comprising: a computer program stored thereon, which implements the method in any of the above method embodiments when the program is executed by a processor.

[0111] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method in any of the above method embodiments when the computer program is executed by a processor.

[0112] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above-mentioned method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof.

[0113] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0116] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations.

[0117] In this application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In this application, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

Claims

1. A holding time detection sensor, characterized in that: include: Signal source, first adjustable delay module, second adjustable delay module, third adjustable delay module, first transmitting register, first capturing register, second transmitting register, second capturing register; The signal source is used to provide a pulse signal to the first adjustable delay module, the second adjustable delay module, the first transmitting register, and the first transmitting register; The first adjustable delay module is used to adjust a first transmit clock delay from the signal source to a clock end of the first transmit register, and is used to adjust a second transmit clock delay from the signal source to a clock end of the second transmit register; The second adjustable delay module is used to adjust a first capture clock delay from the signal source to the clock end of the first capture register, and is used to adjust a second capture clock delay from the signal source to the clock end of the second capture register; The third adjustable delay module is used to adjust a first data delay from the output end of the first transmit register to the data end of the first capture register, and is used to adjust a second data delay from the output end of the second transmit register to the data end of the second capture register; The output of the first capture register, the output of the second capture register, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine a hold time of the first capture register.

2. The holding time detection sensor according to claim 1, characterized in that: The first adjustable delay module, the second adjustable delay module and the third adjustable delay module are all adjustable delay ring oscillators; The adjustable delay ring oscillator includes a first ring oscillator, a first selector, a second ring oscillator and a second selector; The input end of the first ring oscillator is the first input end of the adjustable delay ring oscillator, the first selector is used to delay the signal of the first input end by a first preset time and then output it through the first output end, the input end of the second ring oscillator is the second input end of the adjustable delay ring oscillator, the second selector is used to delay the signal of the second input end by a second preset time and then output it through the second output end, and the first preset time and the second preset time are both adjustable.

3. The holding time detection sensor according to claim 2, characterized in that: The signal source is connected to the first input end and the second input end of the first adjustable delay module respectively, the first output end of the first adjustable delay module is connected to the clock end of the first transmitting register, and the second output end of the first adjustable delay module is connected to the clock end of the second transmitting register.

4. The holding time detection sensor according to claim 2, wherein: The signal source is connected to the first input end and the second input end of the second adjustable delay module respectively, the first output end of the second adjustable delay module is connected to the clock end of the first capture register, and the second output end of the second adjustable delay module is connected to the clock end of the second capture register.

5. The holding time detection sensor according to claim 2, wherein: The output end of the first transmitting register is connected to the first input end of the third adjustable delay module, and the first output end of the third adjustable delay module is connected to the data end of the first capturing register; The output end of the second transmitting register is connected to the second input end of the third adjustable delay module, and the second output end of the third adjustable delay module is connected to the data end of the second capturing register.

6. The holding time detection sensor according to any one of claims 1 to 5, characterized in that: Also includes: XOR gate; The output end of the first capture register and the output end of the second capture register are connected to the XOR gate, and the output of the XOR gate, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine the hold time of the first capture register.

7. The holding time detection sensor according to claim 6, characterized in that: Also includes: First register and second register; The output end of the XOR gate is connected to the data end of the first register, the clock end of the first register is connected to the signal source, the output end of the first register is connected to the clock end of the second register, and the data end of the second register is connected to a high level or ground; The output of the second register, the first transmit clock delay, the first capture clock delay and the first data delay are used to determine a hold time of the first capture register.

8. The holding time detection sensor according to any one of claims 1 to 5, characterized in that: Also includes: The third register; The clock end of the third register is connected to the signal source, the output end of the third register is connected to the data end of the third register through an inverter, and the output end of the third register is connected to the data end of the first transmitting register and the data end of the second transmitting register.

9. A holding time detection method, characterized in that: Applied to the holding time detection sensor according to any one of claims 1 to 8, the method comprises: Setting the second transmit clock delay, the second capture clock delay, and the second data delay to maximum values; Traversing all value combinations of the first transmit clock delay, the first capture clock delay, and the first data delay, and respectively obtaining an exclusive OR value of the output of the first capture register and the output of the second capture register corresponding to each value combination; The holding time of the first capture register is determined according to the XOR value and the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to the XOR value.

10. The method according to claim 9, characterized in that The determining the hold time according to the XOR value and the first transmit clock delay, the first capture clock delay, and the first data delay corresponding to the XOR value includes: Sort the XOR values ​​in descending order of the first transmit clock delay, the first capture clock delay, and the first data delay, and determine at least one target XOR value that is adjacent to the XOR value having a value of 1 and is not 1; The hold time is determined according to a first transmit clock delay, a first capture clock delay, and a first data delay corresponding to each of the at least one target XOR value.

11. The method according to claim 10, characterized in that The determining the hold time according to the first transmit clock delay, the first capture clock delay, and the first data delay respectively corresponding to the at least one target XOR value includes: The first data delay corresponding to each of the at least one target XOR values ​​is added to the first transmission clock delay and then subtracted from the first capture clock delay, and the minimum value of the obtained results is determined as the hold time.

12. A chip, characterized in that: The device comprises a holding time detection sensor as claimed in any one of claims 1 to 8.

13. A chip module, characterized in that: Comprising the chip as claimed in claim 12.

14. An electronic device, characterized in that: include: memory, processors, and transceivers; The memory is used to store computer programs; The processor is configured to implement the method according to any one of claims 9 to 11 when the computer program is executed.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 9 to 11 is implemented.

16. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 9 to 11 when being executed by a processor.

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