A complementary bootstrap switch based on a negative voltage bootstrap capacitor and its working method

Abstract

The present invention relates to a complementary bootstrap switch based on a negative voltage bootstrap capacitor and a working method, including an NMOS sampling switch control part and a PMOS sampling switch control part, wherein: The NMOS sampling switch control part includes a first NMOS transistor and a first PMOS transistor. The first NMOS transistor includes M3, M4, M5, M6, M7, M9, M10 and M13, and the first PMOS transistor includes M1, M2, M8, M11 and M12; The switch of the present invention is composed of an NMOS transistor and a PMOS transistor, reducing the channel charge injection effect; A bootstrap capacitor is introduced at the key node to reduce the aspect ratio of the MOS transistor, thereby reducing the parasitic capacitance. The performance of the bootstrap switch is improved at high-speed sampling frequencies.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly relates to a complementary bootstrap switch based on a negative voltage bootstrap capacitor and a working method thereof. Background Art

[0002] An analog-to-digital converter is a bridge for converting an analog signal into a digital signal, and a sample-and-hold circuit is an important part of the analog-to-digital converter. The function of the bootstrap switch is to sample and hold an analog signal periodically, and the speed and accuracy of the bootstrap switch are the basis for subsequent other analog circuits to achieve functions.

[0003] There are many non-ideal factors in the bootstrap circuit, such as: channel charge injection, clock feedthrough, parasitic capacitance in the sampling circuit, non-fixed on-resistance, etc. The traditional bootstrap switch is composed of only an NMOS transistor or a PMOS transistor as a sampling switch. When the source of the sampling switch is connected to the input signal, this structure makes the gate-source voltage of the sampling switch remain unchanged during the sampling stage, but other non-ideal factors such as channel charge injection and parasitic capacitance still affect the performance of the bootstrap switch. In addition, the sampling switch of the traditional structure bootstrap switch cannot achieve a fixed gate-source voltage when the drain is connected to the input signal V IN connection, resulting in a large change in the on-resistance. Therefore, there is an urgent need for a complementary bootstrap switch based on a negative voltage bootstrap capacitor. By using complementary NMOS and PMOS to jointly form a sampling switch, when the drain of the sampling switch is connected to V IN connection, the change range of the on-resistance is reduced. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention provides a complementary bootstrap switch based on a negative voltage bootstrap capacitor. The sampling switch is composed of an NMOS transistor and a PMOS transistor, reducing the channel charge injection effect; a bootstrap capacitor is introduced at a key node, reducing the aspect ratio of the MOS transistor, and further reducing the parasitic capacitance, thus improving the performance of the bootstrap switch at a high sampling frequency.

[0005] The technical solution of the present invention is as follows:

[0006] A complementary bootstrap switch based on a negative voltage bootstrap capacitor includes an NMOS sampling switch control part and a PMOS sampling switch control part, wherein:

[0007] The NMOS sampling switch control part includes a first NMOS transistor and a first PMOS transistor. The first NMOS transistor includes M3, M4, M5, M6, M7, M9, M10 and M13, and the first PMOS transistor includes M1, M2, M8, M11 and M12;

[0008] Among them, the sources of M1, M8, and M12 and the gate of M3 are respectively connected to the power supply voltage V DD , the drain of M4 and the sources of M5 and M13 are respectively grounded to V SS ; the gates of M8, M9, M11, M12, and M13 are respectively connected to the sampling clock CLK; the gates of M4 and M5 are respectively connected to the sampling clock CLKB, the drain of M1 is connected to the source of M2, the drains of M2 and the source of M3 are respectively connected to the gates of M1, M6, and M7, the drain of M3 is connected to the source of M4, the drain of M5 is connected to the source of M6, the drains of M6 and the source of M7 are respectively connected to the input signal V IN connection, the drain of M7 is connected to the output signal V OUT connection;

[0009] The PMOS sampling switch control part includes a second PMOS transistor and a second NMOS transistor. The second PMOS transistor includes M16, M17, M18, M19, M20, M22, M23, and M26, and the second NMOS transistor includes M14, M15, M21, M24, and M25;

[0010] Among them, the sources of M14, M21, and M25 and the gate of M16 are respectively grounded to VSS, the gates of M21, M22, M24, M25, and M26 are respectively connected to the sampling clock CLKB, the drain of M14 is connected to the source of M15, the drains of M15 and the source of M16 are respectively connected to the gates of M14, M19, and M20, the drain of M16 is connected to the source of M17, the drain of M5 is connected to the source of M19, the drains of M19 and the source of M20 are respectively connected to the input signal V IN connection, the drain of M20 is connected to the output signal V OUT connection.

[0011] Further, the NMOS sampling switch control part further includes that the drain of M8 and the source of M9 are respectively connected to the gates of M2 and M10, the drain of M9 is respectively connected to the sources of M10 and M11, the drains of M10 and M11 are respectively connected to the input signal V IN connection, and the drains of M12 and M13 are connected.

[0012] Further, the NMOS sampling switch control part further includes a first capacitor. The first capacitor includes C1 and C2. Among them, the upper plate of C1 is connected to the drain of M1, the lower plate of C1 is connected to the drain of M5, the upper plate of C2 is connected to the source of M11, the lower plate of C2 is connected to the drain of M13, the substrates of M1 and M2 are respectively connected to the drain of M1, and the substrate and the source of M10 are connected.

[0013] Further, in the PMOS sampling switch control section, the drain of M21 and the source of M22 are respectively connected to the gates of M15 and M23, the drain of M22 is respectively connected to the sources of M23 and M24, and the drains of M23 and M24 are respectively connected to the input signal V IN connection, and the drains of M25 and M26 are connected.

[0014] Further, the PMOS sampling switch control section further includes a second capacitor, the second capacitor includes C3 and C4, the upper plate of C3 is connected to the drain of M14, the lower plate of C3 is connected to the drain of M18, the upper plate of C4 is connected to the source of M23, the lower plate of C4 is connected to the drain of M26, the substrates of M14 and M15 are respectively connected to the drain of M14, and the substrate of M23 is connected to the source.

[0015] A complementary bootstrap switch working method based on a negative voltage bootstrap capacitor, including:

[0016] By setting the sampling clocks CLK and CLKB as opposite signals to control the on / off of the complementary bootstrap switch, specifically including:

[0017] When the bootstrap switch is in the hold stage, CLK is at a low level and CLKB is at a high level;

[0018] For the NMOS sampling switch control section: M1, M3, M4, and M5 are turned on, M2, M6, and M7 are turned off, the potential of the upper plate of C1 is V DD , and the potential of the lower plate of C1 is V SS ; M8, M10, M11, and M12 are turned on, M9 and M13 are turned off, the potential of the upper plate of C2 is V IN , and the potential of the lower plate of C2 is V DD ;

[0019] For the PMOS sampling switch control section: M14, M16, M17, and M18 are turned on, M15, M19, and M20 are turned off, the potential of the upper plate of C3 is V SS , and the potential of the lower plate of C3 is V DD ; M21, M23, M24, and M25 are turned on, M22 and M26 are turned off, the potential of the upper plate of C4 is V IN , and the potential of the lower plate of C4 is V SS .

[0020] Further, when the bootstrap switch is in the sampling stage, CLK is at a high level and CLKB is at a low level;

[0021] For the NMOS sampling switch control section: M2, M6, and M7 are turned on, M1, M3, M4, and M5 are turned off, the potential of the upper plate of C1 is V DD +V IN, the potential of the lower plate is V IN ; M9 and M13 are turned on, M8, M10, M11, and M12 are turned off, and the potential of the upper plate of C2 is V IN -V DD , the potential of the lower plate is V SS ;

[0022] For the PMOS sampling switch control part: M15, M19, and M20 are turned on, M14, M16, M17, and M18 are turned off, and the potential of the upper plate of C3 is V IN -V DD , the potential of the lower plate is V IN ; M22 and M26 are turned on, M21, M23, M24, and M25 are turned off, and the potential of the upper plate of C4 is V IN +V DD , the potential of the lower plate is V DD .

[0023] Furthermore, when the bootstrap switch operates in the sampling stage, the gate-source voltage V of M7 GS7 =V DD , the gate-source voltage V of M20 SG20 =V DD , the gate-source voltage V of M2 SG2 =2V DD , the gate-source voltage V of M15 GS15 =2V DD , and the MOS transistors at the key parasitic nodes have relatively high gate-source voltages.

[0024] Furthermore, when the bootstrap switch operates in the sampling stage, the on-resistance of M2 is:

[0025]

[0026] where μ p is the mobility of holes, C ox is the gate oxide capacitance per unit area, W and L are the channel width and length of M2, and V TH is the threshold voltage.

[0027] Furthermore, when the bootstrap switch operates in the sampling stage, the on-resistance of M2 remains unchanged, the gate-source voltage of M2 increases while the aspect ratio decreases, thereby reducing the parasitic capacitance brought by the transistor and reducing the influence of charge redistribution on the gate potential of the transistor.

[0028] The beneficial effects of the present invention are as follows:

[0029] 1. The present invention uses complementary NMOS transistors and PMOS transistors as sampling switches. When the bootstrap switch state changes, some electrons and holes will cancel each other out, weakening the channel charge injection effect.

[0030] 2. Parasitic capacitances exist at key nodes 1 and 2, which will perform charge distribution with the charges on the upper plates of C1 and C3, causing the potentials of the upper plates of C1 and C3 to decrease. The present invention raises the gate-source voltages of M2 and M15 to approximately 2V by introducing bootstrap capacitors C2 and C4 DD , when the on-resistances of M2 and M15 remain unchanged, the present invention raises the gate-source voltage, thereby reducing the aspect ratio of the transistor, further reducing the parasitic capacitance brought by the MOS transistor, and improving the performance of the bootstrap switch. Brief Description of the Drawings

[0031] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application.

[0032] Figure 1 is a schematic circuit diagram of a complementary bootstrap switch based on a negative voltage bootstrap capacitor according to the present invention;

[0033] Figure 2 is a schematic diagram of the holding stage of a complementary bootstrap switch based on a negative voltage bootstrap capacitor according to the present invention;

[0034] Figure 3 is a schematic diagram of the sampling stage of a complementary bootstrap switch based on a negative voltage bootstrap capacitor according to the present invention;

[0035] Figure 4 is a schematic diagram of the transient simulation of the gate-source voltage of M2 according to the present invention;

[0036] Figure 5 is a schematic diagram of the fast Fourier transform of a complementary bootstrap switch based on a negative voltage bootstrap capacitor in an embodiment of the present invention. Detailed Embodiments

[0037] The present invention will be further limited below in conjunction with the accompanying drawings of the specification and embodiments, but not limited thereto.

[0038] Embodiment 1

[0039] As Figure 1 shown, this embodiment provides a complementary bootstrap switch based on a negative voltage bootstrap capacitor, including an NMOS sampling switch control part and a PMOS sampling switch control part.

[0040] The NMOS sampling switch control part includes first NMOS transistors M3, M4, M5, M6, M7, M9, M10, M13, and first PMOS transistors M1, M2, M8, M11, M12. The sources of M1, M8, M12 and the gate of M3 are connected to the power supply voltage V DD , the drain of M4 and the sources of M5, M13 are grounded to VSS The gates of M8, M9, M11, M12, and M13 are connected to the sampling clock CLK. The gates of M4 and M5 are connected to the sampling clock CLKB. The drain of M1 is connected to the source of M2. The drain of M2, the source of M3, and the gates of M1, M6, and M7 are connected. The drain of M3 is connected to the source of M4. The drain of M5 is connected to the source of M6. The drain of M6, the source of M7, and the input signal V IN are connected. The drain of M7 and the output signal V OUT are connected. The drain of M8, the source of M9, and the gates of M2 and M10 are connected. The drain of M9 is connected to the sources of M10 and M11. The drains of M10 and M11 and the input signal V IN are connected. The drains of M12 and M13 are connected. The upper plate of capacitor C1 is connected to the drain of M1, and the lower plate is connected to the drain of M5. The upper plate of capacitor C2 is connected to the source of M11, and the lower plate is connected to the drain of M13. C P1 and C P2 are parasitic capacitances to ground. The substrates of M1 and M2 are connected to the drain of M1. The substrate of M10 is connected to the source, and the substrates of the remaining NMOS transistors are grounded to V SS , and the substrates of the PMOS transistors are connected to the power supply voltage V DD .

[0041] The PMOS sampling switch control section includes second PMOS transistors M16, M17, M18, M19, M20, M22, M23, M26, and second NMOS transistors M14, M15, M21, M24, M25. The sources of M14, M21, and M25 and the gate of M16 are grounded to V SS , the gates of M21, M22, M24, M25, and M26 are connected to the sampling clock CLKB. The drain of M14 is connected to the source of M15. The drain of M15, the source of M16, and the gates of M14, M19, and M20 are connected. The drain of M16 is connected to the source of M17. The drain of M5 is connected to the source of M19. The drain of M19, the source of M20, and the input signal V IN are connected. The drain of M20 and the output signal V OUT are connected. The drain of M21, the source of M22, and the gates of M15 and M23 are connected. The drain of M22 is connected to the sources of M23 and M24. The drains of M23 and M24 and the input signal V IN are connected. The drains of M25 and M26 are connected. The upper plate of capacitor C3 is connected to the drain of M14, and the lower plate is connected to the drain of M18. The upper plate of capacitor C4 is connected to the source of M23, and the lower plate is connected to the drain of M26. C P3 and C P4 are parasitic capacitances to ground. The substrates of M14 and M15 are connected to the drain of M14. The substrate of M23 is connected to the source, and the substrates of the remaining NMOS transistors are grounded to VSS The PMOS substrate is connected to the power supply voltage V DD .

[0042] Embodiment 2

[0043] As Figures 2-3 shown, this embodiment provides a working method for a complementary bootstrap switch based on a negative voltage bootstrap capacitor, which specifically includes:

[0044] Set the sampling clocks CLK and CLKB as opposite signals, and the load capacitor is C L .

[0045] Among them, the threshold voltage of the NMOS is positive, and the threshold voltage of the PMOS is negative. CLK and CLKB are used as control signals to control the on and off of the NMOS and PMOS. Only relying on the CLK signal alone cannot achieve the on and off states of the MOS transistors required for the bootstrap switch. Therefore, opposite CLK and CLKB signals are required to jointly control to achieve the circuit connection method required for the normal operation of the bootstrap switch.

[0046] Refer to Figure 2 , when the bootstrap switch is working in the hold stage, CLK is at a low level and CLKB is at a high level.

[0047] For the NMOS sampling switch control part: M1, M3, M4, M5 are turned on, M2, M6, M7 are turned off, the potential of the upper plate of C1 is V DD , the potential of the lower plate of C1 is V SS ; M8, M10, M11, M12 are turned on, M9, M13 are turned off, the potential of the upper plate of C2 is V IN , the potential of the lower plate of C2 is V DD .

[0048] For the PMOS sampling switch control part: M14, M16, M17, M18 are turned on, M15, M19, M20 are turned off, the potential of the upper plate of C3 is V SS , the potential of the lower plate of C3 is V DD ; M21, M23, M24, M25 are turned on, M22, M26 are turned off, the potential of the upper plate of C4 is V IN , the potential of the lower plate of C4 is V SS .

[0049] Refer to Figure 3 , when the bootstrap switch is working in the sampling stage, CLK is at a high level and CLKB is at a low level.

[0050] For the NMOS sampling switch control part: M2, M6, M7 are turned on, M1, M3, M4, M5 are turned off, the potential of the upper plate of C1 is V DD +V IN , the potential of the lower plate is VIN ; M9 and M13 are turned on, M8, M10, M11, and M12 are turned off, and the potential of the upper plate of C2 is V IN -V DD , and the potential of the lower plate is V SS .

[0051] For the PMOS sampling switch control part: M15, M19, and M20 are turned on, M14, M16, M17, and M18 are turned off, and the potential of the upper plate of C3 is V IN -V DD , and the potential of the lower plate is V IN ; M22 and M26 are turned on, M21, M23, M24, and M25 are turned off, and the potential of the upper plate of C4 is V IN +V DD , and the potential of the lower plate is V DD .

[0052] The gate-source voltage V of M7 during the sampling phase GS7 =(V DD +V IN )-V IN =V DD , the gate-source voltage V of M20 SG20 =V IN (V IN -V DD )=V DD , the gate-source voltage remains constant, and the gate-source voltage V of M2 SG2 =(V IN +V DD )-(V IN -V DD )=2V DD , the MOS transistors at the key parasitic nodes have relatively high gate-source voltages, and the gate-source voltage V of M15 GS15 =(V IN +V DD )-(V IN -V DD )=2V DD .

[0053] Embodiment 3

[0054] In this embodiment, the Cadence Virtuoso EDA tool is used for circuit design and simulation, and the 0.18μm CMOS process is adopted. The circuit schematic diagram is as shown in Figure 1 , and it includes an NMOS sampling switch control part and a PMOS sampling switch control part.

[0055] The main parameter settings of the present invention are as follows:

[0056] Power supply voltage V DD= 1.8V, sampling frequency F S (CLK signal) = 50MHz, input signal frequency F in = 378.418KHz, input signal V IN has a voltage range of 0 - 1.8V, load capacitance C L is 1pF.

[0057] The on-resistance of M2 is as shown in Equation (1):

[0058]

[0059] where, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, W and L are the channel width and length of M2, V TH is the threshold voltage. The transient simulation result of the gate-source voltage of M2 is as Figure 4 shown. It can be seen from the simulation result that the gate-source voltage of M2 is close to 3.6V (2V DD ) during the sampling phase. According to Equation (1), when the on-resistance remains unchanged, an increase in V SG2 results in a decrease in , thereby reducing the parasitic capacitance of Node 1 and ultimately reducing the impact of charge redistribution on the gate potential of M7. The method of reducing the parasitic capacitance of Node 2 for the gate-source voltage of M15 is similar to that of M2.

[0060] Perform a frequency-domain simulation on the schematic diagram shown in Figure 1 , sample 4096 points, and the final FFT result is as Figure 5 shown. It can be seen that at a sampling frequency of 50MHz, the Effective Number of Bits (ENOB) of the bootstrap switch reaches 16.5 bits, and the Signal to Noise and Distortion Ratio (SNDR) and Spurs Free Dynamic Range (SFDR) reach 101.11dB and 101.83dB respectively, demonstrating that the bootstrap switch structure proposed in the present invention has good performance at high sampling rates.

[0061] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program code.

[0062] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or in multiple blocks.

[0063] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0064] Although the specific implementation manners of the present invention have been described above in conjunction with the accompanying drawings, it is not a limitation on the protection scope of the present invention. Those skilled in the art should understand that, based on the technical solutions of the present invention, various modifications or deformations that can be made without creative efforts by those skilled in the art are still within the protection scope of the present invention.

Claims

1. A complementary bootstrap switch based on a negative voltage bootstrap capacitor, characterized in that, It includes an NMOS sampling switch control part and a PMOS sampling switch control part, where: The NMOS sampling switch control part includes a first NMOS transistor and a first PMOS transistor. The first NMOS transistor includes M3, M4, M5, M6, M7, M9, M10, and M13, and the first PMOS transistor includes M1, M2, M8, M11, and M12; Among them, the sources of M1, M8, and M12 and the gate of M3 are respectively connected to the power supply voltage V DD , the drain of M4 and the sources of M5 and M13 are respectively grounded to V SS ; the gates of M8, M9, M11, M12, and M13 are respectively connected to the sampling clock CLK; the gates of M4 and M5 are respectively connected to the sampling clock CLKB, the drain of M1 is connected to the source of M2, the drain of M2 and the source of M3 are respectively connected to the gates of M1, M6, and M7, the drain of M3 is connected to the source of M4, the drain of M5 is connected to the source of M6, the drains of M6 and the sources of M7 are respectively connected to the input signal V IN connected, and the drain of M7 is connected to the output signal V OUT connected; The PMOS sampling switch control part includes a second PMOS transistor and a second NMOS transistor. The second PMOS transistor includes M16, M17, M18, M19, M20, M22, M23, and M26, and the second NMOS transistor includes M14, M15, M21, M24, and M25; Among them, the sources of M14, M21, and M25 and the gate of M16 are respectively grounded to VSS. The gates of M21, M22, M24, M25, and M26 are respectively connected to the sampling clock CLKB. The drain of M14 is connected to the source of M15. The drains of M15 and the source of M16 are respectively connected to the gates of M14, M19, and M20. The drain of M16 is connected to the source of M17. The drain of M5 is connected to the source of M19. The drains of M19 and the source of M20 are respectively connected to the input signal V IN connection, and the drain of M20 is connected to the output signal V OUT connection.

2. The complementary bootstrap switch based on a negative voltage bootstrap capacitor according to claim 1, wherein The NMOS sampling switch control section further includes that the drain of M8 and the source of M9 are respectively connected to the gates of M2 and M10, the drain of M9 is respectively connected to the sources of M10 and M11, and the drains of M10 and M11 are respectively connected to the input signal V IN connection, and the drains of M12 and M13 are connected.

3. The complementary bootstrap switch based on a negative voltage bootstrap capacitor according to claim 1, wherein The NMOS sampling switch control part further includes a first capacitor. The first capacitor includes C1 and C2. Wherein, the upper plate of C1 is connected to the drain of M1, the lower plate of C1 is connected to the drain of M5, the upper plate of C2 is connected to the source of M11, the lower plate of C2 is connected to the drain of M13, the substrates of M1 and M2 are respectively connected to the drain of M1, and the substrate and the source of M10 are connected.

4. The complementary bootstrap switch based on a negative voltage bootstrap capacitor according to claim 1, wherein The PMOS sampling switch control section further includes that the drain of M21 and the source of M22 are respectively connected to the gates of M15 and M23, the drain of M22 is respectively connected to the sources of M23 and M24, and the drains of M23 and M24 are respectively connected to the input signal V IN connection, and the drains of M25 and M26 are connected.

5. A complementary bootstrap switch based on a negative voltage bootstrap capacitor according to claim 1, characterized in that, The PMOS sampling switch control part further includes a second capacitor. The second capacitor includes C3 and C4. The upper plate of C3 is connected to the drain of M14, the lower plate of C3 is connected to the drain of M18, the upper plate of C4 is connected to the source of M23, the lower plate of C4 is connected to the drain of M26, the substrates of M14 and M15 are respectively connected to the drain of M14, and the substrate and the source of M23 are connected.

6. The working method of the complementary bootstrap switch based on a negative voltage bootstrap capacitor according to any one of claims 1-5, characterized in that, It includes: When the bootstrap switch operates in the hold stage, CLK is at a low level and CLKB is at a high level; For the NMOS sampling switch control part: M1, M3, M4, and M5 are turned on, M2, M6, and M7 are turned off, and the potential of the upper plate of C1 is V DD , and the potential of the lower plate of C1 is V SS ; M8, M10, M11, and M12 are turned on, M9 and M13 are turned off, and the potential of the upper plate of C2 is V IN , and the potential of the lower plate of C2 is V DD ; For the PMOS sampling switch control part: M14, M16, M17, and M18 are turned on, M15, M19, and M20 are turned off, and the potential of the upper plate of C3 is V SS , and the potential of the lower plate of C3 is V DD ; M21, M23, M24, and M25 are turned on, M22 and M26 are turned off, and the potential of the upper plate of C4 is V IN , and the potential of the lower plate of C4 is V SS .

7. A complementary bootstrap switch operating method based on a negative voltage bootstrap capacitor according to claim 6, characterized in that When the bootstrap switch operates in the sampling stage, CLK is at a high level and CLKB is at a low level; For the NMOS sampling switch control part: M2, M6, and M7 are turned on, while M1, M3, M4, and M5 are turned off. The potential of the upper plate of C1 is V DD +V IN , and the potential of the lower plate is V IN ; M9 and M13 are turned on, while M8, M10, M11, and M12 are turned off. The potential of the upper plate of C2 is V IN -V DD , and the potential of the lower plate is V SS ; For the PMOS sampling switch control part: M15, M19, and M20 are turned on, M14, M16, M17, and M18 are turned off, and the potential of the upper plate of C3 is V IN -V DD , and the potential of the lower plate is V IN ; M22 and M26 are turned on, M21, M23, M24, and M25 are turned off, and the potential of the upper plate of C4 is V IN +V DD , and the potential of the lower plate is V DD .

8. A complementary bootstrap switch operating method based on a negative voltage bootstrap capacitor as described in claim 7, characterized in that When the boost switch works in the sampling stage, the gate-source voltage V of M7 GS7 = V DD , the gate-source voltage V of M20 SG20 = V DD , the gate-source voltage V of M2 SG2 = 2V DD , the gate-source voltage V of M15 GS15 = 2V DD .

9. The working method of a complementary bootstrap switch based on a negative voltage bootstrap capacitor according to claim 8, characterized in that, When the bootstrap switch operates in the sampling stage, the on-resistance of M2 is: where μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, W and L are the channel width and length of M2, and V TH is the threshold voltage.

10. A complementary bootstrap switch operating method based on a negative voltage bootstrap capacitor as described in claim 9, characterized in that When the bootstrap switch operates in the sampling stage, the on-resistance of M2 remains unchanged, the gate-source voltage of M2 increases while the width-to-length ratio decreases, thereby reducing the parasitic capacitance brought by the transistor and reducing the influence of charge redistribution on the gate potential of the transistor.

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