Methods, systems, devices, and media for constructing sequence diagrams between modules

Abstract

This application provides a method, system, device, and medium for constructing timing diagrams between modules, applied in the field of electronic design automation technology. The method includes: dividing a circuit design system into at least one sub-module; trimming redundant units in each sub-module and retaining necessary units to obtain a sub-netlist corresponding to each sub-module, where necessary units represent units located at boundary positions in the sub-module, and redundant units represent units not located at boundary positions in the sub-module; traversing all sub-modules to obtain at least one sub-netlist; obtaining a top-level netlist of the circuit design system based on the at least one sub-netlist, marking delay values ​​in the top-level netlist to obtain a timing diagram; and performing timing analysis on the circuit design system based on the timing diagram. By performing system-level trimming on the segmented netlists, retaining only the parts related to system-level timing calculations, the size of the timing diagram can be significantly reduced, shortening the time for inter-module timing analysis.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, specifically to a method, system, device, and medium for constructing timing diagrams between modules. Background Technology

[0002] Electronic Design Automation (EDA) evolved from the concepts of Computer-Aided Design (CAD), Computer-Aided Manufacturing (CAM), Computer-Aided Testing (CAT), and Computer-Aided Engineering (CAE) in the mid-1960s. Modern EDA technology uses computers as tools. Designers complete design documents using hardware description languages ​​on an EDA software platform, and the computer automatically performs logic compilation, simplification, partitioning, synthesis, optimization, placement, routing, and simulation, up to the adaptation compilation, logic mapping, and programming download for specific target chips.

[0003] EDA tools can be applied to IC design and to perform static timing analysis on the completed circuit design, verifying the circuit in terms of timing.

[0004] Currently, existing timing analysis tools can only construct timing diagrams for individual modules and perform timing calculations on the entire netlist. Because these tools lack module partitioning or, after partitioning, lack methods for analyzing the relationships between modules, the entire netlist is contained within a single module. When the user's design is large, the constructed timing diagram becomes excessively large, containing numerous redundant units, resulting in time-consuming and inefficient timing calculations.

[0005] Therefore, a new technical solution for constructing sequence diagrams is needed. Summary of the Invention

[0006] In view of this, embodiments of this specification provide a method, system, device, and medium for constructing timing diagrams between modules, which solves the technical problems that existing timing analysis tools can only construct timing diagrams for a single module, and that timing diagrams contain a large number of redundant units, resulting in time-consuming and inefficient timing calculations.

[0007] The embodiments in this specification provide the following technical solutions:

[0008] This specification provides an embodiment of a method for constructing a sequence diagram between modules, including:

[0009] The circuit design system is divided into at least one sub-module;

[0010] Redundant units in each submodule are pruned, and necessary units are retained to obtain the subnet list corresponding to each submodule. Necessary units represent units located at the boundary positions in the submodule, and redundant units represent units not located at the boundary positions in the submodule.

[0011] Traverse all submodules to obtain at least one subnetlist;

[0012] The top-level netlist of the circuit design system is obtained from at least one subnetlist. Delay values ​​are marked in the top-level netlist to obtain the timing diagram.

[0013] Perform timing analysis on the circuit design system based on the timing diagram.

[0014] Preferably, the ports of necessary units are located at the boundary of the submodule, while the ports of redundant units are not located at the boundary of the submodule. Redundant units in each submodule are pruned, and necessary units are retained, resulting in a subnet list corresponding to each submodule, including:

[0015] For each submodule, iterate through the ports at the boundary positions of the submodule, and perform a search on the submodule according to the direction of the ports to obtain the search results;

[0016] Based on the search results, points and edges are constructed to obtain a subnet table.

[0017] Preferably, for each submodule, the ports at the boundary positions of the submodule are traversed, and the submodule is searched according to the direction of the ports to obtain the search results, including:

[0018] Determine the direction of the port;

[0019] If the direction of the port is the input direction, then a forward search is performed with the port as the node to obtain the search result;

[0020] If the port's direction is the output direction, then a reverse search is performed using the port as the node to obtain the search result.

[0021] Preferably, based on the search results, vertex and edge construction is performed to obtain a subnet table, including:

[0022] If the search result is a boundary point of a basic unit or submodule, then the port or boundary point of the basic unit is used as a node to build points and edges, and a subnet table is obtained.

[0023] Preferably, the basic unit includes: a timing unit and a combination unit;

[0024] If the search result is a boundary point of a basic unit or submodule, then the ports or boundary points of the basic unit are used as nodes to construct points and edges, resulting in a subnet table, including:

[0025] If the basic unit is a composite unit, then the subnet table is obtained by constructing points and edges based on the time arc of the composite unit and using the ports of the basic unit as nodes.

[0026] If the basic unit is a timing unit, the search ends, and a reverse search is performed based on the clock point of the timing unit to obtain the subnet list.

[0027] Preferably, the submodules are searched according to the direction of the port to obtain the search results, including:

[0028] A depth-first search is performed on the submodules based on the direction of the port to obtain the search results.

[0029] Preferably, the top-level netlist of the circuit design system is obtained based on at least one subnetlist, and delay values ​​are marked in the top-level netlist to obtain a timing diagram, including:

[0030] Traverse the nodes corresponding to the ports at the boundary positions of the corresponding submodules in each subnet list. Based on the direction of the nodes, construct nodes and edges for the out-degree points of the nodes. Connect at least one subnet list to obtain the top-level netlist. The out-degree point represents the next node connected to the node.

[0031] Based on the delay information in the standard delay format file, the delay values ​​are marked in the top-level netlist to obtain the timing diagram.

[0032] This specification also provides a system for constructing timing diagrams between modules, including:

[0033] Module division: Divide the circuit design system into at least one sub-module;

[0034] First processing module: Redundant units in each submodule are pruned and necessary units are retained to obtain the subnet list corresponding to each submodule. Necessary units represent units located at the boundary positions in the submodule, and redundant units represent units not located at the boundary positions in the submodule.

[0035] The second processing module: traverses all sub-modules to obtain at least one subnetlist, obtains the top-level netlist of the circuit design system based on at least one subnetlist, marks the delay value in the top-level netlist, and obtains the timing diagram.

[0036] Analysis module: Performs timing analysis on the circuit design system based on the timing diagram.

[0037] This specification also provides an electronic device, including:

[0038] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method for constructing the inter-module timing diagram described above.

[0039] This specification also provides a computer storage medium storing computer-executable instructions, which, when executed by a processor, perform the aforementioned method for constructing a timing diagram between modules.

[0040] Compared with the prior art, the beneficial effects that can be achieved by the above-mentioned at least one technical solution adopted in the embodiments of this specification include at least the following: by performing system-level pruning on the segmented netlist and retaining only the part related to system-level timing calculation, the size of the timing diagram can be significantly reduced and the time for timing analysis between modules can be shortened. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart illustrating a method for constructing a sequence diagram between modules provided in this application;

[0043] Figure 2 This is a schematic diagram of the structure of a single submodule provided in this application;

[0044] Figure 3 This is a schematic diagram of a multi-submodule configuration provided in this application;

[0045] Figure 4 This is a schematic diagram of the system structure of a sequence diagram for inter-module construction provided in this application. Detailed Implementation

[0046] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0047] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0049] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0051] Currently, existing timing analysis tools can only construct timing diagrams for individual modules and perform timing calculations on the entire netlist. This approach, lacking module division or analysis methods between modules after division, results in the entire netlist being contained within a single module. This leads to excessively large timing diagrams containing numerous redundant units, resulting in time-consuming timing calculations. When user designs are too large, for example, exceeding 20 million equivalent application-specific integrated circuit (ASIC) gates, a single module cannot accommodate them. Therefore, for timing analysis of large-scale circuit designs, the user design can be divided into multiple modules, specifically sub-modules. Traditional tools are used for timing analysis within each sub-module, while timing analysis is performed after connecting the sub-modules. This approach helps shorten timing analysis time.

[0052] Based on this, the embodiments of this specification propose a processing scheme: simplifying the circuit design, cutting off redundant parts, and quickly constructing a system-level timing diagram for the large-scale segmented netlist, which can significantly reduce the size of the timing diagram and shorten the timing analysis time.

[0053] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0054] This specification provides a method for constructing timing diagrams between modules, comprising: first, dividing the circuit design system to obtain at least one sub-module.

[0055] Then, redundant units in each submodule are pruned, and necessary units are retained to obtain a subnetlist for each submodule. Necessary units represent units located at the boundary positions in the submodule, and redundant units represent units not located at the boundary positions in the submodule. Furthermore, all submodules are traversed to obtain at least one subnetlist.

[0056] The process of pruning redundant units and retaining necessary units in each submodule involves constructing timing diagrams only for the boundary portions of each submodule, omitting timing diagrams for non-boundary portions. When encountering combinational logic units, points and edges are established. When encountering sequential units, the clock input of the sequential unit is located, and the search proceeds in reverse until the boundary point is reached. This specification focuses only on units located at the boundaries of each submodule; redundant units refer to units in the non-boundary portions.

[0057] This specification divides large-scale circuit designs into multiple sub-modules. Essential units are retained within each sub-module, while redundant units are removed, thus completing the layout between the sub-modules. The distinction between essential and redundant units is determined by whether they are located at the boundary of a sub-module.

[0058] As can be seen, in this specification, the ports of necessary units are located at the boundary positions of submodules, while the ports of redundant units are not located at the boundary positions of submodules. Redundant units in each submodule are pruned, and necessary units are retained to obtain the subnet list corresponding to each submodule. This includes: for each submodule, traversing the ports at the boundary positions of the submodule, searching the submodule according to the direction of the ports to obtain the search results; and constructing points and edges according to the search results to obtain the subnet list.

[0059] Specifically, for each submodule, the ports at the boundary positions of the submodule are traversed, and the submodule is searched according to the direction of the port to obtain the search results. This includes: determining the direction of the port; if the direction of the port is the input direction, a forward search is performed with the port as the node to obtain the search results; if the direction of the port is the output direction, a reverse search is performed with the port as the node to obtain the search results.

[0060] In one optional implementation, the submodule is searched according to the direction of the port to obtain the search results, including: performing a depth-first search on the submodule according to the direction of the port to obtain the search results.

[0061] Furthermore, based on the search results, point and edge construction is performed to obtain a subnet table, including: if the search result is a boundary point of a basic unit or submodule, then point and edge construction is performed using the port or boundary point of the basic unit as a node to obtain a subnet table.

[0062] In one optional implementation, the basic unit includes: a timing unit and a combination unit; if the search result is a boundary point of the basic unit or a submodule, then point and edge construction is performed using the port or boundary point of the basic unit as nodes to obtain a subnet list, including: if the basic unit is a combination unit, then point and edge construction is performed using the port of the basic unit as nodes according to the timing arc of the combination unit to obtain a subnet list; if the basic unit is a timing unit, then the search ends, and a reverse search is performed according to the clock point of the timing unit to obtain a subnet list.

[0063] In one specific implementation, trimming a single submodule includes: traversing the ports at the boundary positions of the submodule. If the direction of the port is the input direction, it is considered a drive, and a forward search is performed. When the depth-first search encounters a basic unit or submodule boundary point, that port is used as the endpoint for point and edge construction. Here, basic units refer to composite units and timing units. Point and edge construction means extracting information from the point and constructing connections to it.

[0064] Specifically, if the basic unit is a composite unit, the timing arcs inside the composite unit are obtained from the timing library, points and edges are constructed, and a depth-first search continues. If the basic unit is a timing unit, the search ends, and the clock point of the timing unit is found from the timing library. Then, a reverse search is performed until an internal clock or a point on the submodule boundary is reached. Further, if the search result is a point on the submodule boundary, point and edge construction is performed, and the search ends.

[0065] Correspondingly, if the port's direction is out, it is considered a load port, and a reverse search is performed. The search steps are the same as above, but the search direction is reversed. Forward and reverse directions are determined by the node's direction. When the node's direction is in, it is a forward search; when the node's direction is out, it is a reverse search.

[0066] Then, the top-level netlist of the circuit design system is obtained based on at least one subnetlist. Delay values ​​are marked in the top-level netlist to obtain the timing diagram.

[0067] In one optional implementation, a top-level netlist of the circuit design system is obtained based on at least one subnetlist. Delay values ​​are marked in the top-level netlist to obtain a timing diagram. This includes: traversing the nodes corresponding to the ports at the boundary positions of the corresponding submodules in each subnetlist; constructing nodes and edges for the out-degree points of the nodes according to their directions; connecting at least one subnetlist to obtain a top-level netlist, where the out-degree point represents the next node connected to the node; and marking delay values ​​in the top-level netlist according to the delay information in the standard delay format file to obtain a timing diagram.

[0068] Specifically, using the top-level netlist of the multi-submodule system, the points on the boundaries of each submodule are traversed. If the direction of a point is "out", then an out-degree point and edge are constructed on the boundary of that submodule. Here, an out-degree edge refers to the next edge connected to the current node, and an out-degree point refers to the next node connected to the current node. Then, delay values ​​are marked on the top-level netlist. By querying the delay information in the Standard Delay Format (SDF) file, the delay value between two points is obtained and marked in the top-level netlist to obtain the timing diagram.

[0069] Finally, timing analysis of the circuit design system is performed based on the timing diagram.

[0070] like Figure 1 The diagram shows one implementation of a method for constructing timing diagrams between modules provided in this specification, including: Step 1: reading in the netlist file of the circuit design and the standard delay format file; Step 2: dividing the circuit design into multiple sub-modules and trimming and constructing the diagram for each sub-module.

[0071] like Figure 2 As shown, starting from port1 with the port direction being "in", the forward search continues, passing through ports2 and 3. When port4 is reached, it is a combination unit. Points and edges are built for ports1 and 4, and the search continues through this combination unit. The forward search continues, passing through ports5 and 6. Port6 is a basic timing device, i.e., a timing unit. Points and edges are built for this basic timing device, and the clock point of the basic timing device is found. Then, the search is reversed until the boundary point of this submodule, port10. Similarly, for port11 on the boundary of the submodule, the direction is found to be "out", so the search is reversed to find port14. After passing through the combination unit, points and edges are built, and the search continues inward to find the clock point of the basic timing device, port17. The search is reversed again to find the boundary point of this submodule, port20. Points and edges are built, and the search ends, completing the trimming of the circuit diagram inside a single submodule.

[0072] Step 3: Create a diagram of the sub-modules.

[0073] like Figure 3 As shown, it includes two sub-modules: Module 1 and Module 2. "Other" can refer to the global reset and clock modules. The sub-modules are connected via Time Division Multiplexing (TDM). The transmit (TX) and receive (RX) modules are connected by a cable. The TDM module is modeled and abstracted as a delay line. The cable represents a special type of cable because it has different transmission rates depending on the ratio of the TDM module, corresponding to different transmission delay values.

[0074] The process involves constructing a graph between submodules, traversing the out-degree points of each submodule, bypassing the TDM module, and directly locating the in-degree point at the boundary of the Userdesign in Module 1 by querying the interconnection relationships between submodules in the configuration file. This completes the graph construction between submodules.

[0075] Step 4: Label the delay values ​​in the timing diagram.

[0076] Specifically, delay values ​​are marked on the timing diagram by querying a Standard Delay Format (SDF) file. The SDF file contains all delay times and timing constraint parameters in the top-level netlist. The delay types in the SDF file include cell delay and wire delay. Cell delay represents the delay within a logic unit device, while wire delay refers to the delay between devices connected via wires.

[0077] Finally, the output node information includes the node's in-degree and out-degree points, as well as the delay value between the two points. The node information refers to the connection relationships between nodes and the stored delay values ​​between two nodes; each node corresponds to a port. Timing analysis involves analyzing the constructed timing graph to determine whether the maximum delay of the triggers meets the setup time requirement and whether the minimum delay of the triggers meets the hold time requirement.

[0078] As we know, the in-degree of a node refers to the previous node connected to that node, and the out-degree refers to the next node connected to that node.

[0079] This specification also provides an embodiment of a system for constructing timing diagrams between modules, such as... Figure 4 As shown, system 100 includes: a partitioning module 101, a first processing module 102, a second processing module 103, and an analysis module 104.

[0080] Among them, the partitioning module 101: divides the circuit design system to obtain at least one sub-module.

[0081] First processing module 102: performs pruning on redundant units in each submodule and retains necessary units to obtain a subnetlist corresponding to each submodule. Necessary units represent units located at the boundary positions in the submodule, and redundant units represent units not located at the boundary positions in the submodule.

[0082] In this process, the ports of necessary units are located at the boundary positions of submodules, while the ports of redundant units are not located at the boundary positions of submodules. The first processing module 101 includes: module M101: for each submodule, traversing the ports at the boundary positions of the submodule, performing search processing on the submodule according to the direction of the ports, and obtaining search results; module M102: performing point and edge construction processing according to the search results, and obtaining a subnet list.

[0083] Specifically, module M101 includes: module M1011: determining the direction of the port; module M1012: if the direction of the port is the input direction, then performing a forward search with the port as the node to obtain the search result; module M1013: if the direction of the port is the output direction, then performing a reverse search with the port as the node to obtain the search result.

[0084] Among them, module M102 includes: module M1021: if the search result is the boundary point of a basic unit or a sub-module, then the port or boundary point of the basic unit is used as the node to perform point and edge construction processing to obtain the subnet list.

[0085] Specifically, the basic unit includes: timing unit and combination unit; module M1021 includes: unit D101: if the basic unit is a combination unit, then according to the timing arc of the combination unit, the port of the basic unit is used as the node to build the point and edge to obtain the subnet list; unit D102: if the basic unit is a timing unit, then the search ends, and according to the clock point of the timing unit, the reverse search is performed to obtain the subnet list.

[0086] Specifically, the search process for sub-modules is performed based on the direction of the port to obtain search results, including: performing a depth-first search on the sub-modules based on the direction of the port to obtain search results.

[0087] Second processing module 103: Traverse all sub-modules to obtain at least one subnetlist; obtain the top-level netlist of the circuit design system based on at least one subnetlist, mark the delay value in the top-level netlist, and obtain the timing diagram.

[0088] The second processing module 103 includes: module M201: traversing the nodes corresponding to the ports at the boundary positions of the corresponding sub-modules on each subnet list, performing point and edge construction processing on the out-degree points of the nodes according to the direction of the nodes, connecting at least one subnet list to obtain a top-level netlist, where the out-degree point represents the next node connected to the node; module M202: marking the delay value in the top-level netlist according to the delay information in the standard delay format file to obtain a timing diagram.

[0089] Analysis Module 104: Perform timing analysis on the circuit design system based on the timing diagram.

[0090] This specification also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described method for constructing a timing diagram between modules.

[0091] This specification also provides a computer storage medium storing computer-executable instructions, which, when executed by a processor, perform the aforementioned method for constructing a timing diagram between modules.

[0092] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the product embodiments described later are relatively simple since they correspond to the methods; relevant parts can be referred to the descriptions in the system embodiments.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for constructing a sequence diagram between modules, characterized in that, include: Read in the netlist file of the circuit design and the standard delay format file; The circuit design system is divided into at least one sub-module; Redundant units in each submodule are pruned, and necessary units are retained to obtain a subnet list corresponding to each submodule. The necessary units represent units located at the boundary positions in the submodule, and the redundant units represent units not located at the boundary positions in the submodule. Traverse all the sub-modules to obtain at least one subnetlist; The top-level netlist of the circuit design system is obtained based on at least one of the subnetlists, and the delay value is marked in the top-level netlist to obtain the timing diagram. Timing analysis is performed on the circuit design system based on the timing diagram.

2. The method for constructing a sequence diagram between modules according to claim 1, characterized in that, The ports of the necessary units are located at the boundary of the submodule, while the ports of the redundant units are not located at the boundary of the submodule. The redundant units in each submodule are pruned, and the necessary units are retained, resulting in a subnet table corresponding to each submodule, including: For each submodule, traverse the ports at the boundary positions of the submodule, and perform a search on the submodule according to the direction of the port to obtain the search result; Based on the search results, point and edge construction is performed to obtain the subnet table.

3. The method for constructing a sequence diagram between modules according to claim 2, characterized in that, For each submodule, traverse the ports at the boundary positions of the submodule, and perform a search on the submodule according to the direction of the port to obtain the search results, including: Determine the direction of the port; If the direction of the port is the input direction, then a forward search is performed with the port as the node to obtain the search result; If the direction of the port is the output direction, then a reverse search is performed with the port as the node to obtain the search result.

4. The method for constructing a sequence diagram between modules according to claim 2 or 3, characterized in that, The step of constructing points and edges based on the search results to obtain the subnet table includes: If the search result is a basic unit or a boundary point of the sub-module, then the port of the basic unit or the boundary point is used as a node to build points and edges to obtain the subnet table.

5. The method for constructing a sequence diagram between modules according to claim 4, characterized in that, The basic unit includes: a timing unit and a combination unit; If the search result is a basic unit or a boundary point of the submodule, then point and edge construction is performed using the port of the basic unit or the boundary point as nodes to obtain the subnet table, including: If the basic unit is the combined unit, then the subnet table is obtained by constructing points and edges based on the time arc of the combined unit and using the ports of the basic unit as nodes. If the basic unit is the timing unit, the search ends, and a reverse search is performed based on the clock point of the timing unit to obtain the subnet list.

6. The method for constructing a sequence diagram between modules according to claim 2, characterized in that, The search process for the submodule based on the direction of the port to obtain the search results includes: The search results are obtained by performing a depth-first search on the submodule based on the direction of the port.

7. The method for constructing a sequence diagram between modules according to claim 1, characterized in that, The top-level netlist of the circuit design system is obtained based on at least one of the subnetlists. Delay values ​​are marked in the top-level netlist to obtain the timing diagram, including: Traverse the nodes corresponding to the ports at the boundary positions of the corresponding sub-modules in each subnet list, and perform point and edge construction on the out-degree points of the nodes according to the direction of the nodes, connecting at least one subnet list to obtain the top-level netlist, where the out-degree point represents the next node connected to the node. Based on the delay information in the standard delay format file, the delay value is marked in the top-level netlist to obtain the timing diagram.

8. A system for constructing sequence diagrams between modules, characterized in that, include: Module partitioning: This is used to read in the netlist file and standard delay format file of the circuit design, and to partition the circuit design system to obtain at least one sub-module; First processing module: performs pruning on redundant units in each sub-module and retains necessary units to obtain a subnet list corresponding to each sub-module. The necessary units represent units located at the boundary positions in the sub-module, and the redundant units represent units not located at the boundary positions in the sub-module. The second processing module traverses all the sub-modules to obtain at least one sub-netlist, and obtains the top-level netlist of the circuit design system based on at least one sub-netlist, marks the delay value in the top-level netlist, and obtains the timing diagram. Analysis module: Performs timing analysis on the circuit design system based on the timing diagram.

9. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method for constructing a timing diagram between modules according to any one of claims 1-7.

10. A computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which, when executed by a processor, perform the method for constructing a timing diagram between modules according to any one of claims 1-7.

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