Monocrystalline sic / si wafer substrate, heterostructure and method for preparing the same

Abstract

The present invention provides a single crystal SiC / Si wafer substrate, a heterostructure and a method for making the same. The single crystal SiC / Si wafer substrate includes a Si substrate having a plurality of patterned unit regions formed thereon, the plurality of unit regions being separated from each other by a spacing region, and each unit region including a single crystal SiC layer formed on the corresponding unit region. The heterostructure includes the aforementioned single crystal SiC / Si and a GaN layer. The method for making includes reacting the carbon-containing material layer with the Si substrate exposed in the recess by an annealing process to selectively grow a single crystal SiC layer. Similarly, the nitrogen-containing gas and the gallium-containing gas phase material are reacted by an MOCVD epitaxial growth process to form a single crystal GaN layer on the patterned single crystal SiC / Si wafer substrate. The resulting single crystal SiC and GaN structures within the unit regions have high quality and low defect density.

Description

TECHNICAL FIELD

[0001] The present invention relates to a heterostructure and a method for fabricating the same; in particular, to a single crystal SiC / Si wafer substrate, a single crystal GaN / SiC heterostructure and a method for fabricating the same. BACKGROUND

[0002] High power and high frequency circuits require devices based on semiconductor materials that have both high breakdown voltage and high electron velocity. Unlike conventional semiconductor materials, wide bandgap materials such as GaN and SiC are of particular interest due to their ability to be used at higher power densities. GaN and SiC based devices grown on silicon (Si) substrates are expected to be one of the best candidate materials for the next generation of systems seeking to integrate RF and digital circuits next to each other, void free.

[0003] SiC has also received wide attention in the power application area due to its high thermal conductivity compared to GaN, which can theoretically sustain higher power densities than the existing poly-SiC, 3C-SiC can be grown directly on Si and is of interest due to its extremely high electron mobility. Currently, there have been numerous attempts to directly grow and integrate high quality SiC and GaN devices on Si substrates for high quality power device applications.

[0004] More commonly used integration techniques are hybrid integration and heteroepitaxy, where hybrid integration methods such as wire bonding and flip-chip methods provide a short term solution. However, this approach has many limitations in terms of interconnect loss and chip positioning / alignment issues and integration density. In addition, the cost of using SiC and GaN materials for power devices that exhibit superior performance is greatly limited by high defect density and small size substrates.

[0005] Heteroepitaxy of different semiconductors onto Si substrates is a more promising approach, while the biggest problem in growing compound semiconductors (CS) directly on Si is the lattice mismatch and the mismatch of the coefficient of thermal expansion (CTE). Currently, the formation of GaN and SiC on larger size Si wafers seems to reduce the cost, while the lattice mismatch and high defect density problems become more severe on larger size Si wafers. Alternatively, a complex process of introducing multiple layers such as buffer layers, superlattice layers and barrier layers is required.

[0006] Therefore, there is a need in the art for a simplified method for growing high quality single crystal SiC and GaN on large size silicon wafers and improved structures thereof. SUMMARY

[0007] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a method for preparing a single crystal SiC-Si wafer substrate, which is used to solve the problem of lattice mismatch and thermal expansion coefficient mismatch between a SiC layer and a substrate heterogeneously grown on a larger Si substrate.

[0008] To achieve the above object and other related objects, the present application provides a patterned single crystal SiC / Si wafer substrate, a patterned single crystal GaN / SiC / Si heterostructure wafer substrate and a method for preparing the same. The method for preparing the single crystal SiC / Si wafer substrate comprises at least the following steps: providing a Si substrate; depositing a SiO2 layer on the Si substrate and patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer, the recesses being defined by SiO2 sidewalls surrounding the recesses and the recess bottoms exposing the Si substrate; forming a carbon-containing material layer in the recesses; reacting the carbon-containing material layer with the Si substrate exposed in the recesses by an annealing process to selectively grow a single crystal SiC layer at the recess bottoms; and removing the residual carbon-containing material layer by a chemical mechanical polishing process to form a plurality of SiC unit regions separated by the SiO2 sidewalls.

[0009] Preferably, the annealing process comprises furnace annealing or rapid thermal annealing.

[0010] Preferably, the method for preparing the single crystal SiC / Si wafer substrate is characterized in that the annealing process is a laser-based local annealing process.

[0011] Preferably, the size of the SiC unit region is less than or equal to 4 inches.

[0012] Preferably, the SiC unit region has a shape of a smooth rounded polygon, an ellipse, a circle or a combination thereof.

[0013] Preferably, the SiC unit region has a thickness of from 0.1 um to 10 um.

[0014] Preferably, the carbon-containing material layer comprises a carbon layer formed by spin coating polymethyl methacrylate or chemical vapor deposition.

[0015] The present application also provides a single crystal SiC / Si wafer substrate, which comprises at least a Si substrate having a plurality of patterned unit regions formed thereon, the plurality of unit regions being separated from each other by spacing regions, and each unit region comprising a single crystal SiC layer formed on the corresponding unit region.

[0016] Preferably, the spacing region comprises silicon dioxide or a void.

[0017] Preferably, the single crystal SiC is 3C-SiC or 4H-SiC.

[0018] The present application provides a SiC-based metal-oxide-semiconductor field-effect transistor, which is formed based on the aforementioned patterned single crystal SiC / Si wafer substrate.

[0019] The present application provides a method for preparing a patterned single crystal GaN / SiC / Si heterostructure wafer substrate, which at least comprises: providing a Si substrate; depositing a SiO2 layer on the Si substrate, and patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer, the recesses being defined by SiO2 sidewalls around the periphery thereof and the recesses exposing the Si substrate at the bottom; forming a carbon-containing material layer in the recesses; reacting the carbon-containing material layer with the Si substrate exposed in the recesses by an annealing process to selectively grow a single crystal SiC layer at the bottom of the recesses; removing the residual carbon-containing material layer by a chemical mechanical polishing process to form SiC cell regions separated by the SiO2 sidewalls; continuing to deposit a GaN stack on the patterned SiC / Si wafer substrate, the GaN stack comprising a GaN layer and an AlGaN barrier layer; and removing the GaN stack on the SiO2 surface by a chemical mechanical polishing process.

[0020] Preferably, the GaN stack further comprises a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.

[0021] Preferably, the GaN stack is deposited by performing a MOCVD epitaxial growth process, which comprises: forming a GaN nucleation layer at a temperature of 500-800℃; and forming a GaN epitaxial layer at a temperature of 900-1100℃.

[0022] Preferably, the precursors used for depositing the GaN stack comprise NH3 as a nitrogen source and an aluminum-, gallium-containing organic vapor material.

[0023] Preferably, the aluminum-containing organic vapor material is trimethylaluminum (TMAl) and the gallium-containing organic vapor material is trimethylgallium (TMGa).

[0024] The present application also provides a patterned single crystal GaN / SiC / Si heterostructure wafer substrate, which at least comprises: a Si substrate, the Si substrate being formed with a plurality of patterned cell regions, the plurality of cell regions being spaced apart from each other by spacing regions, and each cell region comprising: a single crystal SiC layer formed on the corresponding cell region; and a GaN stack, the GaN stack comprising a GaN layer and an AlGaN barrier layer.

[0025] Preferably, the GaN stack further comprises a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.

[0026] The present application also provides a GaN-based high electron mobility transistor (HEMT) formed based on the wafer substrate of the patterned single crystal GaN / SiC / Si heterostructure as described above.

[0027] As described above, the method for preparing the single crystal SiC / Si wafer substrate of the present application has the following beneficial effects: the single crystal SiC layer is selectively grown on the Si substrate, which can purposefully position the CMOS device based on compound semiconductor on the substrate, thereby optimizing the performance of the circuit, while the selective area growth can reduce the defect density at the interface, so that the device based on such wafer substrate has small leakage current and optimized performance; the laser with high energy is used, which can provide a localized heating scheme, and by controlling the spatial distribution of the laser, the resolution of the irradiated area can be improved; the localized annealing based on laser enables the Si material to undergo melting and recrystallization in a very short period of time, quickly making the material uniform, which allows the modification of the surface properties without changing the bulk region properties, and reduces the damage to the substrate and adjacent circuits by limiting the energy absorption area to the irradiated surface area. Through the method for preparing the patterned single crystal SiC / Si wafer substrate, high-quality single crystal SiC and GaN can be grown on a large-size substrate, and the obtained wafer substrate structure has high quality and low defect density, and is particularly suitable for manufacturing SiC and GaN power devices. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A flow chart showing the method for preparing the single crystal SiC / Si wafer substrate of the present application.

[0029] Figure 2 A structural schematic diagram showing the patterned single crystal SiC / Si wafer substrate according to the present application.

[0030] Figures 3 to 6 A structural schematic diagram showing each stage of the method for preparing the single crystal SiC / Si wafer substrate of the present application.

[0031] Figure 7 A flow chart showing the method for preparing the wafer substrate of the patterned single crystal GaN / SiC / Si heterostructure of the present application.

[0032] Figure 8 A structural schematic diagram showing the wafer substrate of the patterned single crystal GaN / SiC / Si heterostructure of the present application.

[0033] Figure 9 FIG. 1 is a plan view showing a schematic diagram of a HEMT device prepared from a wafer substrate of a patterned single-crystal GaN / SiC / Si heterostructure according to the present application.

[0034] Element No. Description

[0035] 110 Si substrate

[0036] 120 SiO2layer

[0037] 122 SiO2side wall

[0038] 124 spacer

[0039] 130 recess

[0040] 140 SiC layer

[0041] 142 SiC cell region

[0042] 250 GaN layer

[0043] 252 GaN / SiC cell region

[0044] 350 GaN stack

[0045] 352 GaN buffer layer

[0046] 354 GaN hetero layer

[0047] 356 AlGaN barrier layer

[0048] 360 gate metal

[0049] 370 source metal

[0050] 380 drain metal

[0051] S1-S8 steps DETAILED DESCRIPTION

[0052] Thereafter, the present application will be described by way of specific example, and it will be apparent to those skilled in the art that other advantages and embodiments of the application can be derived from the description that is disclosed herein without departing from the spirit and scope of the application. The present application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. For the purpose of clarity, components and steps that are well known to those skilled in the art are omitted to avoid unnecessarily obscuring the elements of the present application.

[0053] It is to be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation, the shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can also be more complex.

[0054] To solve the problems of lattice mismatch and thermal expansion coefficient mismatch between the compound semiconductor grown on a larger Si substrate and the substrate, and the device performance degradation caused by high defect density, the present application provides a novel method to selectively or locally grow SiC on a Si substrate. This method allows the performance of the circuit to be optimized by purposefully positioning the compound semiconductor-based CMOS device on a commonly used Si substrate. Selective area growth helps to reduce the density of misfit dislocations in a lattice-mismatched system by reducing the interaction and proliferation of dislocations. Since the area of the growth region is limited to a few mm 2 , the quality of the heteroepitaxial compound semiconductor can be better optimized.

[0055] In the present context, the term "large size substrate" means a wafer having a size exceeding 4 inches in terms of wafer diameter; thus, the method for preparing a single-crystal SiC / Si wafer substrate according to the present application can be applied to a larger wafer having a size exceeding 4 inches, such as a wafer having a size of 6 inches or more, for example, a wafer having a size of 8 inches.

[0056] Conventionally, the step of growing SiC by carbonization on a Si substrate can be preceded by depositing a carbon source on the Si using an annealing process conventional in the art, which causes the carbon to diffuse into the Si. Examples of annealing processes conventional in the art include furnace annealing, rapid thermal annealing (RTA), in which, due to enhanced SiC crystallization at high heating rates, the growth of the SiC layer can be performed at relatively lower temperatures, for example, at temperatures of 1000-1400°C. Preferably, the carbon source deposited on the Si can be locally annealed using a high-power laser beam. Laser irradiation has very high energy, which can decompose the carbon source while simultaneously melting the silicon, thereby initiating the growth of SiC. Laser-based processes can provide localized heating; in particular, by focusing the laser beam with an optical element, the spatial distribution of the laser can be controlled, which allows the localization of the irradiation energy and increases the spatial resolution of the laser. Further, laser-based localized annealing can enable SiC growth on large substrates under ambient conditions (atmospheric pressure and room temperature conditions), which allows the irradiated region of the Si substrate to undergo melting and recrystallization in a very short time period, as compared to conventional furnace annealing and RTA processes.

[0057] In another aspect, the present application also provides a method for growing a crack-free AlGaN / GaN heterostructure on a single crystal SiC / Si wafer substrate, the AlGaN / GaN heterostructure is epitaxially grown on a single crystal SiC layer by a metal organic chemical vapor deposition (MOCVD) technique, the SiC layer is grown on a selected area of the Si substrate relative to the SiC growth on the whole substrate, and the performance of the device can be effectively improved by adjusting the accumulation of the lattice mismatch and thermal expansion mismatch; accordingly, a high-quality GaN / SiC heterostructure can be formed on a patterned single crystal SiC / Si wafer substrate. Such AlGaN / GaN heterostructure can be used to prepare high-performance power devices, such as high electron mobility transistors (HEMTs).

[0058] As shown in Figure 1 and Figures 3-6 The present application provides a method for selectively forming a single crystal SiC on a Si substrate, the method for selectively forming a single crystal SiC layer comprises the following steps:

[0059] S1: providing a Si substrate.

[0060] S2: depositing a SiO2 layer on the Si substrate.

[0061] S3: patterning the SiO2 layer to form a plurality of grooves in the SiO2 layer.

[0062] S4: forming a carbon-containing material layer in the grooves.

[0063] S5: forming a SiC layer in the grooves by an annealing process.

[0064] S6: planarization and cleaning.

[0065] The method for fabricating a single-crystal SiC / Si wafer substrate of the present invention involves patterning a SiO2 layer using photolithography to form multiple grooves separated by SiO2 sidewalls. The bottom of the grooves exposes a Si substrate material. The Si substrate has a (111) crystal orientation surface. A single-crystal SiC layer is grown on the (111) crystal orientation Si substrate. This selective growth of a single-crystal SiC layer on the Si substrate can reduce the density of mismatched dislocations in a lattice-mismatched system, thereby reducing the defect density of the single-crystal SiC / Si heterostructure. Furthermore, by adjusting the process parameters of the annealing operation, the geometry and thickness of the SiC unit region can be determined, thus enabling optimization of circuit performance based on device positioning. In one embodiment, localized annealing can be used, for example, using high-energy laser thermal annealing to decompose the solid carbon source. Within a very short time, the irradiated area of ​​the Si substrate undergoes melting and recrystallization. Compared to conventional annealing processes, this allows for faster material homogenization in selective regions. Moreover, localized annealing under environmental conditions can alleviate the accumulation of thermal mismatch at the junction.

[0066] The following will combine Figure 1 The method flowchart and structural diagrams of each stage are used to specifically describe the preparation method of the patterned single-crystal SiC / Si wafer substrate.

[0067] Specifically, at step S1, Figure 3 As shown, a Si substrate 110 is provided, which has a (111) crystal plane orientation.

[0068] like Figure 4 As shown, in step S2, a SiO2 layer 120 is deposited on the surface of the Si substrate 110. The deposited SiO2 layer 120 may have a thickness greater than 0.1 μm, for example, from 0.1 μm to 5 μm. Examples of processes used to prepare the SiO2 layer may include liquid chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCVD).

[0069] Next, see Figure 5 In step S3, a patterning step is performed, in which a photomask is applied to the SiO2 layer 120 and etched to form a plurality of grooves 130, the bottom of which exposes the Si substrate material, thereby obtaining a patterned Si substrate.

[0070] Subsequently, at step S4, a carbon source is introduced to the patterned Si substrate 110 to form a carbon-containing material layer in the recesses 130. In one embodiment, examples of the carbon source according to the present embodiment can include polymethyl methacrylate (PMMA), C60, CVD carbon layer, or similar carbon-containing material, wherein the PMMA can be applied to the patterned Si substrate 110 using a spin-coating method.

[0071] Next, referring to Figure 5 , an annealing process is performed to anneal the carbon-containing material layer to cause the carbon-containing material layer to contact the Si substrate material at the bottom of the recesses 130 and grow a SiC layer 140 without SiC growth on the surface of SiO2 (i.e., the upper surface of the spacer regions 124). By selectively growing a single-crystalline SiC layer at the bottom of the recesses surrounded by SiO2 sidewalls, the defect propagation caused by lattice mismatch and coefficient of thermal expansion mismatch can be reduced, which helps to reduce the misfit dislocations and thus reduce the defects at the interface of the single-crystalline SiC and Si. Examples of the annealing process employed according to the present embodiment can include furnace annealing, rapid thermal annealing. In one embodiment, a localized annealing can be performed on the recesses 130, for example, using a laser-based technique to apply a shaped high-energy laser beam to the recesses 130 region of the Si substrate 110 to locally anneal the carbon-containing material layer pre-deposited on the Si substrate 110. As a result of the localized annealing of the semiconductor with high-energy laser, the absorbed laser energy is directly converted into heat, and through this thermal effect, a high-energy laser with a threshold value higher than the melting of the material can cause a higher solubility in the solid phase, which enables the material to reach uniformity faster. The laser source can be a KrF excimer laser (λ = 248 nm), and the shorter wavelength of the laser localizes the irradiation of the carbon-containing material layer, which can achieve a local modification of the surface properties without changing the properties of the bulk region. The laser scans the entire substrate at a certain rate to form the single-crystalline SiC layer 140 in the recesses 130 of the Si substrate 110, and the SiC unit regions 142 can have a thickness from 0.1 μm to 10 μm depending on the application of the SiC / Si wafer substrate. In the present embodiment, the thickness on the SiC unit regions can be determined by controlling the energy and scanning rate of the laser; that is, increasing the annealing time appropriately to obtain a thicker SiC layer.

[0072] Subsequently, the carbon-containing material layer remaining on the upper surface of the spacer regions 124 can be removed, for example, a chemical mechanical polishing (CMP) method can be used to treat the surface of the annealed substrate to remove the remaining carbon layer and obtain a planarized SiC surface, as shown in Figure 6 .

[0073] As a second embodiment, the present application provides a method for preparing a patterned GaN / SiC heterostructure wafer substrate, the method comprising the following steps:

[0074] S1: providing a Si substrate.

[0075] S2: depositing a SiO2 layer on the Si substrate.

[0076] S3: patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer.

[0077] S4: forming a carbon-containing material layer in the recesses.

[0078] S5: forming a SiC layer in the recesses by an annealing process.

[0079] S6: planarization and cleaning.

[0080] S7: depositing a GaN layer on the patterned SiC / Si wafer substrate.

[0081] S8: planarization and cleaning.

[0082] Referring to steps S1-S6 in the first embodiment, a patterned SiC / Si wafer substrate can be formed. After step S6, step S7, a GaN layer can be formed on the entire patterned Si substrate 110 by metal organic chemical vapor deposition (MOCVD). The patterned SiC / Si wafer substrate includes a plurality of SiC unit regions 142 and SiO2 side walls 122 for separating the SiC unit regions. In this embodiment, the MOCVD epitaxial growth process can be a two-step process, including; first, forming a GaN nucleation layer at a low temperature of 500-800 °C to effectively improve the crystal quality of the GaN thin film grown at a high temperature subsequently, and then increasing the temperature to 900-1100 °C to form a high-quality GaN layer on the GaN nucleation layer. The GaN layer 250 can include a GaN stack including a thick GaN layer and an AlGaN barrier layer. In an embodiment, the precursors for depositing the GaN layer can include a nitrogen source and an aluminum-, gallium-containing organic vapor material, for example, the nitrogen source is NH3, the aluminum-containing organic vapor material is trimethylaluminum (TMAl), and the gallium-containing organic vapor material is trimethylgallium (TMGa). In an embodiment, the GaN layer can further include a GaN buffer layer disposed between the single-crystal SiC layer 140 and the GaN layer 250 to adjust the stress balance in the epitaxial film.

[0083] Referring to Figure 7At step S8, a step of selectively removing the deposited GaN layer on the polycrystalline SiO2 surface is performed, leaving the GaN layer 250 overlying the single crystalline SiC layer 140, thereby forming a plurality of GaN / SiC cell regions 252 on the Si substrate. For example, a chemical mechanical polishing (CMP) process can be used to remove the deposited GaN layer 250 on the polycrystalline SiO2.

[0084] The present application also provides a patterned single crystalline SiC / Si wafer substrate. Referring to Figure 2 the figure is a structural schematic diagram of a patterned single crystalline SiC / Si wafer substrate according to the present application, Figure 6 may be Figure 2 the patterned single crystalline SiC / Si wafer substrate shown in the partial view along the A-A' cross section. The single crystalline SiC / Si wafer substrate has a Si substrate 110 with a crystal orientation of (111), and a plurality of patterned cell regions 142 are formed on the Si substrate 110, the plurality of cell regions are spaced apart from each other by a spacing region 124, and each cell region 142 includes a single crystalline SiC layer formed on the corresponding cell region. The SiC cell region can have a smooth rounded polygonal shape, an elliptical shape, a circular shape or the like, for reducing defect growth at the region edges. Depending on the device application, the size of the cell regions can be the same, and no more than the size of currently available SiC substrates, for example, no more than 4 inches. The smaller the size of the SiC cell region, the less stress and defects exist in the grown SiC layer. In some embodiments, the single crystalline SiC can be either of 3C-SiC or 4H-SiC.

[0085] In another aspect, the present application also provides a patterned GaN / SiC / Si heterostructure wafer substrate, which can include the patterned single crystalline SiC / Si wafer substrate as previously described, and each cell region can include a GaN stack, which can include a GaN layer and an AlGaN barrier layer. In one embodiment, the GaN stack further includes a GaN buffer layer disposed between the SiC layer and the GaN layer.

[0086] Furthermore, the single-crystal SiC / Si wafer substrate can be used to fabricate improved SiC-based metal-oxide-semiconductor field-effect transistor (MOSFET) devices. The patterned single-crystal SiC / Si wafer substrate fabrication method of the present invention provides a plurality of SiC unit regions selectively grown on a large-size substrate. The SiC unit regions are heterogeneously grown on the large-size Si substrate. Based on this high-quality SiC / Si wafer substrate, SiC-type power devices, such as MOSFET devices, can achieve optimized device performance and high yield.

[0087] The single-crystal GaN / SiC / Si heterostructure wafer substrate can be used to fabricate improved GaN high electron mobility transistor (HEMT) devices. The method for fabricating the patterned single-crystal GaN / SiC / Si heterostructure wafer substrate of this invention provides a high-quality, crack-free AlGaN / GaN heterostructure. This AlGaN / GaN heterostructure is epitaxially grown on SiC unit regions 142, reducing lattice mismatch and thermal expansion mismatch. GaN-type power devices, especially HEMT devices, fabricated based on this high-quality AlGaN / GaN heterostructure can achieve optimized device performance, high yield, and cost-effectiveness. Figure 9 The diagram shows a side cross-sectional view of a HEMT structure based on the single-crystal GaN / SiC heterostructure. The HEMT device based on the AlGaN / GaN heterostructure may include: a substrate, a SiC layer, a GaN stack 350, a gate metal 360, a source metal 370, and a drain metal 380. The GaN stack 350 includes a GaN buffer layer 352, a GaN heterolayer 354, and an AlGaN barrier layer 356. The gate metal 360 is located between the source metal 370 and the drain metal 380. The source metal 370 and drain metal 380 are in ohmic contact with the AlGaN barrier layer 356, and the gate metal 360 is in a Schottky contact with the AlGaN barrier layer 356. The gate metal 360 is used to control the density of the two-dimensional electron gas formed by the GaN heterolayer 354 and the AlGaN barrier layer 356.

[0088] In summary, the method for preparing the single crystal SiC / Si wafer substrate of the present application at least comprises: providing a Si substrate; depositing a SiO2 layer on the Si substrate, and patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer, the recesses being defined by SiO2 side walls around the periphery thereof, and the recess bottoms exposing the Si substrate; forming a carbon-containing material layer in the recesses; reacting the carbon-containing material layer with the Si substrate exposed in the recesses through an annealing process to selectively grow a single crystal SiC layer at the recess bottoms; and removing the residual carbon-containing material layer through a chemical mechanical polishing process to form a plurality of SiC unit regions separated by SiO2 side walls. The preparation method provided by the present application can grow high-quality single crystal SiC and GaN on large-size substrates, and the obtained wafer substrate structure has high quality and low defect density, so that large-size Si wafer substrates can be used to manufacture power devices with SiC or GaN as the substrate, and the yield can be improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0089] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for producing a single crystal SiC / Si wafer substrate, characterized by, The method comprises at least: providing a Si substrate; depositing a SiO2 layer on the Si substrate and patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer, the recesses being defined by SiO2 sidewalls around their periphery and the recesses exposing the Si substrate at their bottoms; forming a carbon-containing material layer in the recesses, the carbon-containing material layer comprising a carbon layer formed by chemical vapor deposition or a polymethyl methacrylate layer formed by spin coating; reacting the carbon-containing material layer with the Si substrate exposed in the recesses by an annealing process to selectively grow a single-crystalline SiC layer at the bottoms of the recesses, the annealing process comprising furnace annealing, rapid thermal annealing, or a laser-based local annealing process; and removing the residual carbon-containing material layer by a chemical mechanical polishing process to form a plurality of SiC cell regions separated by SiO2 sidewalls.

2. The method of claim 1, wherein: The SiC cell regions have a size less than or equal to 4 inches.

3. The method of claim 1, wherein: The SiC cell regions have a shape of a smooth-rounded polygon, an ellipse, a circle, or a combination thereof.

4. The method of claim 1, wherein: The SiC cell regions have a thickness from 0.1 um to 10 um.

5. A patterned single crystal SiC / Si wafer substrate, characterized by, The wafer substrate is prepared by the method of claim 1-4, and the wafer substrate comprises at least: a Si substrate having a plurality of patterned cell regions formed thereon, the plurality of cell regions being separated from each other by spacing regions, and each cell region comprising a single-crystalline SiC layer formed on the corresponding cell region.

6. The patterned single crystal SiC / Si wafer substrate of claim 5, wherein: The spacing regions comprise silicon dioxide or voids.

7. The patterned single crystal SiC / Si wafer substrate of claim 5, wherein: The single-crystalline SiC is 3C-SiC or 4H-SiC.

8. A method for preparing a wafer substrate of a patterned single-crystal GaN / SiC / Si heterostructure, characterized in that, The method comprises at least: providing a Si substrate; depositing a SiO2 layer on the Si substrate and patterning the SiO2 layer to form a plurality of recesses in the SiO2 layer, the recesses being defined by SiO2 sidewalls around their periphery and the recesses exposing the Si substrate at their bottoms; forming a carbon-containing material layer in the recesses, the carbon-containing material layer comprising a carbon layer formed by chemical vapor deposition or a polymethyl methacrylate layer formed by spin coating; reacting the carbon-containing material layer with the Si substrate exposed in the recesses by an annealing process to selectively grow a single-crystalline SiC layer at the bottoms of the recesses, the annealing process comprising furnace annealing, rapid thermal annealing, or a laser-based local annealing process; removing the residual carbon-containing material layer by a chemical mechanical polishing process to form a plurality of SiC cell regions separated by SiO2 sidewalls; continuing to deposit a GaN stack on the patterned SiC / Si wafer substrate, the GaN stack comprising a GaN layer and an AlGaN barrier layer; and removing the GaN stack on the SiO2 surface by a chemical mechanical polishing process.

9. The method of claim 8, wherein the method further comprises: The GaN stack further comprises a GaN buffer layer disposed between the single-crystalline SiC layer and the GaN layer.

10. The method of claim 8, wherein the method further comprises: The GaN stack is deposited by performing a MOCVD epitaxial growth process comprising: forming a GaN nucleation layer at a temperature of 500-800 °C; and forming a GaN epitaxial layer at a temperature of 900-1100 °C. o C.

11. The method of claim 8, wherein the method further comprises: Precursors used for depositing the GaN stack include NH3 as a nitrogen source and an aluminum-containing, gallium-containing organic vapor material.

12. The method of claim 11 for the preparation of a wafer substrate of a patterned single crystal GaN / SiC / Si heterostructure, characterized by: The aluminum-containing organic vapor material is trimethylaluminum, and the gallium-containing organic vapor material is trimethylgallium.

13. A wafer substrate of a patterned single crystal GaN / SiC / Si heterostructure, characterized in that, The wafer substrate is prepared by the method of claim 8-12, and the wafer substrate comprises at least: a Si substrate, wherein a plurality of patterned unit regions are formed on the Si substrate, the plurality of unit regions are spaced apart from each other by a spacing region, and each unit region comprises: a single crystal SiC layer formed on the corresponding unit region; and a GaN stack comprising a GaN layer and an AlGaN barrier layer.

14. The wafer substrate of patterned single crystal GaN / SiC / Si heterostructure of claim 13, wherein: The GaN stack further comprises a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.

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