Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices having different configurations of contact structures and methods of manufacturing the same are disclosed. The method includes forming a first fin structure and a second fin structure on a substrate, forming n-type source / drain (S / D) regions and p-type S / D regions on the first fin structure and the second fin structure, respectively, forming first and second oxidation stop layers on the n-type S / D regions and the p-type S / D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers to first and second semiconductor oxide layers, respectively, forming a first silicon germanide layer on the p-type S / D regions, and forming a second silicon germanide layer on the first silicon germanide layer and the n-type S / D regions.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost continues to grow. To meet these demands, the semiconductor industry is constantly scaling down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and FinFETs. This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure on a substrate; forming an n-type source / drain (S / D) region and a p-type source / drain region on the first fin structure and the second fin structure, respectively; forming a first oxide stop layer and a second oxide stop layer on the n-type source / drain region and the p-type source / drain region, respectively; epitaxially growing a first semiconductor layer and a second semiconductor layer on the first oxide stop layer and the second oxide stop layer, respectively; converting the first semiconductor layer and the second semiconductor layer into a first semiconductor oxide layer and a second semiconductor oxide layer, respectively; forming a first silicon germanide layer on the p-type source / drain region; and forming a second silicon germanide layer on the first silicon germanide layer and the n-type source / drain region.

[0004] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure on a substrate; forming an n-type source / drain (S / D) region and a p-type source / drain region on the first fin structure and the second fin structure, respectively; depositing a silicide stop layer on the n-type source / drain region and the p-type source / drain region; forming a p-type work function metal (pWFM) silicide layer on the p-type source / drain region; and forming an n-type work function metal (nWFM) silicide layer on the p-type work function metal silicide layer and the n-type source / drain region.

[0005] Another embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first fin structure and a second fin structure disposed on the substrate; a stack of a first nanostructure layer disposed on a first portion of the first fin structure; a stack of a second nanostructure layer disposed on a first portion of the second fin structure; a first gate structure surrounding at least one of the first nanostructure layer; a second gate structure surrounding at least one of the second nanostructure layer; a first source / drain (S / D) region and a second source / drain region respectively disposed on a second portion of the first fin structure and the second fin structure; a first metal germanide layer disposed on the first source / drain region; a second metal germanide layer disposed on the first metal germanide layer and the second source / drain region; and a first contact plug and a second contact plug respectively disposed on the first metal germanide layer and the second metal germanide layer, wherein the metal of the first contact plug and the metal of the second contact plug are the same. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0008] Figure 1B and Figure 1C Cross-sectional views of semiconductor devices with different contact structures according to some embodiments are shown.

[0009] Figure 2 This is a flowchart of a method for manufacturing semiconductor devices with different contact structures according to some embodiments.

[0010] Figures 3A to 8B , Figure 8C , Figures 9A to 9C and Figures 10A to 16B Cross-sectional views of semiconductor devices with different contact structures at various stages of the semiconductor device manufacturing process, according to some embodiments, are shown.

[0011] Figure 8D and Figure 9D The device characteristics of a semiconductor device at various stages of the semiconductor device manufacturing process are illustrated according to some embodiments.

[0012] Figure 17 This is a flowchart of another method for manufacturing semiconductor devices with different contact structures, according to some embodiments.

[0013] Figures 18A to 24B Cross-sectional views of semiconductor devices with different contact structures at various stages of the semiconductor device manufacturing process, according to some embodiments, are shown.

[0014] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition itself does not indicate a relationship between the discussed embodiments and / or configurations.

[0016] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] It should be noted that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include a specific component, structure, or feature; however, each embodiment may not necessarily include that specific component, structure, or feature. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific component, structure, or feature is described in connection with an embodiment, whether explicitly described or not, implementing such a component, structure, or feature in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology used herein should be interpreted by those skilled in the art based on the teachings herein.

[0019] In some embodiments, the terms “about” and “substantially” may refer to a value that varies by a given amount within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. The terms “about” and “substantially” may refer to a percentage of the value as interpreted by one of skill in the art based on the teachings herein.

[0020] The fin structures disclosed herein can be patterned using any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0021] This invention provides an example semiconductor device having a FET (e.g., a finFET) (having source / drain (S / D) contact structures that are different from each other), and an example method for forming such a contact structure with a silicide stop layer. This example method forms arrays of n-type S / D regions and p-type S / D regions on the fin structures of the n-type FET (NFET) and p-type FET (PFET) of the semiconductor device, respectively. In some embodiments, the contact structure on the n-type S / D region has a silicide layer (also referred to herein as a "silicongeroxide layer" unless otherwise stated) that is different from the silicide layer of the contact structure on the p-type S / D region.

[0022] The contact resistance between the S / D region and the S / D contact structure is proportional to the Schottky barrier height (SBH) between the material of the S / D region and the silicide layer of the S / D contact structure. For an n-type S / D region, reducing the difference between the work function of the silicide layer and the conduction band energy of the n-type material in the S / D region can reduce the SBH between the n-type S / D region and the S / D contact structure. Conversely, for a p-type S / D region, reducing the difference between the work function of the silicide layer and the valence band energy of the p-type material in the S / D region can reduce the SBH between the p-type S / D region and the S / D contact structure. In some embodiments, since the S / D regions of the NFET and PFET are formed with corresponding n-type and p-type materials, the S / D contact structures of the NFET and PFET are formed with different silicide layers to reduce the contact resistance between the different materials of the S / D contact structure and the S / D region.

[0023] In some embodiments, the NFET S / D contact structure is formed with an n-type work function metal (nWFM) silicide layer (e.g., titanium germanide silicide), the work function of which is closer to the conduction band energy than the valence band energy of the n-type S / D region. Conversely, the PFET S / D contact structure is formed with a p-type WFM (pWFM) silicide layer (e.g., nickel germanide silicide or cobalt germanide silicide), the work function of which is closer to the valence band energy than the conduction band energy of the p-type S / D region. The nWFM silicide layer may be formed by a silicide reaction (or a silicide and germanide reaction) between the n-type S / D region and the nWFM layer disposed on the n-type S / D region. The pWFM silicide layer may be formed by a silicide reaction (or a silicide and germanide reaction) between the p-type S / D region and the pWFM layer disposed on the p-type S / D region.

[0024] In some embodiments, the method of selectively forming a pWFM silicide layer on a p-type S / D region includes forming a silicide stop layer on the n-type S / D region before depositing the pWFM layer on the n-type S / D region and the p-type S / D region. The silicide stop layer prevents silicide reaction between the pWFM layer and the n-type S / D region. In some embodiments, forming the silicide stop layer on the n-type S / D region may include depositing or epitaxially growing a semiconductor material (e.g., silicon or silicon germanium (SiGe)) and an oxide semiconductor material on the n-type S / D region. The semiconductor material has stronger chemical bonds with oxygen atoms than with the metal atoms of the pWFM layer. As a result, the oxidized semiconductor material of the silicide stop layer does not react with the metal of the pWFM layer and prevents chemical interaction between the metal of the pWFM layer and the n-type S / D region beneath the silicide stop layer. In some embodiments, an oxide stop layer may be deposited or epitaxially grown between the silicide stop layer and the n-type S / D region to protect the material of the n-type S / D region from oxidation during the formation of the silicide stop layer.

[0025] Figure 1A An isometric view of a semiconductor device 100 having an NFET 102N and a PFET 102P according to some embodiments is shown. Figure 1B It shows along Figure 1A A cross-sectional view of the NFET 102N with line AA. Figure 1C It shows along Figure 1A A cross-sectional view of the PFET 102P of the line BB. Figure 1B and Figure 1C A cross-sectional view of semiconductor device 100 is shown, wherein, for simplicity, details are not shown. Figure 1A Additional structures are shown below. Unless otherwise stated, the discussion of NFET 102N and PFET 102P devices with the same designation applies to each other.

[0026] refer to Figure 1A The NFET 102N may include an array of gate structures 112N disposed on the fin structure 106N, and the PFET 102P may include an array of gate structures 112P disposed on the fin structure 106P. The NFET 102N may also include a stack of nanostructured channel regions 121 surrounded by the gate structures 112N and an S / D region 110N disposed on the portion of the fin structure 106N not covered by the gate structures 112N. Figure 1A An array of S / D regions 110N (visible in the image). Similarly, the PFET 102P may also include a stack of nanostructured channel regions 121 surrounded by gate structure 112P and epitaxial S / D regions 110P disposed on the portion of fin structure 106P not covered by gate structure 112P (in the image). Figure 1A An array of S / D regions 110P (visible in the image). As used herein, the term “nanostructure” defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm (e.g., about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm).

[0027] The semiconductor device 100 may further include a gate spacer 114, a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an interlayer dielectric (ILD) layer 118. The ILD layer 118 may be disposed on the ESL 117. The ESL 117 may be configured to protect gate structures 112N and 112P and / or S / D regions 110N and 110P. In some embodiments, the gate spacer 114, the STI region 116, the ESL 117, and the ILD layer 118 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and silicon germanium oxide.

[0028] Semiconductor device 100 may be formed on substrate 104, wherein NFET 102N and PFET 102P are formed on different regions of substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed between NFET 102N and PFET 102P on substrate 104. Substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, substrate 104 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, fin structures 106N-106P may comprise a material similar to substrate 104 and extend along the X-axis.

[0029] refer to Figures 1B to 1CThe NFET 102N and PFET 102P may include a stack of nanostructured channel region 121, gate structure 112N-112P, S / D region 110N-110P, and S / D contact structure 120N-120P disposed on the S / D region 110N-110P.

[0030] In some embodiments, the nanostructured channel region 121 may comprise a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructured channel region 121 may comprise Si, SiAs, silicon phosphide (SiP), SiC, SiCP, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), group III-V semiconductor compounds, or other suitable semiconductor materials. Although a rectangular cross-section of the nanostructured channel region 121 is shown, the nanostructured channel region 121 may have cross-sections of other geometries (e.g., circular, elliptical, triangular, or polygonal).

[0031] In some embodiments, gate structures 112N-112P may be multilayer structures and may surround each of the nanostructured channel regions 121, thereby gate structures 112N-112P may be referred to as a "gate all-around (GAA) structure" or a "horizontal gate all-around (HGAA) structure". NFET 102N may be referred to as "GAA FET 102N" or "GAA NFET 102N", and PFET 102N may be referred to as "GAA FET 102P" or "GAA PFET 102P". A portion of gate structures 112N-112P surrounding the nanostructured channel regions 121 may be electrically isolated from adjacent S / D regions 110N-110P by internal spacers 113. Internal spacers 113 may comprise a material similar to gate spacers 114. In some embodiments, NFET 102N and PFET 102P may be finFETs and have fin regions (not shown) instead of nanostructured channel regions 121.

[0032] In some embodiments, each of the gate structures 112N-112P may include an interface oxide (IO) layer 122, a high-k (HK) gate dielectric layer 124 disposed on the IO layer 122, a power function metal (WFM) layer 126 disposed on the HK gate dielectric layer 124, a gate metal fill layer 128 disposed on the WFM layer 126, a conductive capping layer 130 disposed on the HK gate dielectric layer 124, the WFM layer 126 and the gate metal fill layer 128, and an insulating capping layer 132 disposed on the conductive capping layer 130.

[0033] IO layer 122 may include silicon oxide (SiO2) and silicon germanium oxide (SiGeO)x or germanium oxide (GeO) x The HK gate dielectric layer 124 may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). The WFM layer 126 of the gate structure 112N may include aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, combinations thereof, or other suitable Al substrate materials. The WFM layer 126 of the gate structure 112P may comprise a substantially aluminum-free (e.g., no aluminum) titanium-based or tantalum-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof. The gate metal fill layer 128 may comprise a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0034] The insulating capping layer 132 protects the underlying conductive capping layer 130 from structural and / or compositional degradation during subsequent processing of the semiconductor device. In some embodiments, the insulating capping layer 132 may comprise a nitride material (such as silicon nitride) and may have a thickness of about 5 nm to about 10 nm to adequately protect the underlying conductive capping layer 130.

[0035] The conductive capping layer 130 provides a conductive interface between the gate metal fill layer 128 and the gate contact structure (not shown) to electrically connect the gate metal fill layer 128 to the gate contact structure without forming the gate contact structure directly above or within the gate metal fill layer 128. The gate contact structure is not formed directly above or within the gate metal fill layer 128 to prevent contamination caused by any processing materials used to form the gate contact structure. Contamination of the gate metal fill layer 128 can lead to device performance degradation. Therefore, by using the conductive capping layer 130, the gate structures 112N-112P can be electrically connected to the gate contact structures without compromising the integrity of the gate structures 112N-112P.

[0036] In some embodiments, the conductive capping layer 130 may have a thickness of about 4 nm to about 5 nm to adequately provide a conductive interface between the gate metal fill layer 128 and the gate contact structure without compromising device size and manufacturing cost. In some embodiments, to adequately protect the underlying conductive capping layer 130, the ratio between the thickness of the conductive capping layer 130 and the thickness of the insulating capping layer 132 may be in the range of about 1:1 to about 1:2. In some embodiments, the conductive capping layer 130 may comprise a metallic material such as W, Ru, Ir, Mo, other suitable metallic materials, and combinations thereof. In some embodiments, the conductive capping layer 130 may be formed using a precursor gas of tungsten pentachloride (WCl5) or tungsten hexachloride (WCl6), and therefore, the conductive capping layer 130 may comprise tungsten with chlorine atom impurities. The concentration of chlorine atom impurities may be in the range of about 1 atomic percent to about 10 atomic percent of the total concentration of atoms in each conductive capping layer 130.

[0037] refer to Figure 1B The S / D region 110N may include a stack of epitaxial layers—a lightly doped (LD) n-type layer (not shown) epitaxially grown on the fin structure 106N and a heavily doped (HD) n-type layer (not shown) epitaxially grown on the LD n-type layer. In some embodiments, the LD n-type layer and the HD n-type layer may include an epitaxially grown semiconductor material (such as silicon) and an n-type dopant (such as phosphorus and other suitable n-type dopant). The LD n-type layer may include materials from about 10 15 atoms / cm 3 To about 10 18 atoms / cm 3 The doping concentration is within the range of approximately 10, which is lower than the doping concentration of the HD n-type layer. 19 atoms / cm 3 To about 10 23 atoms / cm 3 Within the range. In some embodiments, the HD n-type layer is thicker than the LD n-type layer.

[0038] refer to Figure 1C The S / D region 110P may include a stack of epitaxial layers—an LD p-type layer (not shown) epitaxially grown on the fin structure 106P and an HD p-type layer (not shown) epitaxially grown on the LD p-type layer. In some embodiments, the LD p-type layer and the HD p-type layer may include epitaxially grown semiconductor materials (such as SiGe) and p-type dopants (such as boron and other suitable p-type dopants). The LD p-type layer may include materials from about 10 15 atoms / cm 3 To about 10 18 atoms / cm3 The doping concentration is within the range of approximately 10, which is lower than the doping concentration of the HD p-type layer. 19 atoms / cm 3 To about 10 23 atoms / cm 3 Within the range. In some embodiments, the LD p-type layer may include a Ge concentration ranging from about 5 atomic percent to about 45 atomic percent, which is lower than the Ge concentration of the HD p-type layer, which may have a Ge concentration ranging from about 50 atomic percent to about 80 atomic percent. In some embodiments, the HD p-type layer is thicker than the LD p-type layer.

[0039] refer to Figure 1B An S / D contact structure 120N is disposed on an S / D region 110N. In some embodiments, the S / D contact structure 120N may include (i) an nWFM silicide layer 134N (also referred to as "nWFM silicide-germanium layer 134N") disposed on the S / D region 110N, and (ii) a contact plug 136N disposed on the nWFM silicide layer 134N. In some embodiments, the nWFM silicide layer 134N may include a metal or a metal silicide-germanium compound, wherein the work function of the metal or the metal silicide-germanium compound is closer to the conduction band edge energy than the valence band edge energy of the material of the S / D region 110N. For example, the metal or metal germanium silicon may have a work function of less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which can be closer to the conduction band energy (e.g., 4.1 eV for Si or 3.8 eV for Si) than the valence band energy of the Si-based or SiGe-based material in the S / D region 110N (e.g., 5.2 eV for Si or 4.8 eV for SiGe). In some embodiments, the metal germanium silicon of the nWFM silicide layer 134N may include titanium germanium silicon (Ti). x Si y Ge z ), tantalum germanide (Ta x Si y Ge z ), molybdenum silicon germanium (Mo x Si y Ge z ), zirconium silicate germanide (Zr) x Si y Ge z ), hafnium silicate (Hf) x Si y Ge z Scandium germanide (Sc) x Si y Ge z ), Yttrium silicon germanium (Y x Siy Ge z ), terbium germanide (Tb) x Si y Ge z ), Lutetium silicon germanium (Lu x Si y Ge z Erbium silicate germanium (Er) x Si y Ge z Ytterbium silicate (Yb) x Si y Ge z Europium germanium silicon (Eu) x Si y Ge z ), Thorium germanium silicon (Th) x Si y Ge z ) or combinations thereof.

[0040] In some embodiments, the contact plug 136N may include conductive materials such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and combinations thereof.

[0041] refer to Figure 1C An S / D contact structure 120P is disposed on an S / D region 110P. In some embodiments, the S / D contact structure 120P may include (i) a pWFM silicide layer 131 (also referred to as "pWFM germanium silicon layer 131") disposed on the S / D region 110P, (ii) an nWFM silicide layer 134P (also referred to as "nWFM germanium silicon layer 134P") disposed on the pWFM silicide layer 131, and (iii) a contact plug 136P disposed on the nWFM silicide layer 134P. The height of the contact plug 136N along the Z-axis is greater than the height of the contact plug 136P along the Z-axis by approximately the thickness of the nWFM silicide layer 134P along the Z-axis. Unless otherwise stated, the discussion of the contact plug 136N applies to the contact plug 136P.

[0042] In some embodiments, the pWFM silicide layer 131 may include a metal or a metal germanide, the work function of which is closer to the valence band edge energy than the conduction band edge energy of the material of the S / D region 110P. For example, the metal or metal germanide may have a work function greater than 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which may be closer to the valence band energy (e.g., 5.2 eV for Si or 4.8 eV for Si) than the conduction band energy of the Si-based or SiGe substrate of the S / D region 110P (e.g., 4.1 eV for Si or 3.8 eV for SiGe). In some embodiments, the metal germanide of the pWFM silicide layer 131 may include nickel germanide (Ni x Si y Ge z ), cobalt germanide (Co) x Si y Ge z ), manganese germanide (Mn) x Si y Ge z ), tungsten germanide (W) x Si y Ge z ), Fe silicon germanium iron (Fe x Si y Ge z Rhodium germanium silicon (Rh) x Si y Ge z ), Palladium germanide (Pd) x Si y Ge z ), Ruthenium germanide (Ru x Si y Ge z Platinum silicon germanium (Pt) x Si y Ge z ), Iridium germanide (Ir) x Si y Ge z ), Os(silicongermium) x Si y Ge z (or combinations thereof). The metal germanium silicide of pWFM silicide layer 131 differs from the metal germanium silicide of nWFM silicide layers 134N-134P and may have a larger work function than that of nWFM silicide layers 134N-134P. In some embodiments, nWFM silicide layer 134P may be formed simultaneously with nWFM silicide layer 134N and may include a metal germanium silicide similar to that of nWFM silicide layer 134N.

[0043] Figure 2This is a flowchart of an example method 200 for manufacturing an NFET 102N and a PFET 102P semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to methods for manufacturing such... Figures 3A to 8B , Figure 8C , Figures 9A to 9C and Figure 10A and Figure 10B The example manufacturing processes of NFET 102N and PFET 102P are shown to describe... Figure 2 The operation shown. Figures 3A to 16A It is according to some embodiments along Figure 1A A cross-sectional view of the NFET 102N with line AA, and Figures 3B to 16B It is along the various stages of manufacturing. Figure 1A A cross-sectional view of the PFET 102P on line BB. Depending on the specific application, operations may be performed in a different order or not at all. It should be noted that method 200 may not produce complete NFET 102N and PFET 102P. Therefore, it is understood that additional processes may be provided before, during, and after method 200, and only a few other processes may be briefly described herein. The above describes a process with... Figures 1A to 1C The same label for the components in Figures 3A to 8B , Figures 8C to 8D , Figures 9A to 9D and Figures 10A to 16B The components in.

[0044] refer to Figure 2 In operation 205, a superlattice structure is formed on the fin structure, and a polycrystalline silicon structure is formed on the superlattice structure used for NFETs and PFETs. For example, as Figures 3A to 3B As shown, a superlattice structure 323 is formed on the fin structure 106N-106P, and a polycrystalline silicon structure 312N-312P is formed on the superlattice structure 323. The superlattice structure 323 may include nanostructure layers 121 and 321 arranged in an alternating configuration. In some embodiments, nanostructure layers 121 and 321 comprise different materials from each other. Nanostructure layer 321 is also referred to as sacrificial layer 321. During subsequent processing, the polycrystalline silicon structure 312N-312P and the sacrificial layer 321 can be replaced in a gate replacement process to form the gate structure 112N-112P.

[0045] refer to Figure 2 In operation 210, n-type S / D regions and p-type S / D regions are formed on the fin structure. For example, as... Figures 3A to 3B As shown, S / D regions 110N-110P are formed on the fin structure 106N-106P. In some embodiments, the S / D regions 110N-110P can be epitaxially grown on the fin structure 106N-106P. Figures 3A to 3BAs shown, internal spacers 113 can be formed in the superlattice structure 323 before forming the S / D regions 110N-110P. Figures 3A to 3B As shown, after forming the S / D region 110N-110P, ESL 117 and ILD layer 118 can be formed.

[0046] refer to Figure 2 In operation 215, the polysilicon structure and sacrificial layer are replaced with a gate structure. For example, as referenced... Figures 4A to 6B As described, the polysilicon structure 312N-312P and the sacrificial layer 321 are replaced with a gate structure 112N-112P. The formation of the gate structure 112N-112P may include the following sequential operations: (i) from Figures 3A to 3B The polysilicon structures 312N-312P and the sacrificial layer 321 are removed from the structure to form a gate opening (not shown), (ii) as Figures 4A to 4B As shown, an IO oxide layer 122 is formed within the gate opening, (iii) as Figures 4A to 4B As shown, an HK gate dielectric layer 124 is formed on the IO oxide layer 122, (iv) as Figures 4A to 4B As shown, a WFM layer 126 is formed on the HK gate dielectric layer 124, (v) as Figures 4A to 4B As shown, a gate metal fill layer 128 is formed on the WFM layer 126, (vi) as Figures 5A to 5B As shown, the gate spacer 114, HK gate dielectric layer 124, WFM layer 126 and gate metal fill layer are etched, (vii) as Figures 6A to 6B As shown, a conductive capping layer 130 is formed on the HK gate dielectric layer 124, the WFM layer 126, and the gate metal fill layer, (viii) as Figures 6A to 6B As shown, an insulating cover layer 132 is formed on the conductive cover layer 130.

[0047] refer to Figure 2 In operation 220, contact openings are formed in the n-type S / D region and the p-type S / D region. For example, as... Figures 7A to 7B As shown, by removing portions of ESL 117 and ILD layer 118, contact openings 740 are formed in the S / D regions 110N-110P. Figures 7A to 7B As shown, after forming the contact opening 740, a diffusion barrier layer 138 can be formed along the sidewalls of the contact opening 740. In some embodiments, the diffusion barrier layer 138 may include a dielectric nitride, such as silicon nitride (Si). x N ySilicon oxynitride (SiON), silicon carbonitride (SiCN), and other suitable dielectric nitride materials. The diffusion barrier layer 128 can prevent the oxidation of the subsequently formed contact plugs 136N-136P by preventing oxygen atoms from diffusing from adjacent structures to the contact plugs 136N-136P.

[0048] refer to Figure 2 In operation 225, oxidation stopping layers are formed on the n-type S / D region and the p-type S / D region. For example, as... Figures 8A to 8B As shown, an oxidation stop layer 842 is formed on the S / D regions 110N-110P. In some embodiments, the oxidation stop layer 842 can be formed by epitaxially growing a semiconductor material on the S / D regions 110N-110P. As described below, the semiconductor material of the oxidation stop layer 842 can prevent the underlying S / D regions 110N-110P from being oxidized during the oxidation process performed on the subsequently formed semiconductor layer 844. In some embodiments, the semiconductor material of the oxidation stop layer 842 can be substantially oxidation-resistant at the temperature used to oxidize the subsequently formed semiconductor layer 844. In some embodiments, the semiconductor material of the oxidation stop layer 842 may include silicon or other suitable semiconductor materials. In some embodiments, the oxidation stop layer 842 may have a thickness of about 1 nm to about 3 nm along the Z-axis. If the thickness of the oxidation stop layer 842 is less than 1 nm, the oxidation stop layer 842 may not be sufficient to prevent oxidation of the S / D regions 110N-110P. On the other hand, if the thickness of the oxide stop layer 842 is greater than 3 nm, the processing time for removing the oxide stop layer 842 increases, and thus increases the device manufacturing cost.

[0049] refer to Figure 2 In operation 230, a silicide stop layer is formed on the oxide stop layer. For example, as referenced... Figures 8A to 9D As described, a silicide stop layer 944 is formed on the oxide stop layer 842. In some embodiments, the formation of the silicide stop layer 944 may include the following sequential operations: (i) as Figures 8A to 8B As shown, a semiconductor layer 844 is epitaxially grown on the oxide stop layer 842, and (ii) the oxide layer is subjected to an oxidation temperature of 100°C to about 400°C. Figures 8A to 8B The structure undergoes a thermal oxidation process to form Figures 9A to 9B The structure of the oxide stop layer 842 is such that the semiconductor material is substantially non-oxidized at oxidation temperatures of 100°C to approximately 400°C (e.g., after a thermal oxidation process, the concentration of oxygen atoms in the oxide stop layer 842 is approximately 0 or approximately 0.01 atomic% to approximately 2 atomic%. As a result, the oxide stop layer 842 is substantially non-oxidized during the thermal oxidation process and prevents oxidation of the S / D regions 110N-110P.

[0050] In some embodiments, semiconductor layer 844 may comprise a semiconductor material capable of forming stronger chemical bonds with oxygen than with pWFM, such as nickel, cobalt, manganese, tungsten, iron, rhodium, palladium, ruthenium, platinum, iridium, and osmium. As a result, as described below, by oxidizing semiconductor layer 844 ( Figures 8A to 8B The siliconized stop layer 944 formed Figures 9A to 9B It does not react with the subsequently deposited pWFM layer 1231 to form pWFM silicide (e.g., pWFM silicide layer 131).

[0051] In some embodiments, the semiconductor layer 844 may comprise SiGe or other suitable semiconductor materials, and the silicide stop layer 944 may comprise an oxide of SiGe (e.g., SiGeO). x (or other suitable semiconductor materials). In some embodiments, as described below, SiGeO x It has stronger bonds with oxygen than with pWFM, and therefore does not break the chemical bonds with oxygen to substantially react with the subsequently deposited pWFM layer 1231 to form pWFM silicide in the S / D region 110N in operation 240 (e.g., the concentration of silicon atoms in the silicide stop layer 944 is equal to about 0 or about 0.01 atomic% to about 2 atomic%.

[0052] In some embodiments, Ge is used as an oxidation catalyst for oxidizing SiGe in semiconductor layer 844. In some embodiments, semiconductor layer 844 may have a Ge concentration of about 25 atomic% to about 55 atomic%. If the Ge concentration is less than 25 atomic%, the SiGe in semiconductor layer 844 may not be sufficiently oxidized during the thermal oxidation process. On the other hand, if the Ge concentration is greater than 55 atomic%, the complexity and processing time for epitaxially growing SiGe for semiconductor layer 844 increase, and thus increase the device manufacturing cost.

[0053] In some embodiments, the semiconductor layer 844 may have a thickness of approximately 2 nm to approximately 5 nm along the Z-axis and may be thicker than the oxidation stop layer 842. If the thickness of the semiconductor layer 844 is less than 2 nm, the silicide stop layer 944 formed after the oxidation of the semiconductor layer 844 may not be thick enough to prevent the formation of pWFM silicide in the S / D region 110N. On the other hand, if the thickness of the semiconductor layer 844 is greater than 5 nm, the duration of the thermal oxidation process increases, and thus the device manufacturing cost increases.

[0054] In some embodiments, the silicide stop layer 944 may have a thickness of about 10 nm to about 30 nm along the Z-axis, and may be thicker than the oxide stop layer 842. If the thickness of the silicide stop layer 944 is less than 10 nm, the silicide stop layer 944 may not be sufficient to prevent the formation of pWFM silicide in the S / D region 110N. On the other hand, if the thickness of the silicide stop layer 944 is greater than 30 nm, the processing time for removing the silicide stop layer 944 increases, and thus the device manufacturing cost increases.

[0055] Figure 8C This illustrates the process prior to performing a thermal oxidation process on the SiGe semiconductor layer 844. Figures 8A to 8B Enlarged view of part 843 of the structure. Figure 8D It shows the span Figure 8C The Si concentration distribution of the line CC is 850 and the Ge concentration distribution is 854. Figure 9C This illustrates the process following the thermal oxidation of the SiGe semiconductor layer 844 to form a silicon stop layer 944. Figures 9A to 9B A magnified view of part 943 of the structure. Due to the preferential oxidation of Si over Ge, Ge atoms in semiconductor layer 844 are pushed to the bottom of semiconductor layer 844 during the thermal oxidation process. As a result, in some embodiments, after the oxidation of semiconductor layer 844 having SiGe, silicide stop layer 944 can be formed having silicon oxide (SiO2). x The top layer of 946 and SiGeO x The underlying 948 (e.g.) Figure 9C (As shown).

[0056] In some embodiments, such as Figure 9D As shown, Ge atoms in semiconductor layer 844 are also pushed onto the top of oxide stop layer 842 and S / D region 110N-110P. Figure 9D It shows the span Figure 9C The Si concentration distribution (950), oxygen concentration distribution (952), and Ge concentration distribution (954) of the line DD are shown. These can be compared... Figure 8D and Figure 9D The Ge concentration distributions at 854 and 954 were used to observe the migration of Ge atoms during the oxidation of the SiGe semiconductor layer 844. Figure 8D As shown, prior to the thermal oxidation process, semiconductor layer 844 has a higher Ge concentration than oxidation stop layer 842 and S / D regions 110N-110P. Figure 9D As shown, after the thermal oxidation process, the Ge concentration in semiconductor layer 844 decreases, while the Ge concentration in oxidation stop layer 842 and S / D regions 110N-110P increases.

[0057] refer to Figure 2In operation 235, p-type dopant is implanted into the p-type S / D region. For example, as... Figures 10A to 10B As shown, a p-type dopant 1058, such as boron, is implanted into the S / D region 110P. The p-type dopant implantation process may include the following sequential operations: (i) as Figure 10A As shown, a masking layer 1056 is formed on the NFET 102N, and (ii) a p-type dopant 1058 is used to mask the NFET 102N. Figures 10A to 10B Ion implantation is performed on the structure. In some embodiments, approximately 10T ions can be implanted into the S / D region 110P. 20 atoms / cm 3 To about 10 21 atoms / cm 3 The concentration of p-type dopant.

[0058] refer to Figure 2 In operation 240, a pWFM silicide layer is selectively formed on the p-type S / D region. For example, as referenced... Figures 11A to 14B As described, a pWFM silicide layer 131 is selectively formed on the S / D region 110P. The selective formation of the pWFM silicide layer 131 may include the following sequential operations: (i) as Figure 11B As shown, for Figures 10A to 10B The structure is subjected to an etching process (e.g., etching with dilute hydrofluoric acid) to remove... Figure 10B (ii) in the structure removal of oxide stop layer 842 and silicide stop layer 944, (ii) in from Figure 11A After removing the masking layer 1056 from the structure, Figures 11A to 11B Depositing pWFM layers 1231 on the structure to form Figures 12A to 12B The structure, and (iii) such as Figure 13B As shown, at a temperature of approximately 400°C to approximately 500°C... Figures 12A to 12B The structure is subjected to an annealing process to initiate a silicide reaction between the bottom of the S / D region 110P and the pWFM layer 1231 to form the pWFM silicide layer 131.

[0059] In some embodiments, the pWFM layer 1231 may include a work function value that is closer to the valence band edge energy than the conduction band edge energy of the material in the S / D region 110P. For example, the pWFM layer 1231 may include a metal with a work function value greater than 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which may be closer to the valence band energy (5.2 eV for Si or 4.8 eV for SiGe) than the conduction band energy (4.1 eV for Si or 3.8 eV for SiGe) of the S / D region 110P. In some embodiments, the pWFM layer 1231 may include Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, or combinations thereof. In some embodiments, the metal of the pWFM layer 1231 reacts with Si atoms in the S / D region 110P and Ge atoms pushed into the S / D region 110P during the thermal oxidation process in operation 230. As a result, in some embodiments, the pWFM silicide layer 131 may include a metal silicide-germanium compound (an alloy of metal silicide and metal germanium compound).

[0060] The deposition of the pWFM layer 1231 may include depositing a pWFM layer of about 0.5 nm to about 5 nm thickness using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process at a temperature ranging from about 160 °C to about 220 °C and a pressure ranging from about 5 Torr to about 10 Torr. In some embodiments, the ALD process may include about 10 to several hundred cycles, wherein one cycle may include the following sequential cycle: (i) flow of a mixture of metal precursor, reactant, and carrier gas and (ii) a gas purge process lasting from about 3 seconds to about 15 seconds. In some embodiments, the reactant gas may include ammonia (NH3), the carrier gas may include nitrogen or argon, and the purge gas may include an inert gas.

[0061] A portion of the pWFM layer 1231 on the S / D region 110N does not react with the silicide stop layer 944 and / or the material of the S / D region 110N to form a metal silicide, because the silicide stop layer 944 on the S / D region 110N prevents the pWFM layer 1231 from reacting with the silicide stop layer 944 and / or the material of the S / D region 110N. The silicon-oxygen (Si-O) bonds in the silicide stop layer 944 do not break at silicide temperatures of about 400°C to about 500°C, and therefore, the silicon atoms in the silicide stop layer 944 do not react with the metal of the pWFM layer 1231 to form a metal silicide.

[0062] In some embodiments, after forming the pWFM silicide layer 131, the unreacted portions of the pWFM layer 1231, the oxidation stop layer 842, and the silicide stop layer 944 can be removed by a wet etching process to form Figures 14A to 14B The structure.

[0063] refer to Figure 2In operation 245, an nWFM silicide layer is formed on the n-type S / D region and the pWFM silicide layer. For example, as referenced... Figures 15A to 16B As described, nWFM silicide layers 134N and 134P are formed on the S / D region 110N and the pWFM silicide layer 131, respectively. The formation of the nWFM silicide layers 134N-134P may include the following sequential operations: (i) in Figures 14A to 14B (ii) depositing nWFM layer 1534 on the structure, and (ii) subjecting to temperature of about 400°C to about 500°C. Figures 15A to 15B The structure undergoes an annealing process. The annealing process can initiate a silicide reaction between (i) the bottom of the S / D region 110N and the nWFM layer 1534 to form the nWFM silicide layer 134N, as... Figure 16A As shown, and (ii) the silicide reaction between the bottom of the nWFM layer 1534 and the S / D region 110P through the pWFM silicide layer 131 to form the nWFM silicide layer 134P, as Figure 16B As shown.

[0064] In some embodiments, the deposition of the nWFM layer 1534 may include depositing a metal using a CVD or ALD process at a temperature ranging from about 300°C to about 500°C, the work function of which is closer to the conduction band edge energy than the valence band edge energy of the material in the S / D region 110N. For example, the nWFM layer 1534 may include a metal with a work function less than 4.5 eV (e.g., from about 3.5 eV to about 4.4 eV), which may be closer to the conduction band energy (4.1 eV for Si or 3.8 eV for SiGe) than the valence band energy (5.2 eV for Si or 4.8 eV for SiGe) of the S / D region 110N. In some embodiments, the nWFM layer 1534 may include Ti, Ta, Mo, Zr, Hf, Sc, Y, Ho, Tb, Gd, Lu, Dy, Er, Yb, or combinations thereof. In some embodiments, the metal of the nWFM layer 1534 reacts with Si atoms in the S / D region 110N and Ge atoms pushed into the S / D region 110N during the thermal oxidation process in operation 230. As a result, in some embodiments, the nWFM silicide layer 134N may include a metal silicide-germanium compound (an alloy of metal silicide and metal germanium compound).

[0065] In some embodiments, such as Figures 16A to 16B As shown, after forming the nWFM silicide layer 134N-134P, the unreacted portion of the nWFM layer 1534 can be removed by a wet etching process.

[0066] refer to Figure 2 In operation 250, a contact plug is formed within the first contact opening and the second contact opening. For example, as... Figures 16A to 16BAs shown, contact plugs 136N-136P are formed within the contact opening 740.

[0067] Figure 17 This is a flowchart of another example method 1700 for manufacturing an NFET 102N and a PFET 102P semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to methods for manufacturing such... Figures 3A to 7B and Figures 18A to 24B The example manufacturing processes of NFET 102N and PFET 102P are shown to describe... Figure 17 The operation shown is illustrated. Figures 3A to 7A and Figures 18A to 24A It is along the various stages of manufacturing according to some embodiments. Figure 1A A cross-sectional view of the NFET102N with line AA, and Figures 3B to 7B and Figures 18B to 24B It is along Figure 1A A cross-sectional view of the PFET 102P on line BB. Depending on the specific application, operations may be performed in a different order or not at all. It should be noted that method 1700 may not produce complete NFET 102N and PFET 102P. Therefore, it is understood that additional processes may be provided before, during, and after method 1700, and only a few other processes may be briefly described herein. The above describes a process with... Figures 1A to 1C and Figures 3A to 16B The same label for the components in Figures 18A to 24B The components in.

[0068] refer to Figure 17 Operations 1705-1720 are similar to operations 205-220, respectively. For example... Figures 18A to 18B As shown, after operation 1720, a result similar to Figures 7A to 7B The structure.

[0069] refer to Figure 17 In operation 1725, a silicide stop layer is deposited in the contact opening. For example, as... Figures 19A to 19B As shown, a siliconization stop layer 1964 is deposited in the contact opening 740. In some embodiments, the siliconization stop layer 1964 may comprise an oxide of a semiconductor material, such as SiO2. x And it can be deposited using an ALD process. In some embodiments, the silicide stop layer 1964 may have a thickness of about 2 nm to about 10 nm along the Z-axis. If the thickness of the silicide stop layer 1964 is less than 2 nm, the silicide stop layer 1964 may be insufficient to prevent the formation of pWFM silicide in the S / D region 110N. On the other hand, if the thickness of the silicide stop layer 1964 is greater than 10 nm, the processing time for depositing and removing the silicide stop layer 1964 increases, and thus increases the device manufacturing cost.

[0070] refer to Figure 17 In operation 1730, p-type dopant is implanted into the p-type S / D region. For example, as... Figures 20A to 20B As shown, a p-type dopant 1058, such as boron, is implanted into the S / D region 110P. The p-type dopant implantation process may include the following sequential operations: (i) as Figure 20A As shown, a masking layer 2066 is formed on the NFET 102N, and (ii) a p-type dopant 1058 is used to mask the NFET 102N. Figures 20A to 20B Ion implantation is performed on the structure. In some embodiments, approximately 10T ions can be implanted into the S / D region 110P. 20 atoms / cm 3 To about 10 21 atoms / cm 3 The concentration of p-type dopant.

[0071] refer to Figure 17 In operation 1735, a pWFM silicide layer is selectively formed on the p-type S / D region. For example, as referenced... Figures 21A to 23B As described, a pWFM silicide layer 131 is selectively formed on the S / D region 110P. The selective formation of the pWFM silicide layer 131 may include the following sequential operations: (i) for Figures 20A to 20B The structure is subjected to an etching process (e.g., etching with dilute hydrofluoric acid) to remove... Figure 20B The structure removes a portion of the siliconized stop layer in 1964 to form Figure 21B The structure, (ii) from Figure 21A After removing the masking layer 2066 from the structure, Figures 21A to 21B Depositing pWFM layers 1231 on the structure to form Figures 22A to 22B The structure, and (iii) such as Figure 23B As shown, at a temperature of approximately 400°C to approximately 500°C... Figures 22A to 22B The structure is subjected to an annealing process to initiate a silicide reaction between the bottom of the S / D region 110P and the pWFM layer 1231 to form the pWFM silicide layer 131.

[0072] A portion of the pWFM layer 1231 on the S / D region 110N does not react with the silicide stop layer 1964 and / or the material of the S / D region 110N to form a metal silicide, because the silicide stop layer 1964 on the S / D region 110N prevents the pWFM layer 1231 from reacting with the silicide stop layer 1964 and / or the material of the S / D region 110N. The silicon-oxygen (Si-O) bonds in the silicide stop layer 1964 do not break at silicide temperatures of about 400°C to about 500°C, and therefore, the silicon atoms in the silicide stop layer 1964 do not react with the metal of the pWFM layer 1231 to form a metal silicide.

[0073] In some embodiments, after forming the pWFM silicide layer 131, the unreacted portions of the pWFM layer 1231 and the silicide stop layer 1964 can be removed by a wet etching process to form Figures 23A to 23B The structure.

[0074] refer to Figure 17 Operations 1740-1745 are similar to operations 245-250, respectively. After operation 1750, the following is formed: Figures 24A to 24B The structure.

[0075] In some embodiments, unlike the nWFM silicide layer 134N formed in method 200, the nWFM silicide layer 134N formed in method 1700 does not include metal germanide. The silicide stop layer 1964 does not include Ge atoms, and therefore Ge atoms are not introduced from the silicide stop layer 1964 into the S / D region 110N, whereas in operation 230 of method 200, Ge atoms can be introduced from the silicide stop layer 944 into the S / D region 110N. In some embodiments, the nWFM silicide layer 134N may include metal silicides, such as titanium silicide (Ti). x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y Zirconium silicide (Zr) x Si y ), Hafnium silicide (Hf) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si y ) or combinations thereof.

[0076] This invention provides an example semiconductor device having FETs (e.g., GAA FET 102N-102P) (having source / drain (S / D) contact structures that are different from each other), and an example method for forming such a contact structure with a silicide stop layer. This example method forms arrays of n-type S / D regions and p-type S / D regions, respectively, on the fin structures of the n-type FET (NFET) and p-type FET (PFET) of the semiconductor device. In some embodiments, the contact structure on the n-type S / D region has a silicide layer (also referred to herein as a "silicongeroxide layer") that is different from the silicide layer of the contact structure on the p-type S / D region, unless otherwise stated.

[0077] In some embodiments, a pWFM silicide layer (e.g., pWFM silicide layer 131) of a PFET S / D contact structure (e.g., contact structure 120P) is selectively formed on a p-type S / D region (e.g., S / D region 110P). Conversely, an nWFM silicide layer (e.g., nWFM silicide layer 134N) of an NFET S / D contact structure (e.g., contact structure 120N) is formed on an n-type S / D region (e.g., S / D region 110N) and a pWFM silicide layer. The pWFM silicide layer may be formed by a silicide reaction between the p-type S / D region and a pWFM layer (e.g., pWFM layer 1231) disposed on the p-type S / D region. The nWFM silicide layer may be formed by a silicide reaction between the n-type S / D region and an nWFM layer (e.g., nWFM layer 1534) disposed on the n-type S / D region and the pWFM silicide layer.

[0078] In some embodiments, the method of selectively forming a pWFM silicide layer on a p-type S / D region (e.g., methods 200 and 1700) includes forming a silicide stop layer (e.g., silicide stop layers 944 and 964) on the n-type S / D region before depositing the pWFM layer on the n-type S / D region and the p-type S / D region. The silicide stop layer can prevent silicide reaction between the pWFM layer and the n-type S / D region. In some embodiments, forming a silicide stop layer on the n-type S / D region may include depositing or epitaxially growing a semiconductor material (e.g., semiconductor layer 844) and oxidizing the semiconductor material on the n-type S / D region. The semiconductor material has stronger chemical bonds with oxygen atoms than with the metal atoms of the pWFM layer. As a result, the oxidized semiconductor material of the silicide stop layer does not react with the metal of the pWFM layer and prevents chemical interaction between the metal of the pWFM layer and the n-type S / D region beneath the silicide stop layer. In some embodiments, an oxide stop layer (e.g., oxide stop layer 842) may be deposited or epitaxially grown between the silicide stop layer and the n-type S / D region to protect the material in the n-type S / D region from oxidation during the formation of the silicide stop layer.

[0079] In some embodiments, a method includes forming a first fin structure and a second fin structure on a substrate, forming an n-type source / drain (S / D) region and a p-type source / drain (S / D) region on the first fin structure and the second fin structure, forming a first oxide stop layer and a second oxide stop layer on the n-type S / D region and the p-type S / D region, epitaxially growing a first semiconductor layer and a second semiconductor layer on the first oxide stop layer and the second oxide stop layer, converting the first semiconductor layer and the second semiconductor layer into a first semiconductor oxide layer and a second semiconductor oxide layer, forming a first silicon germanide layer on the p-type S / D region, and forming a second silicon germanide layer on the first silicon germanide layer and the n-type S / D region.

[0080] In some embodiments, forming the first oxide stop layer and the second oxide stop layer includes epitaxially growing silicon layers on the n-type source / drain region and the p-type source / drain region.

[0081] In some embodiments, the epitaxial growth of the first semiconductor layer and the second semiconductor layer includes epitaxial growth of a silicon-germanium (SiGe) layer on the first oxide stop layer and the second oxide stop layer.

[0082] In some embodiments, converting the first semiconductor layer and the second semiconductor layer into a first semiconductor oxide layer and the second semiconductor oxide layer includes performing a thermal oxidation process on the first semiconductor layer and the second semiconductor layer.

[0083] In some embodiments, converting the first semiconductor layer into a first semiconductor oxide layer includes converting a first portion of the first semiconductor layer into silicon oxide (SiO2). x The first semiconductor layer is converted into silicon germanium oxide (SiGeO) layer, and the second portion of the first semiconductor layer is converted into silicon germanium oxide (SiGeO). x )layer.

[0084] In some embodiments, forming the first silicon germanide layer includes removing the second semiconductor oxide layer.

[0085] In some embodiments, forming the first silicon germanium compound layer includes removing the second oxidation stopping layer.

[0086] In some embodiments, forming the first silicon germanium compound layer includes depositing a p-type work function metal (pWFM) layer on the first semiconductor oxide layer and on the p-type source / drain regions.

[0087] In some embodiments, forming a second silicon germanide layer includes depositing an n-type work function metal (nWFM) layer on the first silicon germanide layer and on the n-type source / drain regions.

[0088] In some embodiments, the method further includes performing p-type dopant implantation on the second semiconductor oxide layer.

[0089] In some embodiments, a method includes forming a first fin structure and a second fin structure on a substrate, forming an n-type source / drain (S / D) region and a p-type source / drain (S / D) region on the first fin structure and the second fin structure, respectively, depositing a silicide stop layer on the n-type S / D region and the p-type S / D region, forming a p-type work function metal (pWFM) silicide layer on the p-type S / D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and the n-type S / D region.

[0090] In some embodiments, depositing a silicide stop layer includes depositing a semiconductor oxide layer or a silicon oxide layer on the n-type source / drain region and the p-type source / drain region.

[0091] In some embodiments, the method further includes: forming a first stack of alternating first and second nanostructure layers on a first fin structure, wherein the first and second nanostructure layers comprise different semiconductor materials; and forming a second stack of alternating third and fourth nanostructure layers on a second fin structure, wherein the third and fourth nanostructure layers comprise different semiconductor materials.

[0092] In some embodiments, the method further includes performing p-type dopant implantation on a portion of the silicide stop layer on the p-type source / drain region.

[0093] In some embodiments, forming a p-type power function metal silicide layer includes removing a portion of the silicide stop layer on the p-type source / drain regions.

[0094] In some embodiments, forming an n-type power function metal silicide layer includes removing a portion of the silicide stop layer on the n-type source / drain regions.

[0095] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure disposed on the substrate; a first gate structure and a second gate structure disposed on the first fin structure and the second fin structure, respectively; a first source / drain (S / D) region and a second source / drain (S / D) region disposed on the first fin structure and the second fin structure, respectively; a first metal germanide layer disposed on the first S / D region; a second metal germanide layer disposed on the first metal germanide layer and the second S / D region; and a first contact plug and a second contact plug disposed on the first metal germanide layer and the second metal germanide layer, respectively, wherein the metal of the first contact plug is the same as the metal of the second contact plug.

[0096] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure disposed on the substrate; a stack of first nanostructure layers disposed on a first portion of the first fin structure; a stack of second nanostructure layers disposed on a first portion of the second fin structure; a first gate structure surrounding at least one of the first nanostructure layers; a second gate structure surrounding at least one of the second nanostructure layers; a first source / drain (S / D) region and a second source / drain region respectively disposed on a second portion of the first fin structure and the second fin structure; a first metal germanide layer disposed on the first source / drain region; a second metal germanide layer disposed on the first metal germanide layer and the second source / drain region; and a first contact plug and a second contact plug respectively disposed on the first metal germanide layer and the second metal germanide layer, wherein the metal of the first contact plug is the same as the metal of the second contact plug.

[0097] In some embodiments, the metal of the first metal germanide layer is different from the metal of the second metal germanide layer.

[0098] In some embodiments, the first metal germanide layer comprises a p-type work function metal (pWFM) germanide layer.

[0099] In some embodiments, the second metal germanium silicon layer comprises an n-type work function metal (nWFM) germanium silicon layer.

[0100] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate; An n-type source / drain (S / D) region and a p-type source / drain region are formed on the first fin structure and the second fin structure, respectively; A first oxidation stop layer and a second oxidation stop layer are formed on the n-type source / drain region and the p-type source / drain region, respectively; A first semiconductor layer and a second semiconductor layer are epitaxially grown on the first oxidation stop layer and the second oxidation stop layer, respectively; The first semiconductor layer and the second semiconductor layer are respectively converted into a first semiconductor oxide layer and a second semiconductor oxide layer; A first silicon-germanium oxide layer is formed on the p-type source / drain region; as well as A second silicon germanium layer is formed on the first silicon germanium layer and on the n-type source / drain region.

2. The method according to claim 1, wherein, Forming the first oxide stop layer and the second oxide stop layer involves epitaxially growing silicon layers on the n-type source / drain region and the p-type source / drain region.

3. The method according to claim 1, wherein, Epitaxial growth of the first semiconductor layer and the second semiconductor layer includes epitaxial growth of silicon-germanium (SiGe) layers on the first oxidation stop layer and the second oxidation stop layer.

4. The method according to claim 1, wherein, Converting the first semiconductor layer and the second semiconductor layer into the first semiconductor oxide layer and the second semiconductor oxide layer includes performing a thermal oxidation process on the first semiconductor layer and the second semiconductor layer.

5. The method according to claim 1, wherein, Converting the first semiconductor layer into the first semiconductor oxide layer includes converting a first portion of the first semiconductor layer into silicon oxide (SiO2). x The first semiconductor layer is converted into silicon germanium oxide (SiGeO) layer, and a second portion thereof is converted into silicon germanium oxide (SiGeO). x )layer.

6. The method according to claim 1, wherein, Forming the first silicon germanium compound layer includes removing the second semiconductor oxide layer.

7. The method according to claim 1, wherein, Forming the first silicon germanium compound layer includes removing the second oxidation stop layer.

8. The method according to claim 1, wherein, Forming the first silicon germanium compound layer includes depositing a p-type work function metal (pWFM) layer on the first semiconductor oxide layer and on the p-type source / drain regions.

9. The method according to claim 1, wherein, Forming the second silicon germanium compound layer includes depositing an n-type work function metal (nWFM) layer on the first silicon germanium compound layer and on the n-type source / drain region.

10. The method of claim 1, further comprising performing p-type dopant implantation on the second semiconductor oxide layer.

11. A method for manufacturing a semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate; An n-type source / drain (S / D) region and a p-type source / drain region are formed on the first fin structure and the second fin structure, respectively; A first contact opening and a second contact opening are formed on the n-type source / drain region and the p-type source / drain region, respectively, and a first diffusion barrier layer and a second diffusion barrier layer are formed along the sidewalls of the first contact opening and the second contact opening, respectively. A silicide stop layer is deposited on the bottom surface of the first contact opening in the n-type source / drain region, the sidewall of the first diffusion barrier layer, and the p-type source / drain region. Remove the silicide stop layer on the p-type source / drain region; A p-type work function metal layer is deposited on the sidewalls and bottom wall of the silicide stop layer in the n-type source / drain region, and the p-type work function metal layer is deposited on the bottom surface of the second contact opening in the p-type source / drain region and on the sidewall of the second diffusion barrier layer to form a p-type work function metal (pWFM) silicide layer. as well as An n-type power function metal (nWFM) silicide layer is formed on the p-type power function metal silicide layer and the n-type source / drain region.

12. The method according to claim 11, wherein, Depositing the silicide stop layer includes depositing a semiconductor oxide layer or a silicon oxide layer on the n-type source / drain region and the p-type source / drain region.

13. The method of claim 11, further comprising: A first stack of alternating first and second nanostructure layers is formed on the first fin structure, wherein the first and second nanostructure layers comprise different semiconductor materials; and A second stack of alternating third and fourth nanostructure layers is formed on the second fin structure, wherein the third and fourth nanostructure layers comprise different semiconductor materials.

14. The method of claim 11, further comprising performing p-type dopant implantation on a portion of the silicide stop layer on the p-type source / drain region.

15. The method according to claim 11, wherein, The siliconized stop layer has a thickness of 2 nm to 10 nm.

16. The method according to claim 11, wherein, Forming the n-type power function metal silicide layer includes removing a portion of the silicide stop layer on the n-type source / drain regions.

17. A semiconductor device, comprising: Substrate; The first fin structure and the second fin structure are disposed on the substrate; The stack of the first nanostructure layer is disposed on the first part of the first fin structure; The stack of the second nanostructure layer is disposed on the first part of the second fin structure; A first gate structure, surrounding at least one of the first nanostructure layers; A second gate structure, surrounding at least one of the second nanostructure layers; The first source / drain (S / D) region and the second source / drain region are respectively disposed on the second part of the first fin structure and the second fin structure; A first metal germanium silicon oxide layer is disposed on the first source / drain region; A second metal silicon germanium oxide layer is disposed on the first metal silicon germanium oxide layer and the second source / drain region; as well as The first contact plug and the second contact plug are respectively disposed on the first metal silicon germanide layer and the second metal silicon germanide layer, wherein the metal of the first contact plug and the metal of the second contact plug are the same. A first diffusion barrier layer is disposed in the first source / drain region and located on both sides of the first contact plug; The first diffusion barrier layer overlaps with the first metal silicon germanium compound layer in the vertical direction.

18. The semiconductor device according to claim 17, wherein, The metal of the first metal germanium silicon compound layer is different from the metal of the second metal germanium silicon compound layer.

19. The semiconductor device according to claim 17, wherein, The first metal germanium silicon compound layer includes a p-type work function metal (pWFM) germanium silicon compound layer.

20. The semiconductor device according to claim 17, wherein, The second metal germanium silicon compound layer includes an n-type work function metal (nWFM) germanium silicon compound layer.

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