A multi-chip package structure for filter chips and its construction method

Abstract

This invention relates to the field of semiconductor packaging technology, and proposes a multi-chip packaging structure for filter chips and its construction method. The method includes: arranging a first wiring structure on a first surface of a substrate; connecting the first wiring structure to a first wafer; constructing a through-silicon via (TSV) structure on the substrate; arranging a second wiring structure on a second surface of the substrate, and connecting the second wiring structure to the first wiring structure through the TSV structure, wherein the second wiring structure includes multiple chips, at least one of which is a filter chip; arranging a release layer, a fifth dielectric layer, and metal pillars on the second wafer; connecting the metal pillars to the second wiring structure; encapsulating the metal pillars and the second wiring structure, and removing the second wafer; and arranging a third wiring structure on the fifth dielectric layer, and removing the first wafer.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor packaging technology. Specifically, this invention relates to a multi-chip packaging structure for filter chips and a method for constructing the same. Background Technology

[0002] Traditional multi-chip packaging methods include stacked package and stacked die package. Stacked package involves stacking multiple individual packages, which requires multiple molding processes. Due to the complexity of the packaging process and the large size resulting from stacking multiple packages, the overall system integration density is reduced. Stacked die package involves stacking multiple individual chips before packaging. The yield of the final product is affected by the individual chips. Upgrades require modifications to the overall chip and substrate structure, making system testing difficult. Furthermore, the yield is often low due to chip misalignment and warpage issues inherent in traditional chip molding processes. Additionally, in both stacked package and stacked die package, the electrical interconnections between systems are achieved through wire bonding, resulting in long interconnect lines and increased system latency.

[0003] In addition to the problems with the multi-chip packaging method mentioned above, when multiple chips include filter chips, cavities need to be set on the surface of the filter chips. However, the existing packaging of filter chips usually involves attaching the filter chips to a printed circuit board (PCB) and then molding them to form cavities. The above-mentioned methods for packaging filter chips are usually quite complicated. Summary of the Invention

[0004] To at least partially solve the above-mentioned problems in the prior art, the present invention proposes a method for constructing a multi-chip package structure for filter chips, comprising the following steps:

[0005] A first wiring structure is arranged on the first surface of the substrate;

[0006] Connect the first wiring structure to the first carrier chip;

[0007] A through-silicon via structure is constructed on the substrate;

[0008] A second wiring structure is disposed on a second surface of the substrate, and the second wiring structure is connected to the first wiring structure through the through-silicon via structure, wherein the second wiring structure includes a plurality of chips, at least one of which is a filter chip;

[0009] A release layer, a fifth dielectric layer, and metal pillars are arranged on the second substrate;

[0010] Connect the metal pillar to the second wiring structure;

[0011] The metal pillar and the second wiring structure are encapsulated, and the second substrate is removed; and

[0012] A third wiring structure is arranged on the fifth dielectric layer, and the first substrate is removed.

[0013] In one embodiment of the present invention, a cavity is constructed on a first surface of the filter chip, wherein the cavity faces a second surface of the substrate.

[0014] In one embodiment of the present invention, arranging a first wiring structure on a first surface of a substrate includes the following steps:

[0015] A first dielectric layer is disposed on a first surface of the substrate;

[0016] A first wiring layer is disposed on the first dielectric layer;

[0017] A second dielectric layer is disposed on the first wiring layer, and a first opening is formed on the second dielectric layer to expose the first wiring layer;

[0018] A second wiring layer is arranged at the first opening;

[0019] A third dielectric layer is disposed on the second wiring layer, and a second opening is formed in the third dielectric layer to expose the second wiring layer; and

[0020] The first solder ball is placed at the second opening.

[0021] In one embodiment of the present invention, constructing a through-silicon via structure on the substrate includes the following steps:

[0022] Thin the substrate:

[0023] Silicon vias are constructed on the substrate; and

[0024] A filler metal is electroplated in the through-silicon via, wherein the filler metal is connected to the first wiring structure.

[0025] In one embodiment of the present invention, arranging a second wiring structure on the second surface of the substrate includes the following steps:

[0026] A third wiring layer is disposed on a second surface of the substrate, wherein the third wiring layer is connected to the filler metal;

[0027] A fourth dielectric layer is disposed on the third wiring layer, and a third opening is formed in the fourth dielectric layer to expose the third wiring layer; and

[0028] The plurality of chips are arranged at the third opening.

[0029] In one embodiment of the invention, the metal pillar is connected to the third wiring layer exposed in the third opening.

[0030] In one embodiment of the present invention, arranging a third wiring structure on the fifth dielectric layer includes the following steps:

[0031] A fourth opening is constructed in the fifth dielectric layer to expose the metal pillar;

[0032] A rewiring layer is arranged at the fourth opening;

[0033] A sixth dielectric layer is disposed on the redistribution layer, and a fifth opening is formed on the sixth dielectric layer to expose the redistribution layer; and

[0034] A second solder ball is placed at the fifth opening.

[0035] This invention also proposes a multi-chip package structure for filter chips, which is constructed using the aforementioned construction method. The multi-chip package structure includes:

[0036] Substrate having a through-silicon via structure;

[0037] A first wiring structure is disposed on a first surface of the substrate;

[0038] A second wiring structure is disposed on a second surface of the substrate. The second wiring structure is connected to the first wiring structure through the through-silicon via structure. The second wiring structure includes a plurality of chips, at least one of which is a filter chip.

[0039] A metal pillar connected to the second wiring structure, wherein both the second wiring structure and the metal pillar are encapsulated; and

[0040] The third wiring structure is connected to the second wiring structure via metal pillars.

[0041] In one embodiment of the present invention, a cavity is formed on a first surface of the filter chip, wherein the cavity faces a second surface of the substrate.

[0042] In one embodiment of the present invention, the first wiring structure includes a first to a third dielectric layer, a first to a second wiring layer, and a first solder ball;

[0043] The second wiring structure includes a fourth dielectric layer, a third wiring layer, and multiple chips; and

[0044] The third wiring structure includes a sixth dielectric layer, a rewiring layer, and a second solder ball.

[0045] This invention offers at least the following advantages: By pre-fabricating cavities on the surface of the filter chip, it avoids the complex process issues associated with traditional cavity fabrication during packaging. Furthermore, by prioritizing the fabrication of the chip's fan-out redistribution layer, it avoids problems caused by chip misalignment and warping during redistribution layer construction, thus improving product yield. Additionally, by connecting the chip via TSV vias for vertical signal output, it enhances integration density, and by using metal pillar soldering instead of TSVs for vertical signal connections, it avoids the complexity of TSV fabrication. In summary, this invention proposes a 3D integrated packaging method that significantly improves packaging efficiency and integration density. Attached Figure Description

[0046] To further illustrate the advantages and other features of the various embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by the same or similar reference numerals for clarity.

[0047] Figure 1 The diagram shows a flowchart illustrating a method for constructing a multi-chip package structure for a filter chip according to one embodiment of the present invention.

[0048] Figure 2A -C、 Figure 3-8 The diagram illustrates the construction process of a multi-chip package structure for a filter chip according to one embodiment of the present invention.

[0049] Figure 9 This invention illustrates a multi-chip package structure for a filter chip in one embodiment. Detailed Implementation

[0050] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0051] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0052] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0053] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0054] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0055] It should also be noted that, within the scope of this invention, terms such as "same," "equal," and "equal to" do not imply that the two values ​​are absolutely equal, but rather allow for a certain reasonable margin of error. In other words, these terms also encompass "substantially the same," "substantially equal," and "substantially equal to." Similarly, in this invention, the directional terms "perpendicular to," "parallel to," etc., also encompass the meanings of "substantially perpendicular to" and "substantially parallel to."

[0056] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0057] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0058] Figure 1 A flowchart illustrating a method for constructing a multi-chip package structure for a filter chip according to one embodiment of the present invention is shown. Figure 1 As shown, the method may include the following steps:

[0059] Step 101: Arrange a first wiring structure on the first surface of substrate 201.

[0060] Step 102: Connect the first wiring structure to the first carrier chip.

[0061] Step 103: Construct a through-silicon via structure 301 on the substrate 201.

[0062] Step 104: Arrange a second wiring structure on the second surface of the substrate 201, and connect the second wiring structure to the first wiring structure through the through-silicon via structure 301, wherein the second wiring structure includes a plurality of chips, at least one of which is a filter chip 401.

[0063] Step 105: Arrange a release layer 502, a fifth dielectric layer 503, and a metal pillar 504 on the second substrate 501.

[0064] Step 106: Connect the metal pillar 504 to the second wiring structure.

[0065] Step 107: Encapsulate the metal pillar 504 and the second wiring structure, and remove the second carrier 501.

[0066] Step 108: Arrange a third wiring structure on the fifth dielectric layer and remove the first substrate.

[0067] Figure 2A -C、 Figure 3 A structural diagram illustrating the construction process of a multi-chip package structure for a filter chip according to one embodiment of the present invention is shown. The various embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0068] like Figure 2A As shown in -C, the first wiring structure may include a first dielectric layer 202, a second dielectric layer 204, a third dielectric layer 207, a first wiring layer 203, a second wiring layer 206, and a first solder ball 208. Step 101 may include the following steps:

[0069] A first dielectric layer 202 is disposed on the first surface of the substrate 201;

[0070] A first wiring layer 203 is disposed on the first dielectric layer 202;

[0071] A second dielectric layer 204 is disposed on the first wiring layer 203, and a first opening 205 is formed on the second dielectric layer 204 to expose the first wiring layer 202.

[0072] A second wiring layer 206 is arranged at the first opening 205;

[0073] A third dielectric layer 207 is disposed on the second wiring layer 206, and a second opening is formed in the third dielectric layer 207 to expose the second wiring layer 206; and

[0074] A first solder ball 208 is arranged at the second opening.

[0075] In step 102, the first substrate (not shown in the figure) can be connected to the first solder ball 208.

[0076] In this invention, the substrate can be made of various materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can also be made of electrically non-conductive materials, such as glass, plastic, or sapphire wafers. The dielectric layer can be inorganic materials such as silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated glass silicate glass (FSG), or ow-K dielectric; or it can be organic materials such as polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive additive material, BCB (bisphenylcyclobutene resin), or PBO (phenylbenzodioxazole resin).

[0077] like Figure 3 As shown, in step 103, constructing the through-silicon via structure 301 on the substrate 201 may include the following steps:

[0078] Thin the substrate 201:

[0079] Silicon vias are formed on the substrate 201; and

[0080] A filler metal is electroplated in the through-silicon via, wherein the filler metal is connected to the first wiring structure.

[0081] like Figure 3 and Figure 4 As shown, the second wiring structure may include a fourth dielectric layer, a third wiring layer, and multiple chips. Step 104 may include...

[0082] A third wiring layer 302 is disposed on the second surface of the substrate 201, wherein the third wiring layer 302 is connected to the fill metal;

[0083] A fourth dielectric layer 303 is disposed on the third wiring layer 302, and a third opening is formed in the fourth dielectric layer to expose the third wiring layer 302; and

[0084] The plurality of chips are arranged at the third opening.

[0085] At least one of the plurality of chips is a filter chip, for example, a filter chip 401 may be arranged at the third opening using a hybrid bonding method, and a general-purpose chip 402 may be bonded at the remaining third openings. A cavity is formed on a first surface of the filter chip 401, wherein the cavity faces the second surface of the substrate 201. In this invention, by pre-constructing the cavity on the filter chip, the problem of complex processes caused by traditionally creating cavities during the packaging process is avoided.

[0086] like Figure 5As shown, in step 105, a release layer 502, a fifth dielectric layer 503, and a metal pillar 504 can be arranged on the second substrate 501. The metal pillar 504 can be a copper pillar.

[0087] like Figure 6 As shown, in step 106, the metal pillar 504 can be connected to the third wiring layer 302 exposed at the third opening.

[0088] like Figure 7 and Figure 8 As shown, in step 107, the metal pillar 504 and the second wiring structure can be encapsulated to form an encapsulation layer 701. After encapsulation, the second carrier 501 can be removed.

[0089] The third wiring structure may include a sixth dielectric layer 901, a rewiring layer 902, and a second solder ball 903. Step 108 may include the following steps:

[0090] A fourth opening is constructed on the fifth dielectric layer 503 to expose the metal pillar 504;

[0091] A redistribution layer 902 is arranged at the fourth opening;

[0092] A sixth dielectric layer 901 is disposed on the redistribution layer, and a fifth opening is formed on the sixth dielectric layer 901 to expose the redistribution layer 902;

[0093] A second solder ball 903 is arranged at the fifth opening; and

[0094] After removing the first substrate, the following was obtained: Figure 9 The diagram shows a multi-chip package structure for filter chips.

[0095] like Figure 9 As shown, the multi-chip package structure for the filter chip may include:

[0096] Substrate 201, which has a through-silicon via structure 301;

[0097] A first wiring structure is arranged on a first surface of the substrate 201;

[0098] A second wiring structure is disposed on a second surface of the substrate 201. The second wiring structure is connected to the first wiring structure through the through-silicon via structure 301. The second wiring structure includes a plurality of chips, at least one of which is a filter chip 401.

[0099] Metal pillar 504, which is connected to the second wiring structure, wherein the second wiring structure and the metal pillar 504 are encapsulated; and

[0100] The third wiring structure is connected to the second wiring structure via a metal post 504.

[0101] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for constructing a multi-chip package structure for a filter chip, characterized in that, Includes the following steps: A first wiring structure is arranged on the first surface of the substrate; Connect the first wiring structure to the first carrier chip; A through-silicon via structure is constructed on the substrate; A second wiring structure is disposed on the second surface of the substrate, and the second wiring structure is connected to the first wiring structure through the through-silicon via structure; A release layer, a fifth dielectric layer, and metal pillars are arranged on the second substrate; Connect the metal pillar to the second wiring structure; The metal pillar and the second wiring structure are encapsulated in plastic, and the second carrier is removed; as well as A third wiring structure is arranged on the fifth dielectric layer, and the first substrate is removed. The process of constructing a through-silicon via structure on the substrate includes the following steps: Thin the substrate; Through-silicon vias are constructed on the substrate; as well as A filler metal is electroplated in the through-silicon via, wherein the filler metal is connected to the first wiring structure. Arranging the second wiring structure on the second surface of the substrate includes the following steps: A third wiring layer is disposed on a second surface of the substrate, wherein the third wiring layer is connected to the filler metal; A fourth dielectric layer is disposed on the third wiring layer, and a third opening is formed on the fourth dielectric layer to expose the third wiring layer; as well as Multiple chips are arranged at the third opening, at least one of which is a filter chip. The filter chip is arranged at the third opening by a hybrid bonding method, and ordinary chips are bonded at the remaining third openings. A cavity is formed on the first surface of the filter chip, and the cavity faces the second surface of the substrate. The cavity on the first surface of the filter chip and the second surface of the substrate constitute a sealed cavity.

2. The method for constructing a multi-chip package structure for a filter chip according to claim 1, characterized in that, Arranging the first wiring structure on the first surface of the substrate includes the following steps: A first dielectric layer is disposed on a first surface of the substrate; A first wiring layer is disposed on the first dielectric layer; A second dielectric layer is disposed on the first wiring layer, and a first opening is formed in the second dielectric layer to expose the first wiring layer; A second wiring layer is arranged at the first opening; A third dielectric layer is disposed on the second wiring layer, and a second opening is constructed on the third dielectric layer to expose the second wiring layer; as well as The first solder ball is placed at the second opening.

3. The method for constructing a multi-chip package structure for a filter chip according to claim 1, characterized in that, The metal pillar is connected to the third wiring layer exposed in the third opening.

4. The method for constructing a multi-chip package structure for a filter chip according to claim 1, characterized in that, Arranging the third wiring structure on the fifth dielectric layer includes the following steps: A fourth opening is constructed in the fifth dielectric layer to expose the metal pillar; A rewiring layer is arranged at the fourth opening; A sixth dielectric layer is disposed on the redistribution layer, and a fifth opening is formed on the sixth dielectric layer to expose the redistribution layer; as well as A second solder ball is placed at the fifth opening.

5. A multi-chip package structure for a filter chip, characterized in that, The multi-chip package structure is constructed using the construction method described in any one of claims 1-4, and includes: Substrate having a through-silicon via structure; A first wiring structure is disposed on a first surface of the substrate; A second wiring structure is disposed on a second surface of the substrate. The second wiring structure is connected to the first wiring structure through the through-silicon via structure. The second wiring structure includes a plurality of chips, at least one of which is a filter chip. A metal pillar connected to the second wiring structure, wherein the second wiring structure and the metal pillar are encapsulated; and The third wiring structure is connected to the second wiring structure via metal pillars.

6. The multi-chip packaging structure for filter chips according to claim 5, characterized in that, A cavity is formed on the first surface of the filter chip, wherein the cavity faces the second surface of the substrate.

7. The multi-chip packaging structure for filter chips according to claim 5, characterized in that, The first wiring structure includes first to third dielectric layers, first to second wiring layers, and a first solder ball; The second wiring structure includes a fourth dielectric layer, a third wiring layer, and multiple chips; as well as The third wiring structure includes a sixth dielectric layer, a rewiring layer, and a second solder ball.

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