Electronic package, its carrier structure and method of manufacture

Abstract

This invention relates to an electronic package and its carrier structure and manufacturing method, comprising a carrier structure carrying electronic components, wherein an electrical contact pad for mounting solder balls is connected to a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion within the carrier structure. The design of connecting a single electrical contact pad with a plurality of conductors disperses structural stress and avoids the problem of circuit breakage.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to an electronic package and its carrier structure and manufacturing method. Background Technology

[0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. In order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed, such as Fan-Out Package on Package (FO PoP), to accommodate the significantly increased number of input / output ports on various chips. This allows integrated circuits with different functions to be integrated into a single package structure. Electronic components with different functions, such as memory, central processing unit, graphics processor, and image application processor, can be integrated into a system through stacking design, which is suitable for use in thin and light electronic products.

[0003] like Figure 1 The semiconductor package 1 shown here comprises a plurality of semiconductor chips 11 bonded to a package substrate 10 via a plurality of solder bumps 13, and then forming a package colloid 14 covering the plurality of semiconductor chips 11, and an electrical contact pad 100 on the underside of the package substrate 10 is attached to a circuit board (not shown) via solder balls 17.

[0004] However, in existing semiconductor packages 1, due to the material characteristics of the packaging substrate 10, the packaging substrate 10 is prone to deformation during the thermal cycle of the packaging process due to thermal expansion and contraction (e.g., Figure 1 (As shown by the dotted line), this causes the package substrate 10 to warp, resulting in a gap between the conductive blind via 101 and the electrical contact pad 100 within the package substrate 10 (e.g., as shown by the dotted line). Figure 1A As shown, it is prone to cracking due to stress concentration.

[0005] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Summary of the Invention

[0006] In view of the various defects of the prior art, the present invention provides an electronic package and its supporting structure and manufacturing method, which can disperse structural stress and avoid the problem of fracture.

[0007] A first aspect of the present invention provides a support structure comprising: a support body including an insulating portion and at least one line portion coupled to the insulating portion; a plurality of conductors embedded in the insulating portion and electrically connected to the line portion; and at least one electrical contact pad coupled to the insulating portion to connect at least two of the plurality of conductors, wherein the insulating portion includes at least one dielectric layer to form a plurality of opening regions in the dielectric layer, such that each conductor is formed in each of the opening regions.

[0008] A second aspect of the present invention provides a method for manufacturing a support structure, comprising: forming a support body on a support member, the support body including an insulating portion and at least one circuit portion connected to the insulating portion, and embedding a plurality of conductive bodies electrically connected to the circuit portion in the insulating portion, wherein the insulating portion includes at least one dielectric layer to form a plurality of opening regions in the dielectric layer, such that each conductive body is formed in each of the opening regions; removing the support member; and forming at least one electrical contact pad on the insulating portion to connect at least two of the plurality of conductive bodies.

[0009] In the aforementioned carrier structure and its manufacturing method, the circuit section includes a seed layer and a wiring layer formed on the seed layer.

[0010] In the aforementioned load-bearing structure and its manufacturing method, the conductor is made of metal.

[0011] In the aforementioned load-bearing structure and its manufacturing method, the conductor is columnar.

[0012] In the aforementioned support structure and its manufacturing method, a seed layer is formed on the end face and side of the conductor.

[0013] In the aforementioned support structure and its manufacturing method, the electrical contact pad is covered on at least two of the plurality of conductors via a seed layer.

[0014] In the aforementioned support structure and its manufacturing method, a seed layer is formed on the upper surface of the dielectric layer and the wall of the opening region.

[0015] A third aspect of the present invention provides an electronic package comprising: a carrier structure as described in the first aspect above, the carrier body having opposing first and second sides such that an electrical contact pad is disposed on the second side of the carrier body; and an electronic component disposed on the first side of the carrier structure and electrically connected to the circuit portion.

[0016] A fourth aspect of the present invention provides a method for manufacturing an electronic package, comprising: providing a carrier structure as described in the first aspect above, wherein the carrier body has opposing first and second sides, such that an electrical contact pad is disposed on the second side of the carrier body; and disposing an electronic component on the first side of the carrier structure such that the electronic component is electrically connected to the circuit portion.

[0017] The aforementioned electronic package and its manufacturing method also include covering the electronic component with a packaging layer.

[0018] The aforementioned electronic package and its manufacturing method further include forming conductive elements on the electrical contact pad.

[0019] As can be seen from the above, the electronic package and its supporting structure and manufacturing method of the present invention mainly disperse the structural stress by connecting multiple conductors to a single electrical contact pad, thereby avoiding the breakage of the circuit section. Therefore, the supporting structure of the present invention can strengthen its overall structural strength, so that the conductor can avoid or reduce the problems caused by warping, thereby improving the reliability of the electronic package.

[0020] Furthermore, by designing the seed layer, the present invention increases the thickness of the circuit section, conductor, and / or electrical contact pad, thereby enhancing the structural strength of the circuit section, conductor, and / or electrical contact pad. Therefore, the present invention can effectively reduce the situation of stress concentration damage due to thin circuit thickness. Attached Figure Description

[0021] Figure 1 This is a cross-sectional schematic diagram of an existing semiconductor package.

[0022] Figure 1A for Figure 1 A magnified view of a portion of the image.

[0023] Figures 2A to 2E This is a cross-sectional schematic diagram of the manufacturing method of the electronic package of the present invention.

[0024] Figures 2A-1 to 2A-3 for Figure 2A A partial cross-sectional schematic diagram of the manufacturing process of the supporting body.

[0025] Figure 2A-4 for Figure 2A A partial cross-sectional schematic diagram.

[0026] Figure 2D-1 for Figure 2D A partial cross-sectional schematic diagram.

[0027] Figure 2D-2 for Figure 2D A partial top view diagram.

[0028] Explanation of reference numerals in the attached figures

[0029] 1: Semiconductor package

[0030] 10: Packaging substrate

[0031] 100: Electrical contact pad

[0032] 101: Conductive blind hole

[0033] 11: Semiconductor chips

[0034] 13: Solder bumps

[0035] 14: Encapsulating colloid

[0036] 17: Welding ball

[0037] 2: Electronic packaging components

[0038] 2a: Load-bearing structure

[0039] 20: Supporting Body

[0040] 20a: First side

[0041] 20b: Second side

[0042] 200: Insulation section

[0043] 200a: First dielectric layer

[0044] 200b: Second dielectric layer

[0045] 201: Line Department

[0046] 201a: First wiring layer

[0047] 201b: Second wiring layer

[0048] 202 Initial Seed Layer

[0049] 202a: First seed layer

[0050] 202b: Second seed layer

[0051] 202c: Third seed layer

[0052] 203: Conductive blind hole

[0053] 21: Electronic Components

[0054] 21a: Surface of Action

[0055] 21b: Non-acting surface

[0056] 210: Electrode pad

[0057] 211: Conductive bump

[0058] 22: Insulation materials

[0059] 23: Conductor

[0060] 23b: End face

[0061] 230: Opening area

[0062] 24: Electrical contact pad

[0063] 25: Encapsulation layer

[0064] 26: Adhesive Material

[0065] 27: Conductive elements

[0066] 28: Electronic devices

[0067] 28a:Contact

[0068] 280: Packaging material

[0069] 29: Heat sink

[0070] 290: Heatsink

[0071] 291: Support foot

[0072] 8: Support components

[0073] 80: Bonding layer. Detailed Implementation

[0074] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0075] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0076] Figures 2A to 2E This is a cross-sectional schematic diagram of the manufacturing method of the electronic package 2 of the present invention.

[0077] like Figure 2A As shown, a support body 20 is provided on a support member 8, having a first side 20a and a second side 20b opposite to each other, and at least one electronic component 21 is provided on the first side 20a of the support body 20.

[0078] In this embodiment, the carrier body 20 is, for example, a packaging substrate with a core layer, a coreless packaging substrate, a through-silicon via (TSV) silicon interposer (TSI), or other board types. It includes an insulating portion 200 and at least one circuit portion 201 bonded to the insulating portion 200, such as at least one fan-out redistribution layer (RDL). It should be understood that the carrier body 20 can also be other substrates for carrying chips, such as leadframes, wafers, or other boards with metal wiring, and is not limited to the above.

[0079] Furthermore, taking the coreless form of the substrate as an example, the carrier body 20 is manufactured by electroplating, in which a metal material is electroplated onto the dielectric layer via a seed layer on the support member 8 to form patterned circuits. For example, the material of the dielectric layer may be ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (PI), bismaleimide triazine (BT), FR5 prepreg (PP), molding compound, epoxy molding compound (EMC), or other suitable materials, and the seed layer may be formed by sputtering a metal material such as Ti, Cu, Ni, V, Al, W, Au, or a combination thereof, but is not limited to these.

[0080] Specifically, such as Figure 2A-1 As shown, the manufacturing process of the carrier body 20 first forms an initial seed layer 202 on the bonding layer 80 of the support member 8, and then forms a first dielectric layer 200a with a patterned opening region 230 on the initial seed layer 202, so that a portion of the surface of the initial seed layer 202 is exposed to the patterned opening region 230. Next, as... Figure 2A-2 As shown, a first seed layer 202a is formed on the first dielectric layer 200a and the initial seed layer 202 to electroplate a plurality of columnar conductors 23 in the patterned opening region 230, and a first wiring layer 201a is electroplated on the first dielectric layer 200a to electrically connect the plurality of conductors 23 to the first wiring layer 201a. Then, as... Figure 2A-3As shown, at least one second dielectric layer 200b, one second seed layer 202b, and one second wiring layer 201b are sequentially formed in an additive manner, such that the second wiring layer 201b is electrically connected to the first wiring layer 201a via at least one conductive blind via 203 embedded in the second dielectric layer 200b, and the second seed layer 202b formed on the second dielectric layer 200b and the first wiring layer 201a (or another second wiring layer 201b). The first and second dielectric layers 200a and 200b can be regarded as insulating portions 200, and the first seed layer 202a, the first wiring layer 201a, the second seed layer 202b, and the second wiring layer 201b can be regarded as circuit portions 201.

[0081] Furthermore, the electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, capacitor, and inductor. In this embodiment, as... Figure 2A-4 As shown, the electronic component 21 is a semiconductor chip with opposing active surfaces 21a and non-active surfaces 21b. The active surface 21a has multiple electrode pads 210, which are disposed on the second wiring layer 201b of the wiring portion 201 of the first side 20a of the carrier body 20 via multiple conductive bumps 211 such as solder material, metal pillars, or others using a flip-chip method and electrically connected to the wiring portion 201. The conductive bumps 211 are covered with an insulating material 22 such as a primer or a non-conductive film (NCF). Alternatively, the electronic component 21 can be electrically connected to the wiring portion 201 of the first side 20a of the carrier body 20 via multiple bonding wires (not shown) in a wire bonding manner. Or, the electronic component 21 can directly contact the wiring portion 201 of the first side 20a of the carrier body 20. Therefore, a required type and number of electronic components can be attached to the carrier body 20 to enhance its electrical functions, and there are many ways in which the electronic components 21 are electrically connected to the carrier body 20, not limited to the above.

[0082] In addition, the support member 8 is, for example, a plate of semiconductor material (such as silicon or glass), on which a release film or other adhesive film bonding layer 80 is sequentially formed by coating, for example, wherein the bonding layer 80 serves as a sacrificial release layer.

[0083] like Figure 2B As shown, an encapsulation layer 25 is formed on the first side 20a of the carrier body 20 so that the encapsulation layer 25 covers the electronic component 21 and the insulating material 22.

[0084] In this embodiment, the material forming the encapsulation layer 25 is an insulating material such as polyimide (PI), dry film, epoxy resin, or molding compound, but is not limited to the above. For example, the encapsulation layer 25 can be formed on the first side 20a of the carrier body 20 by lamination or molding.

[0085] Furthermore, the encapsulation layer 25 covers the non-functional surface 21b of the electronic component 21; alternatively, a leveling process can be performed as needed to make the upper surface of the encapsulation layer 25 flush with the non-functional surface 21b, so that the non-functional surface 21b is exposed by the encapsulation layer 25. For example, the leveling process can be performed by grinding to remove part of the material of the encapsulation layer 25.

[0086] like Figure 2C As shown, the support member 8 and its bonding layer 80 are removed, exposing the second side 20b of the bearing body 20.

[0087] In this embodiment, after removing the support member 8 and the bonding layer 80 thereon, the initial seed layer 202 on the second side 20b of the carrier body 20 is also removed to expose the lower end face 23b of the conductor 23.

[0088] like Figure 2D As shown, multiple C4-shaped conductive elements 27, such as solder balls, are formed on the second side 20b of the carrier body 20 to be attached to the contacts 28a of an electronic device 28, such as a circuit board, and an encapsulation material 280, such as a base adhesive, is formed on the electronic device 28 to cover the conductive elements 27.

[0089] In this embodiment, an electrical contact pad 24 is formed on the second side 20b of the carrier body 20 via electroplating through a third seed layer 202c, such as... Figure 2D-1 As shown, the conductive element 27 is combined, wherein the carrier body 20, the electrical contact pad 24 and the plurality of conductors 23 constitute a carrier structure 2a.

[0090] Furthermore, a single electrical contact pad 24 contacts multiple conductors 23, such that an array of multiple conductors 23 are erected on the electrical contact pad 24, as shown below. Figure 2D-2 As shown, the first wiring layer 201a is electrically connected to a single electrical contact pad 24 via a plurality of conductors 23.

[0091] like Figure 2E As shown, a heat sink 29 is disposed on the electronic device 28, and the heat sink 29 also covers the electronic component 21 to form the electronic package 2 of the present invention.

[0092] Through the aforementioned manufacturing method, the electronic package 2 of the present invention mainly includes: a carrier structure 2a, an electronic component 21 disposed on the carrier structure 2a, a packaging layer 25 covering the electronic component 21, an electronic device 28 that carries the carrier structure 2a via a plurality of conductive elements 27, and a heat sink 29 disposed on the electronic device 28 for dissipating heat from the electronic component 21.

[0093] In this embodiment, the heat sink 29 has a heat sink 290 and a plurality of support feet 291 extending downward from the edge of the heat sink 290. The lower side of the heat sink 290 is bonded to the non-functional surface 21b of the electronic component 21 by a heat dissipation material (not shown). For example, the heat dissipation material is a thermal interface material (TIM), solder, metal, or other thermally conductive material. When the non-functional surface 21b of the electronic component 21 is exposed to the encapsulation layer 25, the heat sink 290 (or the heat dissipation material) will contact and bond to the non-functional surface 21b of the electronic component 21.

[0094] In addition, the support foot 291 can be attached to the electronic device 28 via an adhesive material 26, such as a rubber material (or thermal adhesive), to fix the heat sink 29.

[0095] Therefore, the manufacturing method of the present invention mainly uses the design of these opening areas 230 to disconnect the first dielectric layer 200a, so that the structural stress will not be continuously concentrated on the insulating part 200, thereby reducing the stress on the circuit part 201 and preventing the circuit part 201 from breaking. Therefore, compared with the design of the existing single conductive blind hole connecting the electrical contact pad, the bearing structure 2a of the present invention can improve the problem of the copper material of the first dielectric layer 200a being too thin at the corner of the electrical contact pad 24, and strengthen its overall structural strength, thereby improving the reliability of the electronic package 2.

[0096] Furthermore, the present invention utilizes the principle of stress cutoff to form these opening regions 230, thereby the conductor 23 can avoid or reduce problems caused by warpage, and by using each stress cutoff point (multiple conductors 23) as the deformation degree of freedom control point of the load-bearing structure 2a, the warpage direction can be appropriately compensated.

[0097] In addition, the design of the first seed layer 202a, the second seed layer 202b and the third seed layer 202c increases the thickness of the circuit section 201, the conductor 23 and the electrical contact pad 24, thereby enhancing the structural strength of the circuit section 201, the conductor 23 and the electrical contact pad 24, and thus effectively reducing the situation of stress concentration damage due to the thin circuit thickness.

[0098] In addition, a first seed layer 202a is formed on the upper surface of the first dielectric layer 200a and the wall of the opening area, and / or a seed layer (first seed layer 202a and third seed layer 202c) is formed on the bottom surface and side of the conductor 23.

[0099] The present invention also provides a support structure 2a, which includes a support body 20, a plurality of conductors 23 disposed in the support body 20, and at least one electrical contact pad 24 disposed on the support body 20.

[0100] The carrier body 20 includes an insulating portion 200 and at least one circuit portion 201 connected to the insulating portion 200.

[0101] The conductor 23 is embedded in the insulating part 200 and electrically connected to the circuit part 201.

[0102] The electrical contact pad 24 is combined with the insulating portion 200 to connect a plurality of the conductors 23.

[0103] In one embodiment, the insulating portion 200 includes at least one dielectric layer (first and second dielectric layers 200a, 200b) to form a plurality of opening regions 230 in the first dielectric layer 200a, such that each conductor 23 is formed in each of the opening regions 230.

[0104] In one embodiment, the circuit section 201 includes a seed layer (first and second seed layers 202a, 202b) and a wiring layer (first and second wiring layers 201a, 201b) formed on the seed layer.

[0105] In one embodiment, the conductor 23 is made of metal.

[0106] In one embodiment, the conductor 23 is columnar.

[0107] In one embodiment, the end face 23b and side edge of the conductor 23 are formed with seed layers (first seed layer 202a and third seed layer 202c).

[0108] In one embodiment, the electrical contact pad 24 is covered over at least two of the plurality of conductors 23 via a third seed layer 202c.

[0109] In one embodiment, a first seed layer 202a is formed on the upper surface of the first dielectric layer 200a and the wall of the opening region.

[0110] In summary, the electronic package and its carrier structure and manufacturing method of the present invention, through the design of these opening areas, disconnect the insulating part, so that the structural stress can be dispersed, thereby avoiding the breakage of the circuit part. Therefore, the carrier structure of the present invention can strengthen its overall structural strength, so that the conductor can avoid or reduce the problems caused by warping, thereby improving the reliability of the electronic package.

[0111] Furthermore, by designing the seed layer to increase the thickness of the circuit section, conductor, and / or electrical contact pad, the structural strength of the circuit section, conductor, and / or electrical contact pad is enhanced, thus effectively reducing the situation of stress concentration damage due to thin circuit thickness.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A load-bearing structure, characterized in that, include: A carrier body includes an insulating portion and at least one circuit portion connected to the insulating portion; Multiple conductors, embedded in the insulating portion and electrically connected to the circuit portion; and At least one electrical contact pad is attached to the insulating portion to connect at least two of the plurality of conductors, wherein the insulating portion includes at least one dielectric layer and forms a plurality of opening regions in the dielectric layer for each conductor to be formed in each of the opening regions; A first seed layer is formed on the upper surface of the dielectric layer, the wall of the opening area, and the sides of the plurality of conductors; In this configuration, a single electrical contact pad contacts the plurality of conductors via a third seed layer, and the third seed layer directly contacts the end faces of the plurality of conductors, thereby causing the array of the plurality of conductors to be erected on the electrical contact pad.

2. The load-bearing structure as described in claim 1, characterized in that, The circuit section includes a second seed layer and a wiring layer formed on the second seed layer.

3. The load-bearing structure as described in claim 1, characterized in that, The conductor is made of metal.

4. The load-bearing structure as described in claim 1, characterized in that, The conductor is columnar.

5. An electronic package, characterized in that, include: The support structure as described in any one of claims 1 to 4, wherein the support body has opposing first and second sides, and the electrical contact pad is disposed on the second side of the support body; and An electronic component is disposed on the first side of the support structure and electrically connected to the circuit section.

6. The electronic package as described in claim 5, characterized in that, The electronic package also includes a packaging layer that covers the electronic component.

7. The electronic package as described in claim 5, characterized in that, The electronic package also includes conductive elements bonded to the electrical contact pad.

8. A method for manufacturing a load-bearing structure, characterized in that, include: A carrier body is formed on a support member, wherein the carrier body includes an insulating portion and at least one circuit portion connected to the insulating portion, and a plurality of conductive bodies electrically connected to the circuit portion are embedded in the insulating portion, and wherein the insulating portion includes at least one dielectric layer to form a plurality of opening regions in the dielectric layer, such that each conductive body is formed in each of the opening regions, wherein a first seed layer is formed on the upper surface of the dielectric layer, the wall surface of the opening region and the side of the plurality of conductive bodies; Remove the support component; and At least one electrical contact pad is formed on the insulating portion so that the electrical contact pad connects to at least two of the plurality of conductors; In this configuration, a single electrical contact pad contacts the plurality of conductors via a third seed layer, and the third seed layer directly contacts the end faces of the plurality of conductors, thereby causing the array of the plurality of conductors to be erected on the electrical contact pad.

9. The method for manufacturing the load-bearing structure as described in claim 8, characterized in that, The circuit section includes a second seed layer and a wiring layer formed on the second seed layer.

10. The method for manufacturing the load-bearing structure as described in claim 8, characterized in that, The conductor is made of metal.

11. The method for manufacturing the load-bearing structure as described in claim 8, characterized in that, The conductor is columnar.

12. A method for manufacturing an electronic package, characterized in that, include: Provided a support structure as described in any one of claims 1 to 4, wherein the support body has opposing first and second sides, and the electrical contact pad is disposed on the second side of the support body; and An electronic component is disposed on the first side of the support structure and is electrically connected to the circuit section.

13. The method for manufacturing an electronic package as described in claim 12, characterized in that, The manufacturing process also includes encapsulating the electronic component with a packaging layer.

14. The method for manufacturing an electronic package as described in claim 12, characterized in that, The manufacturing process also includes forming conductive elements on the electrical contact pad.

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