Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a first dielectric layer located on the substrate; a first metal interconnect line located in the first dielectric layer, extending along a first direction and arranged in parallel along a second direction, including a lower sub-interconnect line and an upper sub-interconnect line, the upper sub-interconnect line being located above the lower sub-interconnect line, and in the second direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged; a second dielectric layer located on the top of the first dielectric layer and the upper sub-interconnect line; a second metal interconnect line located in a part of the thickness of the second dielectric layer, extending along the second direction and arranged in parallel along the first direction; a via interconnect structure located in the remaining second dielectric layer at the bottom of the second metal interconnect line and a part of the thickness of the first dielectric layer, the via interconnect structure being connected to the top of the upper sub-interconnect line and covering the sidewalls of a part of the thickness of the upper sub-interconnect line in the longitudinal direction. The present invention is beneficial to reducing the resistance-capacitance delay.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the requirements for the integration and performance of integrated circuits have become increasingly high. In order to improve the integration and reduce the cost, the critical dimensions of components have been continuously reduced, and the circuit density inside the integrated circuit has become increasingly large. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnect lines.

[0003] To meet the requirements of the interconnect lines after the reduction of critical dimensions, the conduction between different metal layers or between the metal layer and the substrate is currently achieved through an interconnect structure. As the technology node progresses, the size of the interconnect structure has also become smaller and smaller; correspondingly, the process difficulty of forming the interconnect structure has become greater and greater, and the formation quality of the interconnect structure has a great impact on the electrical performance of the back end of line (BEOL) and the device reliability. In severe cases, it will affect the normal operation of semiconductor devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate, the normal direction of the surface of the substrate being longitudinal; a first dielectric layer located on the substrate; a plurality of first metal interconnect lines located in the first dielectric layer, the first metal interconnect lines including a lower sub-interconnect line and an upper sub-interconnect line, the lower sub-interconnect line being located in a partial thickness of the first dielectric layer, the upper sub-interconnect line being located in the remaining thickness of the first dielectric layer above the lower sub-interconnect line, both the lower sub-interconnect line and the upper sub-interconnect line extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction, in the second direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged; a second dielectric layer located on the top of the first dielectric layer and the upper sub-interconnect line; a plurality of second metal interconnect lines located in a partial thickness of the second dielectric layer and spaced from the first metal interconnect lines in the longitudinal direction, the second metal interconnect lines extending along the second direction and arranged in parallel along the first direction; a via interconnect structure located in the remaining thickness of the second dielectric layer at the bottom of the second metal interconnect lines and a partial thickness of the first dielectric layer, the via interconnect structure being connected to the top of the upper sub-interconnect line and covering the sidewalls of a partial thickness of the upper sub-interconnect line in the longitudinal direction.

[0006] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the normal direction of the surface of the substrate being longitudinal; forming a first sub-dielectric layer on the substrate; forming a plurality of lower sub-interconnect lines in the first sub-dielectric layer, the lower sub-interconnect lines extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; forming a second sub-dielectric layer covering the lower sub-interconnect lines and the first sub-dielectric layer, the second sub-dielectric layer and the first sub-dielectric layer constituting a first dielectric layer; forming a plurality of upper sub-interconnect lines in the second sub-dielectric layer, the upper sub-interconnect lines extending along the first direction and arranged in parallel along the second direction, in the second direction, the projections of the lower sub-interconnect lines and the upper sub-interconnect lines on the substrate being alternately arranged, the lower sub-interconnect lines and the upper sub-interconnect lines constituting a first metal interconnect; forming a second dielectric layer covering the first dielectric layer and the upper sub-interconnect lines; forming a plurality of second metal interconnects and via interconnect structures located at the bottoms of the second metal interconnects in the second dielectric layer, the second metal interconnects extending along the second direction and arranged in parallel along the first direction, the via interconnect structures being connected to the tops of the upper sub-interconnect lines, and the via interconnect structures extending longitudinally into a part of the thickness of the second sub-dielectric layer and covering the sidewalls of a part of the thickness of the upper sub-interconnect lines longitudinally.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a lower sub-interconnect line in a first sub-dielectric layer, a second sub-dielectric layer covering the lower sub-interconnect line and the first sub-dielectric layer is formed, and an upper sub-interconnect line is formed in the second sub-dielectric layer. The upper sub-interconnect line extends in the same direction as the lower sub-interconnect line. The lower sub-interconnect line and the upper sub-interconnect line constitute a first metal interconnect line. And in a second direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged. After forming the second dielectric layer, a plurality of second metal interconnect lines and via interconnect structures located at the bottoms of the second metal interconnect lines are formed in the second dielectric layer. The via interconnect structures are connected to the tops of the upper sub-interconnect lines, and the via interconnect structures extend longitudinally into the second sub-dielectric layer with a partial thickness and cover the sidewalls of the upper sub-interconnect line with a partial thickness in the longitudinal direction. Compared with a single-layer first metal interconnect line, in the embodiment of the present invention, since the first metal interconnect line of the same layer includes a lower sub-interconnect line and an upper sub-interconnect line, the lower sub-interconnect line and the upper sub-interconnect line are located at different thickness positions of the first dielectric layer. That is to say, the lower sub-interconnect line and the upper sub-interconnect line are located at different height positions in the longitudinal direction, and in the second direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged. This provides more spatial positions for the via interconnect structures to extend longitudinally into the second sub-dielectric layer with a partial thickness. At the same time, by making the via interconnect structures cover the sidewalls of the upper sub-interconnect line with a partial thickness in the longitudinal direction, it is beneficial to increase the contact area between the via interconnect structures and the upper sub-interconnect lines, thereby reducing the contact resistance between the via interconnect structures and the upper sub-interconnect lines. In addition, the position arrangement of the lower sub-interconnect line and the upper sub-interconnect line also provides more spatial positions for increasing the size of the via interconnect structures in the second direction. Therefore, it is easy to reduce the resistance of the via interconnect structures themselves by increasing the size of the via interconnect structures in the second direction. This correspondingly is also beneficial to increasing the contact area between the via interconnect structures and the first metal interconnect lines to reduce the contact resistance between the via interconnect structures and the first metal interconnect lines. In summary, by using the lower sub-interconnect line and the upper sub-interconnect line with a stacked structure to form the first metal interconnect line of the same layer, and the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged, and making the via interconnect structures cover the sidewalls of the upper sub-interconnect line with a partial thickness in the longitudinal direction, it is beneficial to reduce the RC delay (resistance-capacitance delay) in the back-end process. Moreover, the reduction of the contact resistance between the via interconnect structures and the upper sub-interconnect lines is also beneficial to improving the stress migration problem at the positions of the via interconnect structures, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a perspective view of a semiconductor structure;

[0010] Figure 2 isFigure 1 Cross-sectional view along the secant line a1a2;

[0011] Figure 3 is a perspective view of an embodiment of the semiconductor structure of the present invention;

[0012] Figure 4 is Figure 3 a top view of the first metal interconnect line in

[0013] Figure 5 is Figure 3 a cross-sectional view along the secant line a1a2;

[0014] Figures 6 to 17 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed implementation manners

[0015] Currently, the performance of semiconductor structures still needs to be improved. Now, the reasons for the performance improvement need to be analyzed in combination with a semiconductor structure.

[0016] Refer to Figure 1 , Figure 1 is a perspective view of a semiconductor structure.

[0017] The semiconductor structure includes: a substrate 10, in which a transistor structure 20 is formed; a dielectric layer (not shown in the figure), located on the substrate 10; a metal interconnect structure (not labeled), located in the dielectric layer. In the longitudinal direction (i.e., the normal direction of the surface of the substrate 10), the metal interconnect structure includes multiple layers of metal interconnect lines 30 arranged at intervals. The bottommost metal interconnect line 30 is electrically connected to the transistor structure 20, and adjacent two layers of metal interconnect lines 30 are connected by a via interconnect structure 35.

[0018] Currently, for each layer of metal interconnect line 30, the metal interconnect line 30 is a single-layer structure, and the extending directions of adjacent two layers of metal interconnect lines 30 in the longitudinal direction are perpendicular to each other. For example, the adjacent two layers of metal interconnect lines 30 are the first-layer metal interconnect line 31 and the second-layer metal interconnect line 32 located above the first-layer metal interconnect line 31 respectively. The first-layer metal interconnect line 31 extends along a first direction (such as Figure 1 the x direction shown in Figure 1 ), and the second-layer metal interconnect line 32 extends along a second direction (such as

[0019] the y direction shown in Figure 2 ), and the first direction and the second direction are perpendicular to each other. Figure 2 is Figure 1 a cross-sectional view along the secant line a1a2. Taking the first-layer metal interconnect line 31 and the second-layer metal interconnect line 32 as examples, the second-layer metal interconnect line 32 and the first-layer metal interconnect line 31 are electrically connected through the via interconnect structure 35.

[0020] Specifically, the via interconnect structure 35 is connected to the top of the first-layer metal interconnect line 31 located therebelow. That is to say, the via interconnect structure 35 is only located on the top of the first-layer metal interconnect line 31. Therefore, the contact area between the via interconnect structure 35 and the first-layer metal interconnect line 31 is limited by the line width of the first-layer metal interconnect line 31 along the second direction (such as Figure 1 the y direction shown in the figure), which makes it difficult to further increase the contact area between the via interconnect structure 35 and the first-layer metal interconnect line 31, and thus difficult to further reduce the RC delay in the back-end process. Correspondingly, the RC delay in the back-end process increasingly becomes a factor restricting the performance of the semiconductor structure.

[0021] To solve the above technical problems, in the semiconductor structure provided by the embodiments of the present invention, the first metal interconnecting line includes a lower sub-interconnecting line and an upper sub-interconnecting line. The lower sub-interconnecting line is located in a first dielectric layer with a partial thickness, and the upper sub-interconnecting line is located in the remaining thickness of the first dielectric layer above the lower sub-interconnecting line. And in the second direction, the projections of the lower sub-interconnecting line and the upper sub-interconnecting line on the substrate are alternately arranged. The via interconnecting structure is connected to the top of the upper sub-interconnecting line and longitudinally covers the sidewalls of the upper sub-interconnecting line with a partial thickness. Compared with the single-layer first metal interconnecting line, in the embodiments of the present invention, since the first metal interconnecting line of the same layer includes a lower sub-interconnecting line and an upper sub-interconnecting line, the lower sub-interconnecting line and the upper sub-interconnecting line are located at different thickness positions of the first dielectric layer, that is to say, the lower sub-interconnecting line and the upper sub-interconnecting line are located at different height positions longitudinally, and in the second direction, the projections of the lower sub-interconnecting line and the upper sub-interconnecting line on the substrate are alternately arranged. This provides more spatial positions for the via interconnecting structure to extend longitudinally into the first dielectric layer with a partial thickness. At the same time, by making the via interconnecting structure longitudinally cover the sidewalls of the upper sub-interconnecting line with a partial thickness, it is beneficial to increase the contact area between the via interconnecting structure and the upper sub-interconnecting line, thereby reducing the contact resistance between the via interconnecting structure and the upper sub-interconnecting line. In addition, the position arrangement of the lower sub-interconnecting line and the upper sub-interconnecting line also provides more spatial positions for increasing the size of the via interconnecting structure in the second direction. Therefore, it is easy to reduce the resistance of the via interconnecting structure itself by increasing the size of the via interconnecting structure in the second direction, which correspondingly is also beneficial to increase the contact area between the via interconnecting structure and the first metal interconnecting line to reduce the contact resistance between the via interconnecting structure and the first metal interconnecting line. In summary, by adopting the stacked lower sub-interconnecting line and upper sub-interconnecting line to form the first metal interconnecting line of the same layer, and the projections of the lower sub-interconnecting line and the upper sub-interconnecting line on the substrate are alternately arranged, and making the via interconnecting structure longitudinally cover the sidewalls of the upper sub-interconnecting line with a partial thickness, it is beneficial to reduce the RC delay in the back-end process. Moreover, the reduction of the contact resistance between the via interconnecting structure and the upper sub-interconnecting line is also beneficial to improve the stress migration problem at the position of the via interconnecting structure, thereby improving the performance of the semiconductor structure.

[0022] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0023] With reference to Figures 3 to 5 , Figure 3 is a perspective view of an embodiment of the semiconductor structure of the present invention, Figure 4 is Figure 3 the top view of the first metal interconnecting line in Figure 5 is Figure 3 the cross-sectional view along the a1a2 secant line.

[0024] The semiconductor structure includes: a substrate 100 (as shown in Figure 5 ), the surface normal direction of the substrate 100 is longitudinal (as shown by the Z direction in Figure 3 ); a first dielectric layer 200 (as shown in Figure 5 ), located on the substrate 100; multiple first metal interconnects 280, located in the first dielectric layer 200. The first metal interconnects 280 include lower sub-interconnects 230 and upper sub-interconnects 260. The lower sub-interconnects 230 are located in a partial thickness of the first dielectric layer 200, and the upper sub-interconnects 260 are located in the remaining thickness of the first dielectric layer 200 above the lower sub-interconnects 230. Both the lower sub-interconnects 230 and the upper sub-interconnects 260 extend along a first direction (as shown by the X direction in Figure 3 ) and are arranged in parallel along a second direction (as shown by the Y direction in Figure 3 ). The first direction is perpendicular to the second direction. In the second direction, the projections of the lower sub-interconnects 230 and the upper sub-interconnects 260 on the substrate 100 are alternately arranged; a second dielectric layer 120 (as shown in Figure 5 ), located on the top of the first dielectric layer 200 and the upper sub-interconnects 260; multiple second metal interconnects 110, located in a partial thickness of the second dielectric layer 120 and spaced from the first metal interconnects 280 longitudinally. The second metal interconnects 110 extend along the second direction and are arranged in parallel along the first direction; a via interconnect structure 240, located in the remaining thickness of the second dielectric layer 120 at the bottom of the second metal interconnects 110 and a partial thickness of the first dielectric layer 200. The via interconnect structure 240 is connected to the top of the upper sub-interconnects 260 and covers the sidewalls of a partial thickness of the upper sub-interconnects 260 longitudinally.

[0025] According to the actual process conditions, the substrate 100 includes a substrate and functional structures formed on the substrate. For example, the functional structures may include semiconductor devices such as MOS field effect transistors, resistance structures, conductive structures, etc. In this embodiment, the surface normal direction of the substrate 100 is longitudinal (as shown by the Z direction in Figure 3 ).

[0026] In the back-end process, the electrical properties of the functional structures in the substrate 100 are usually led out through metal interconnect structures, and the metal interconnect structures are composed of multiple layers of metal interconnects. The first metal interconnects 280 are one of the layers of metal interconnects in the metal interconnect structure. It should be noted that in the traditional back-end process, in each layer of metal interconnects, the metal interconnects are usually single-layer structures, while in this embodiment, the first metal interconnects 280 of the same layer are stacked structures. Specifically, the first metal interconnects 280 include lower sub-interconnects 230 and upper sub-interconnects 260 located above the lower sub-interconnects 230.

[0027] The upper sub-interconnect line 260 and the lower sub-interconnect line 230 form the first metal interconnect line 280 of the same layer. Therefore, the extending directions of the upper sub-interconnect line 260 and the lower sub-interconnect line 230 are the same. Specifically, the lower sub-interconnect line 230 extends along the first direction and is arranged in parallel along the second direction, and the upper sub-interconnect line 260 extends along the first direction and is arranged in parallel along the second direction. As Figure 4 shown, in this embodiment, in the second direction (such as Figure 4 the Y direction shown), the projections of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 on the substrate 100 are alternately arranged.

[0028] In the longitudinal direction, the second metal interconnect line 110 and the upper sub-interconnect line 260 are electrically connected through the via interconnect structure 240. In the traditional back-end process, the via interconnect structure is usually only located at the top of the corresponding metal interconnect line. However, in this embodiment, for the first metal interconnect line 280 of the same layer, the lower sub-interconnect line 230 and the upper sub-interconnect line 260 are located at different thickness positions of the first dielectric layer 200, that is to say, the lower sub-interconnect line 230 and the upper sub-interconnect line 260 are located at different height positions in the longitudinal direction, and in the second direction, the projections of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 on the substrate are alternately arranged. Therefore, in the second direction, the distance between the upper sub-interconnect lines 260 with opposite sidewalls is increased, which is equal to the sum of twice the distance between the adjacent lower sub-interconnect line 230 and the upper sub-interconnect line 260 and the line width of the lower sub-interconnect line 230. This increases the distance between the upper sub-interconnect lines 260 with opposite sidewalls, thereby providing more space positions for the via interconnect structure 240 to extend into the first dielectric layer 200 with a partial thickness in the longitudinal direction.

[0029] Correspondingly, by alternately arranging the projections of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 on the substrate 100, the distance between the lower sub-interconnect lines 230 with opposite sidewalls is also increased. According to the capacitance formula C = εrS / 4πkd, the capacitance is inversely proportional to the distance between the adjacent capacitor plates facing each other. The smaller the distance, the larger the capacitance. Among them, d represents the distance between the adjacent capacitor plates, S represents the facing area of the adjacent capacitor plates, εr represents the relative dielectric constant of the dielectric layer between the adjacent capacitor plates, and k is the electrostatic constant. Therefore, in this embodiment, by alternately arranging the projections of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 on the substrate 100 in the second direction, the in-layer capacitance of the first metal interconnect line 280 of the same layer can be effectively reduced, thereby reducing the RC delay in the back-end process and correspondingly improving the performance of the semiconductor structure.

[0030] As Figure 4 shown, in this embodiment, in the first direction (such as Figure 4In the X direction shown in the figure, adjacent lower-level sub-interconnect lines 230 are isolated from each other, and adjacent upper-level sub-interconnect lines 260 are isolated from each other. Specifically, in order to make the projections of the lower-level sub-interconnect lines 230 and the upper-level sub-interconnect lines 260 on the substrate 100 be arranged alternately, for the lower-level sub-interconnect lines 230, along the second direction, adjacent lower-level sub-interconnect lines 230 are staggered in the first direction; for the upper-level sub-interconnect lines 260, along the second direction, adjacent upper-level sub-interconnect lines 260 are staggered in the first direction.

[0031] As an example, the upper-level sub-interconnect line 260 also extends along the first direction to the top of a part of an adjacent lower-level sub-interconnect line 230 on either side and is connected to the corresponding lower-level sub-interconnect line 230. The connected upper-level sub-interconnect line 260 and lower-level sub-interconnect line 230 together serve as the same first metal interconnect line 280. Among them, by making the upper-level sub-interconnect line 260 also extend along the first direction to the top of a part of an adjacent lower-level sub-interconnect line 230 on either side, during the formation of the via interconnect structure 240, it is beneficial to make the via interconnect structure 240 be connected to the upper-level sub-interconnect line 260, thereby reducing the process complexity of forming the via interconnect structure 240 and improving process stability.

[0032] In other embodiments, according to actual process requirements, the layout of the upper-level sub-interconnect lines and the lower-level sub-interconnect lines can also be of other types. For example, the upper-level sub-interconnect line also extends along the first direction to the top of a part of adjacent lower-level sub-interconnect lines on both sides and is connected to the corresponding lower-level sub-interconnect lines, or, in the first direction, the projections of the lower-level sub-interconnect lines and the upper-level sub-interconnect lines on the substrate are arranged alternately.

[0033] It should be noted that when the upper-level sub-interconnect line 260 also extends along the first direction to the top of a part of an adjacent lower-level sub-interconnect line 230 on either side, along the first direction, the length (not marked) of the overlapping part of the lower-level sub-interconnect line 230 and the upper-level sub-interconnect line 260 should not be too small or too large. If the length of the overlapping part is too small, during the formation of the semiconductor structure, affected by the lithography alignment error, the probability that the upper-level sub-interconnect line 260 cannot be connected to the corresponding lower-level sub-interconnect line 230 is likely to increase, thereby affecting the normal performance of the metal interconnect line 280; if the length of the overlapping part is too large, it is likely to increase the facing area of adjacent upper-level sub-interconnect lines 260 in the second direction, thereby resulting in a higher in-layer capacitance of the same-layer metal interconnect line 280. For this reason, in this embodiment, along the first direction, the length of the overlapping part of the lower-level sub-interconnect line 230 and the upper-level sub-interconnect line 260 is 10 nanometers to 2000 nanometers.

[0034] In this embodiment, during the formation of the semiconductor structure, it is necessary to etch the first dielectric layer 200 in the area corresponding to the upper sub-interconnect 260 to form an interconnect trench for accommodating the upper sub-interconnect 260. The etching process generally includes main etch and over etch. Compared with the lower sub-interconnect line 230, the hardness of the first dielectric layer 200 is lower, and the etching process is likely to cause a certain amount of over-etching to the first dielectric layer 200 on the side of the lower sub-interconnect line 230. Therefore, the bottom surface of the upper sub-interconnect 260 on the side of the lower sub-interconnect line 230 is lower than the top surface of the lower sub-interconnect line 230.

[0035] In this embodiment, the material of the first metal interconnect line 280 includes one or more of cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), copper (Cu), platinum (Pt), nickel (Ni), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0036] In this embodiment, the lower sub-interconnect line 230 includes a first interconnect layer (not shown in the figure), and further includes a first diffusion barrier layer (not shown in the figure) located between the sidewall of the first interconnect layer and the first dielectric layer 200, and between the bottom of the first interconnect layer and the first dielectric layer 200.

[0037] The first diffusion barrier layer is used to achieve isolation between the first interconnect layer and the first dielectric layer 200, and plays a role in blocking the atoms of the conductive material in the first interconnect layer, thereby preventing the atoms of the conductive material from diffusing into the first dielectric layer 200, and further reducing the impact on the electrical isolation performance of the first dielectric layer 200. In addition, the first diffusion barrier layer can also improve the electromigration problem of the conductive ions in the first interconnect layer. Therefore, the material of the first diffusion barrier layer includes one or more of Ta, TaN, Ti, and TiN. These materials have a relatively high density and can play a good role in blocking diffusion. In this embodiment, the material of the first diffusion barrier layer is TaN.

[0038] The material of the first interconnect layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the first interconnect layer is Cu. Cu has a relatively low resistivity, which is beneficial to reducing the RC delay of the device, and Cu has excellent electromigration resistance.

[0039] In this embodiment, the upper sub-interconnect line 260 includes a second interconnect layer (not shown in the figure), and further includes a second diffusion barrier layer (not shown in the figure) located between the sidewalls of the second interconnect layer and the first dielectric layer 200, between the bottom of the second interconnect layer and the first dielectric layer 200, and between the bottom of the second interconnect layer and the top of the lower sub-interconnect line 230. For the specific descriptions of the second interconnect layer and the second diffusion barrier layer, reference can be made to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer respectively, which will not be elaborated here.

[0040] The first dielectric layer 200 is used to achieve electrical isolation between the first metal interconnect lines 280. The material of the first dielectric layer 200 may include one or more of silicon oxycarbide hydroxide (SiOCH), silicon oxycarbide (SiOC), silicon dioxide (SiO2), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), and boron-phosphorus-doped silicon dioxide (BPSG). Specifically, the material of the first dielectric layer 200 may be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so as to effectively reduce the capacitance between the first metal interconnect lines 280, and further reduce the RC delay in the back-end process. In this embodiment, the material of the first dielectric layer 200 is silicon oxycarbide hydroxide. Silicon oxycarbide hydroxide is an ultra-low-k dielectric material.

[0041] In this embodiment, the first dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220 located on top of the first sub-dielectric layer 210. Therefore, the lower sub-interconnect line 230 is located in the first sub-dielectric layer 210, and the upper sub-interconnect line 260 is located in the second sub-dielectric layer 220. Since the first dielectric layer 200 is a stacked structure, the traditional back-end process can be used to form the lower sub-interconnect line 230 in the first sub-dielectric layer 210, and then form the second sub-dielectric layer 220 additionally. Then, the upper sub-interconnect line 260 is formed in the second sub-dielectric layer 220. The formation process of the first metal interconnect lines 280 has less modification to the traditional back-end process and has high process compatibility.

[0042] In this embodiment, the semiconductor structure further includes: an in-layer etch stop layer 290, located between the top of the lower sub-interconnect line 230 exposed by the upper sub-interconnect line 260 and the bottom of the second sub-dielectric layer 220, and between the top of the first sub-dielectric layer 210 exposed by the upper sub-interconnect line 260 and the bottom of the second sub-dielectric layer 220.

[0043] During the formation of a semiconductor structure, it is necessary to etch the second sub-dielectric layer 220 in the area corresponding to the upper sub-interconnect 260 to form an interconnect trench for accommodating the upper sub-interconnect 260. Among them, during the process of forming the interconnect trench for accommodating the upper sub-interconnect 260, the in-layer etch stop layer 290 is used to define the position where etching stops, thereby improving the over-etching problem of the lower sub-interconnect line 230 exposed by the interconnect trench or the first sub-dielectric layer 210 at the bottom of the interconnect trench.

[0044] The material of the in-layer etch stop layer 290 includes one or more of SiCN (silicon carbonitride), SiCO (silicon carbon oxide), SiN (silicon nitride), Al2O3 (aluminum oxide), and AlN (aluminum nitride). In this embodiment, the material of the in-layer etch stop layer 290 is SiN.

[0045] The second dielectric layer 120 is used to achieve electrical isolation between the second metal interconnect lines 110 and also to achieve electrical isolation between the via interconnect structures 240. The material of the second dielectric layer 120 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. For the description of the material of the second dielectric layer 120, reference can be made to the foregoing description of the first dielectric layer 200, which will not be elaborated here.

[0046] The second metal interconnect line 110 is another layer of metal interconnect line in the metal interconnect structure. In this embodiment, longitudinally, the second metal interconnect line 110 and the first metal interconnect line 280 are two adjacent layers of metal interconnect lines, and the second metal interconnect line 110 and the first metal interconnect line 280 are spaced apart longitudinally. Therefore, the extending directions of the second metal interconnect line and the first metal interconnect line are perpendicular to each other.

[0047] In this embodiment, the material of the second metal interconnect line 110 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN. Specifically, the second metal interconnect line 110 includes a third interconnect layer (not shown in the figure), and also includes a third diffusion barrier layer (not shown in the figure) located between the sidewalls of the third interconnect layer and the second dielectric layer 120, and between the bottom of the third interconnect layer and the second dielectric layer 120. For the specific descriptions of the third interconnect layer and the third diffusion barrier layer, reference can be made to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer respectively, which will not be elaborated here.

[0048] The via interconnect structure 240 is located between two adjacent layers of metal interconnect lines longitudinally and is used to achieve electrical connection between the second metal interconnect line 110 and the first metal interconnect line 280. In this embodiment, the via interconnect structure 240 is located in the second dielectric layer 120 with the remaining thickness at the bottom of the second metal interconnect line 110.

[0049] In this embodiment, the via interconnect structure 240 is connected to the top of the upper sub-interconnect line 260, and the via interconnect structure 240 also extends longitudinally into the first dielectric layer 200 with a partial thickness, and the via interconnect structure 240 covers the sidewalls of the upper sub-interconnect line 260 with a partial thickness in the longitudinal direction. Specifically, the via interconnect structure 240 extends longitudinally into the second sub-dielectric layer 220 with a partial thickness.

[0050] By making the via interconnect structure 240 cover the sidewalls of the upper sub-interconnect line 260 with a partial thickness in the longitudinal direction, it is beneficial to increase the contact area between the via interconnect structure 240 and the upper sub-interconnect line 260, thereby reducing the contact resistance between the via interconnect structure 240 and the upper sub-interconnect line 260.

[0051] In addition, the positional arrangement of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 also provides more spatial positions for increasing the size of the via interconnect structure 240 in the second direction (such as Figure 3 shown by the Y direction in the figure). For example, when there is sufficient space on the side of the upper sub-interconnect line 260 in the second direction, it is easy to reduce the resistance of the via interconnect structure 240 itself by increasing the size of the via interconnect structure 240 in the second direction, which also correspondingly helps to increase the contact area between the via interconnect structure 240 and the second metal interconnect line 110 to reduce the contact resistance between the via interconnect structure 240 and the first metal interconnect line 110.

[0052] In summary, in this embodiment, the lower sub-interconnect line 230 and the upper sub-interconnect line 260 with a stacked structure form the first metal interconnect line 280 of the same layer, and the projections of the lower sub-interconnect line 230 and the upper sub-interconnect line 260 on the substrate 100 are alternately arranged, and the via interconnect structure 240 covers the sidewalls of the upper sub-interconnect line 260 with a partial thickness in the longitudinal direction, which is beneficial to reducing the RC delay in the back-end process, and further improving the performance of the semiconductor structure.

[0053] Moreover, the reduction of the contact resistance between the via interconnect structure 240 and the upper sub-interconnect line 260 is also beneficial to improving the stress migration problem at the position of the via interconnect structure 240, and correspondingly improving the performance of the semiconductor structure.

[0054] In addition, the via interconnect structure 240 is connected to the top of the upper sub-interconnect line 260, thereby increasing the process window for forming the via interconnect structure 240. During the process of forming the via interconnect structure 240, it is beneficial to reduce the requirement for the alignment accuracy of the lithography process. That is to say, it is beneficial to reduce the probability that the via interconnect structure 240 cannot be connected to the upper sub-interconnect line 260 due to alignment deviation, thereby ensuring the electrical connection between the via interconnect structure 240 and the upper sub-interconnect line 260.

[0055] In this embodiment, the thickness of the upper sub-interconnecting line 260 is defined as a first thickness (not labeled), and the thickness of the upper sub-interconnecting line 260 covered by the via interconnect structure 240 is a second thickness D (as Figure 5 shown). Then, the ratio of the second thickness D to the first thickness should neither be too small nor too large. If the ratio of the second thickness D to the first thickness is too small, the effect of increasing the contact area between the via interconnect structure 240 and the upper sub-interconnecting line 260 is not good, and it is difficult to effectively reduce the RC delay in the back-end process; if the ratio of the second thickness D to the first thickness is too large, the probability of short circuit between the via interconnect structure 240 and the lower sub-interconnecting line 230 on the side of the upper sub-interconnecting line 260 becomes higher, thereby having an adverse effect on the performance of the semiconductor structure. Therefore, in this embodiment, the ratio of the second thickness D to the first thickness is 5% to 80%.

[0056] In this embodiment, according to the actual situation (for example, the dimension of the via interconnect structure 240 in the second direction), while ensuring an increase in the contact area between the via interconnect structure 240 and the upper sub-interconnecting line 260, the via interconnect structure 240 can cover the entire top of the upper sub-interconnecting line 260 in the second direction, or can cover a part of the top of the upper sub-interconnecting line 260. For example, as Figure 5 shown, a situation where the via interconnect structure 240 covers a part of the top of the upper sub-interconnecting line 260 in the second direction is shown. In some other embodiments, when the dimension of the via interconnect structure in the second direction is large, the via interconnect structure not only covers the sidewalls of the upper sub-interconnecting line with a part of the thickness in the longitudinal direction, but also covers the entire top of the upper sub-interconnecting line in the second direction, thereby further increasing the contact area between the via interconnect structure and the upper sub-interconnecting line.

[0057] In this embodiment, in the second direction, the width of the upper sub-interconnecting line 260 is defined as a first width (not labeled), and the width of the upper sub-interconnecting line 260 covered by the via interconnect structure 240 is a second width W (as shown in FIG. 5). The ratio of the second width W to the first width should not be too small. If the ratio of the second width W to the first width is too small, affected by the alignment deviation or the dimensional accuracy of the via interconnect structure 240, the probability that the via interconnect structure 240 cannot be connected to the upper sub-interconnecting line 260 is likely to increase. Therefore, in this embodiment, the ratio of the second width W to the first width is 20% to 100%. Among them, when the ratio of the second width W to the first width is 100%, it means that the via interconnect structure 240 covers the entire top of the upper sub-interconnecting line 260 in the second direction.

[0058] In this embodiment, the material of the via interconnect structure 240 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN. Specifically, the via interconnect structure 240 includes conductive pillars (not shown in the figure), and further includes a fourth diffusion barrier layer (not shown in the figure) between the sidewalls of the conductive pillars and the first dielectric layer 200, between the sidewalls of the conductive pillars and the second dielectric layer 120, between the bottom of the conductive pillars and the first dielectric layer 200, and between the conductive pillars and the upper interconnect line 260. For the specific descriptions of the conductive pillars and the fourth diffusion barrier layer, reference can be made to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer respectively, which will not be elaborated here.

[0059] In this embodiment, the via interconnect structure 240 and the second metal interconnect line 110 are formed by using a traditional back-end process. Therefore, the via interconnect structure 240 and the second metal interconnect line 110 are an integral structure. Correspondingly, the conductive pillars and the third interconnect layer are an integral structure, and the fourth diffusion barrier layer and the third diffusion barrier layer are an integral structure.

[0060] Figures 6 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0061] Refer to Figure 6 , a substrate 300 is provided, and the surface normal direction of the substrate 300 is longitudinal.

[0062] The substrate 300 provides a process platform for the formation of the semiconductor structure. According to the actual process conditions, the substrate 300 includes a substrate and functional structures formed on the substrate. For example, the functional structures may include semiconductor devices such as MOS field-effect transistors, resistor structures, conductive structures, etc.

[0063] Continue to refer to Figure 7 , a first sub-dielectric layer 410 is formed on the substrate 300.

[0064] The first sub-dielectric layer 410 is used to provide a process platform for the subsequent formation of the lower sub-interconnect lines and also to achieve electrical isolation between the lower sub-interconnect lines.

[0065] The material of the first sub-dielectric layer 410 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. Specifically, the material of the first sub-dielectric layer 410 may be a low-k dielectric material or an ultra-low-k dielectric material, so as to effectively reduce the capacitance between the first metal interconnect lines and further reduce the RC delay of the device. In this embodiment, the material of the first sub-dielectric layer 410 is silicon oxycarbide hydroxide.

[0066] Combined with reference to Figures 7 to 9 , Figure 7It is a cross-sectional view after forming the first interconnect trench 415. Figure 8 It is a cross-sectional view after forming the lower sub-interconnect line 430. Figure 9 It is a top view of the lower sub-interconnect line 430. The lower sub-interconnect line 430 is formed in the first sub-dielectric layer 410 and extends along a first direction (as shown by the X direction in Figure 9 ), and is arranged in parallel along a second direction (as shown by the Y direction in Figure 9 ). The first direction is perpendicular to the second direction.

[0067] The lower sub-interconnect line 430 is used to form the first metal interconnect line. In the traditional back-end process, in each layer of metal interconnect lines, the metal interconnect line is usually a single-layer structure. In this embodiment, the metal interconnect lines in the same layer are a stacked structure, and the lower sub-interconnect line 430 is one of the sub-interconnect lines in the first metal interconnect line.

[0068] As an example, in the first direction, the adjacent lower sub-interconnect lines 430 are isolated from each other, and the region between the adjacent lower sub-interconnect lines 430 is used to provide a space position for forming the upper sub-interconnect line above the lower sub-interconnect line 430 subsequently. Correspondingly, in the second direction, the adjacent lower sub-interconnect lines 430 are staggered in the first direction, so that after the upper sub-interconnect line is formed subsequently, in the second direction, the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line on the substrate 300 can be alternately arranged.

[0069] Moreover, in the second direction, the adjacent lower sub-interconnect lines 430 are staggered in the first direction, which increases the distance between the lower sub-interconnect lines 430 with opposite sidewalls in the second direction, thereby reducing the capacitance between the lower sub-interconnect lines 430, effectively reducing the intra-layer capacitance of the first metal interconnect line, and further reducing the RC delay in the back-end process, and correspondingly improving the performance of the semiconductor structure.

[0070] In this embodiment, in the first direction, the distance (not marked) between the ends of the adjacent lower sub-interconnect lines 430 meets the requirements of the design rules.

[0071] In this embodiment, the material of the lower sub-interconnect line 430 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0072] With reference to Figure 7 , before forming the lower sub-interconnect line 430, it further includes: etching the first sub-dielectric layer 410 to form a plurality of first interconnect trenches 415 in the first sub-dielectric layer 410. The first interconnect trenches 415 extend along the first direction and are arranged in parallel along the second direction.

[0073] The first interconnect groove 415 provides a spatial position for the formation of the lower-level sub-interconnect lines 430. In this embodiment, in the first direction, adjacent first interconnect grooves 415 are isolated from each other, and along the second direction, adjacent first interconnect grooves 415 are staggered in the first direction.

[0074] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to etch the first sub-dielectric layer 410 to form the first interconnect groove 415. The dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first interconnect groove 415.

[0075] Correspondingly, referring to Figure 8 , the steps of forming the lower-level sub-interconnect lines 430 include: filling the first interconnect material layer in the first interconnect groove 415 to form the lower-level sub-interconnect lines 430 located in the first interconnect groove 415.

[0076] Specifically, after filling the first interconnect material layer, the first interconnect material layer usually also covers the top of the first sub-dielectric layer 410. Therefore, the steps of forming the lower-level sub-interconnect lines 430 further include: performing a planarization process (for example, a chemical mechanical polishing process) on the first interconnect material layer to remove the first interconnect material layer higher than the top of the first sub-dielectric layer 410.

[0077] The material of the first interconnect material layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the first interconnect material layer is Cu. Cu has a lower resistivity, which is beneficial to reducing the RC delay in the back-end process, and Cu has excellent electromigration resistance.

[0078] In this embodiment, before filling the first interconnect material layer in the first interconnect groove 415, it further includes: forming a first diffusion barrier layer (not labeled) on the sidewalls and bottom of the first interconnect groove 415. The material of the first diffusion barrier layer includes one or more of Ta, TaN, Ti, and TiN. In this embodiment, the material of the first diffusion barrier layer is TaN. For the specific description of the first diffusion barrier layer, reference can be made to the corresponding description in the foregoing embodiment, which will not be elaborated here.

[0079] It should be noted that during the formation of the first diffusion barrier layer, the first diffusion barrier layer also extends to cover the top of the first sub-dielectric layer 410. Correspondingly, during the planarization process of the first interconnect material layer, the first diffusion barrier layer located on the top of the first sub-dielectric layer 410 is also removed.

[0080] Referring to Figure 10, a second sub-dielectric layer 420 covering the underlying sub-interconnect lines 430 and the first sub-dielectric layer 410 is formed, and the second sub-dielectric layer 420 and the first sub-dielectric layer 410 constitute the first dielectric layer 400.

[0081] The second sub-dielectric layer 420 is used to provide a process platform for the subsequent formation of upper-layer sub-interconnect lines and also for realizing electrical isolation between the upper-layer sub-interconnect lines. For the description of the material of the second sub-dielectric layer 420, reference can be made to the relevant description of the first sub-dielectric layer 410 above, which will not be elaborated here.

[0082] In this embodiment, the materials of the second-layer sub-dielectric layer 420 and the first sub-dielectric 410 are the same.

[0083] Continuing to refer to Figure 10 , it should be noted that before forming the second sub-dielectric layer 420, it further includes: forming an in-layer etch stop layer 490 covering the top of the underlying sub-interconnect lines 430 and the top of the first sub-dielectric layer 410.

[0084] Subsequently, the second sub-dielectric layer 420 is etched to form a second interconnect trench for accommodating the upper-layer sub-interconnect lines. During the etching process, the in-layer etch stop layer 490 is used to define the position where the etching stops, thereby improving the over-etching problem of the underlying sub-interconnect lines 430 exposed by the second interconnect trench or the first sub-dielectric layer 410 at the bottom of the second interconnect trench. Correspondingly, in the step of forming the second sub-dielectric layer 420, the second sub-dielectric layer 420 covers the in-layer etch stop layer 490.

[0085] The material of the in-layer etch stop layer 490 includes one or more of SiCN, SiCO, SiN, Al2O3, and AlN. In this embodiment, the material of the in-layer etch stop layer 490 is SiN.

[0086] Combined with reference to Figures 11 to 13 , Figure 11 is a cross-sectional view after forming the second interconnect trench, Figure 12 is a top view after forming the upper-layer sub-interconnect lines 460, Figure 13 is a top view of the underlying sub-interconnect lines 430 and the upper-layer sub-interconnect lines 460. A plurality of upper-layer sub-interconnect lines 460 are formed in the second sub-dielectric layer 420, and the upper-layer sub-interconnect lines 460 extend along a first direction (such as Figure 13 the X direction shown in Figure 13 ) and are arranged in parallel along a second direction (such as the Y direction shown in

[0087] ). In the second direction, the projections of the underlying sub-interconnect lines 430 and the upper-layer sub-interconnect lines 460 on the substrate 300 are alternately arranged, and the underlying sub-interconnect lines 430 and the upper-layer sub-interconnect lines 460 constitute the first metal interconnect line 480.

[0087] In this embodiment, the upper sub-interconnect line 460 is another layer of sub-interconnect line in the first metal interconnect line 480. The upper sub-interconnect line 460 and the lower sub-interconnect line 430 together form the first metal interconnect line 480 of the same layer. Therefore, the extending directions of the upper sub-interconnect line 460 and the lower sub-interconnect line 430 are the same. Specifically, the upper sub-interconnect line 460 extends along the first direction and is arranged in parallel along the second direction.

[0088] In the traditional back-end process, in each layer of metal interconnect line, the metal interconnect line is usually a single-layer structure. In this embodiment, the first metal interconnect line 480 of the same layer is a stacked structure.

[0089] As Figure 13 shown, in this embodiment, in the second direction, the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 on the substrate 300 are alternately arranged.

[0090] Subsequently, a second metal interconnect line is formed above the first metal interconnect line 480. In the longitudinal direction, the second metal interconnect line and the upper sub-interconnect line 460 are electrically connected through a via interconnect structure. In the traditional process, the via interconnect structure is usually only located at the top of the corresponding metal interconnect line. In this embodiment, for the first metal interconnect line 480 of the same layer, the lower sub-interconnect line 430 and the upper sub-interconnect line 460 are located at different thickness positions of the first dielectric layer 400, that is to say, the lower sub-interconnect line 430 and the upper sub-interconnect line 460 are located at different height positions in the longitudinal direction, and in the second direction, the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 on the substrate are alternately arranged. Therefore, in the second direction, the distance between the upper sub-interconnect lines 460 with opposite sidewalls is increased, which is equal to the sum of twice the distance between the adjacent lower sub-interconnect line 430 and the upper sub-interconnect line 460 and the line width of the lower sub-interconnect line 430. This increases the distance between the upper sub-interconnect lines 460 with opposite sidewalls, thereby providing more space positions for the subsequent via interconnect structure to extend longitudinally into the second sub-dielectric layer 420 with a partial thickness.

[0091] Correspondingly, by alternately arranging the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 on the substrate 300, the distance between the lower sub-interconnect lines 430 with opposite sidewalls is also increased. Therefore, in this embodiment, by alternately arranging the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 on the substrate 300 in the second direction, the intra-layer capacitance of the first metal interconnect line 280 of the same layer can be effectively reduced, thereby reducing the RC delay in the back-end process.

[0092] As Figure 13As shown, in this embodiment, in the first direction, the adjacent upper-layer sub-interconnect lines 460 are isolated from each other. Specifically, in order to make the projections of the lower-layer sub-interconnect lines 430 and the upper-layer sub-interconnect lines 460 on the substrate 300 be alternately arranged, in the second direction, the adjacent upper-layer sub-interconnect lines 460 are staggeredly arranged in the first direction.

[0093] As an example, the upper-layer sub-interconnect line 460 also extends along the first direction to the top of a part of the adjacent lower-layer sub-interconnect line 430 on any side and is connected to the corresponding lower-layer sub-interconnect line 430. The connected upper-layer sub-interconnect line 460 and lower-layer sub-interconnect line 430 together serve as the same first metal interconnect line 480. By making the upper-layer sub-interconnect line 460 also extend along the first direction to the top of a part of the adjacent lower-layer sub-interconnect line 430 on any side, during the subsequent formation of the via interconnect structure, it is beneficial for the via interconnect structure to be connected to the upper-layer sub-interconnect line 460, thereby reducing the process complexity of forming the via interconnect structure and improving the process stability.

[0094] In this embodiment, in the first direction, the length of the overlapping part of the lower-layer sub-interconnect line 430 and the upper-layer sub-interconnect line 460 is from 10 nanometers to 2000 nanometers.

[0095] In other embodiments, according to actual process requirements, the layout of the upper-layer sub-interconnect line and the lower-layer sub-interconnect line can also be of other types. For example, the upper-layer sub-interconnect line also extends along the first direction to the top of a part of the adjacent lower-layer sub-interconnect line on both sides and is connected to the corresponding lower-layer sub-interconnect line. The connected upper-layer sub-interconnect line and lower-layer sub-interconnect line together serve as the same first metal interconnect line, or the projections of the lower-layer sub-interconnect line and the upper-layer sub-interconnect line on the substrate are alternately arranged.

[0096] In this embodiment, the material of the upper-layer sub-interconnect line 460 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0097] With reference to Figure 11 , before forming the upper-layer sub-interconnect line 460, it further includes: etching the second sub-dielectric layer 420 to form a plurality of second interconnect grooves 425 penetrating through the second sub-dielectric layer 420. The second interconnect grooves 425 extend along the first direction and are arranged in parallel in the second direction. In the second direction, the projections of the lower-layer sub-interconnect line 430 and the second interconnect grooves 425 on the substrate 300 are alternately arranged.

[0098] The second interconnect grooves 425 are used to provide a spatial position for forming the upper-layer sub-interconnect line 460.

[0099] In this embodiment, in the first direction, the second interconnect groove 425 exposes a part of the top surface of the underlying sub-interconnect line 430 and the first sub-dielectric layer 410 on the side of the corresponding underlying sub-interconnect line 430, so that the upper-layer sub-interconnect line 460 formed subsequently in the second interconnect groove 425 can be partially stacked with the underlying sub-interconnect line 230 and achieve electrical connection.

[0100] In this embodiment, for the underlying sub-interconnect lines 430, along the second direction, adjacent underlying sub-interconnect lines 430 are staggered in the first direction; correspondingly, in the first direction, adjacent second interconnect grooves 425 are isolated from each other, and along the second direction, adjacent second interconnect grooves 425 are staggered in the first direction.

[0101] In this embodiment, in the step of etching the second sub-dielectric layer 420, the top of the in-layer etch stop layer 490 is used as the etch stop position. There is an etch selectivity between the second sub-dielectric layer 420 and the in-layer etch stop layer 490. Therefore, using the top of the in-layer etch stop layer 490 as the etch stop position can reduce the probability of over-etching the underlying sub-interconnect line 230 or over-etching the first sub-dielectric layer 410 while ensuring the completion of the etching of the second sub-dielectric layer 420 in each region. Correspondingly, in the process of forming the second interconnect groove 425, after etching the second sub-dielectric layer 420, it further includes: etching the exposed in-layer etch stop layer 490.

[0102] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to etch the second sub-dielectric layer 420 and the etch stop layer 490 to form the second interconnect groove 425, thereby improving the sidewall topography quality and dimensional accuracy of the second interconnect groove 425.

[0103] It should be noted that in the process of forming the second interconnect groove 425, the etching process usually includes main etching and over-etching. Compared with the underlying sub-interconnect line 430, the first sub-dielectric layer 410 has a lower hardness. Therefore, the etching process is likely to cause a certain degree of over-etching to the first sub-dielectric layer 410 at the bottom of the second interconnect groove 425. Correspondingly, after the second interconnect groove 425 is formed, the top surface of the first sub-dielectric layer 410 exposed by the second interconnect groove 425 is lower than the top surface of the underlying sub-interconnect line 430.

[0104] Combined with reference Figure 12 , the step of forming the upper-layer sub-interconnect line 460 includes: filling a second interconnect material layer in the second interconnect groove 425 to form the upper-layer sub-interconnect line 460 located in the second interconnect groove 425.

[0105] Specifically, after filling the second interconnect material layer, the second interconnect material layer generally also covers the top of the second sub-dielectric layer 420. Therefore, the step of forming the upper sub-interconnect line 460 further includes: planarizing the second interconnect material layer (e.g., chemical mechanical polishing), and removing the second interconnect material layer above the top of the second sub-dielectric layer 420.

[0106] The material of the second interconnect material layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the second interconnect material layer is Cu.

[0107] In this embodiment, before filling the second interconnect material layer in the second interconnect trench 425, it further includes: forming a second diffusion barrier layer on the sidewalls and bottom of the second interconnect trench 425. It should be noted that during the process of forming the second diffusion barrier layer, the second diffusion barrier layer also extends to cover the top of the second sub-dielectric layer 420. Correspondingly, during the process of planarizing the second interconnect material layer, the second diffusion barrier layer located on the top of the second sub-dielectric layer 420 is also removed. For the specific description of the second diffusion barrier layer and its material, reference can be made to the corresponding description of the first diffusion barrier layer above, and details will not be elaborated here.

[0108] In this embodiment, after forming the lower sub-interconnect line 430, the second sub-dielectric layer 420 and the upper sub-interconnect line 460 located in the second sub-dielectric layer 420 are formed. Therefore, the process of forming the stacked first metal interconnect line 480 has less impact on the traditional back-end process and has high process compatibility.

[0109] Reference Figure 14 , a second dielectric layer 320 covering the first dielectric layer 400 and the upper sub-interconnect line 460 is formed. The second dielectric layer 320 is used to provide a process platform for subsequent formation of the second metal interconnect lines and the via interconnect structure, and is also used to achieve electrical isolation between the second metal interconnect lines and between the via interconnect structures.

[0110] The material of the second dielectric layer 320 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. In this embodiment, the material of the second dielectric layer 320 is silicon oxycarbide hydroxide. For the specific description of the second dielectric layer 320, reference can be made to the corresponding description of the first sub-dielectric layer 410 above, and details will not be elaborated here.

[0111] Combined with reference Figures 14 to 16 , Figure 14 is a cross-sectional view after forming the third interconnect trench 325 and the via 326, Figure 15 is a perspective view after forming the second metal interconnect lines and the via interconnect structure, Figure 16 is Figure 15Cross-sectional view along the a1a2 secant line, forming multiple second metal interconnect lines 310 in the second dielectric layer 320, and a via interconnect structure 440 at the bottom of the second metal interconnect lines 310. The second metal interconnect lines 310 extend along the second direction (as shown by the Y direction in Figure 16 ), and are arranged in parallel along the first direction (as shown by the X direction in Figure 16 ). The via interconnect structure 440 is connected to the top of the upper sub-interconnect line 460, and the via interconnect structure 440 extends in the longitudinal direction (as shown by the Z direction in Figure 16 ) into the second sub-dielectric layer 420 with a partial thickness, and covers the sidewalls of the upper sub-interconnect line 460 with a partial thickness in the longitudinal direction.

[0112] By making the via interconnect structure 440 cover the sidewalls of the upper sub-interconnect line 460 with a partial thickness in the longitudinal direction, the contact area between the via interconnect structure 440 and the upper sub-interconnect line 460 is increased, thereby reducing the contact resistance between the via interconnect structure 440 and the upper sub-interconnect line 460. In addition, the positional arrangement of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 also provides more spatial positions for increasing the size of the via interconnect structure 440 along the second direction. For example, when there is enough space on the side of the upper sub-interconnect line 460 in the second direction, it is easy to reduce the resistance of the via interconnect structure 440 itself by increasing the size of the via interconnect structure 440 along the second direction, which correspondingly also helps to increase the contact area between the via interconnect structure 440 and the second metal interconnect line 310 to reduce the contact resistance between the via interconnect structure 440 and the first metal interconnect line 310. In summary, in this embodiment, the lower sub-interconnect line 430 and the upper sub-interconnect line 460 with a stacked structure form the first metal interconnect line 480 of the same layer, and the projections of the lower sub-interconnect line 430 and the upper sub-interconnect line 460 on the substrate 300 are alternately arranged, and the via interconnect structure 440 covers the sidewalls of the upper sub-interconnect line 460 with a partial thickness in the longitudinal direction, thereby facilitating the reduction of the RC delay in the subsequent process.

[0113] Moreover, the reduction of the contact resistance between the via interconnect structure 440 and the upper sub-interconnect line 460 is also beneficial to improving the stress migration problem at the position of the via interconnect structure 440, and correspondingly improving the performance of the semiconductor structure.

[0114] In addition, the via interconnect structure 440 is connected to the top of the upper sub-interconnect line 460, thereby increasing the process window for forming the via interconnect structure 440. During the process of forming the via interconnect structure 440, it is beneficial to reduce the requirement for the alignment accuracy of the lithography process. That is to say, it is beneficial to reduce the probability that the via interconnect structure 440 cannot be connected to the upper sub-interconnect line 460 due to alignment deviation, thereby ensuring the electrical connection between the via interconnect structure 440 and the upper sub-interconnect line 460.

[0115] In this embodiment, according to the actual situation (for example, the dimension of the via interconnect structure 240 in the second direction), while ensuring an increase in the contact area between the via interconnect structure 440 and the upper sub-interconnect line 460, the via interconnect structure 440 can cover the entire top of the upper sub-interconnect line 460 in the second direction, or can cover a part of the top of the upper sub-interconnect line 460. For example, as Figure 17 shown, the situation where the via interconnect structure 440 covers a part of the top of the upper sub-interconnect line 460 in the second direction is illustrated. In some other embodiments, when the dimension of the via interconnect structure in the second direction is large, the via interconnect structure not only covers the sidewalls of the upper sub-interconnect line with a part of the thickness in the longitudinal direction, but also covers the entire top of the upper sub-interconnect line in the second direction, thereby further increasing the contact area between the via interconnect structure and the upper sub-interconnect line.

[0116] With reference to Figure 15 , before forming the second metal interconnect line 310 and the via interconnect structure 440, it further includes: etching the second dielectric layer 320 and a part of the thickness of the second sub-dielectric layer 420 to form a third interconnect groove 325 in a part of the thickness of the second dielectric layer 320, forming a via 326 in the remaining thickness of the second dielectric layer 320 and a part of the thickness of the second sub-dielectric layer 420, the bottom of the third interconnect groove 325 is connected to the top of the via 326, the third interconnect groove 325 extends in the second direction and is arranged in parallel in the first direction, the via 326 exposes the top of the upper sub-interconnect line 460, and exposes a part of the sidewall of the upper sub-interconnect line 460 with a part of the thickness in the longitudinal direction.

[0117] The third interconnect groove 325 is used to provide a spatial position for forming the second metal interconnect line 310, and the via 326 is used to provide a spatial position for forming the via interconnect structure 440. In this embodiment, the third interconnect groove 325 and the via 326 can be formed by an all in one etch (AIO etch) method, or the via 326 can be formed after forming the third interconnect groove 325; or the third interconnect groove 325 can be formed after forming the via 326. Specifically, a dry etching process (for example, an anisotropic dry etching process) is used to etch the second dielectric layer 320 and a part of the thickness of the second sub-dielectric layer 420, thereby improving the sidewall topography quality and dimensional accuracy of the third interconnect groove 325 and the via 326.

[0118] Compared with the traditional back-end manufacturing process, in this embodiment, during the process of forming the third interconnect groove 325 and the via 326, a part of the thickness of the second sub-dielectric layer 420 is also etched. Therefore, the process of forming the via 326 has little impact on the current back-end manufacturing process, and the process compatibility is relatively high.

[0119] In this embodiment, the thickness of the upper sub-interconnect line 460 is defined as a first thickness (not labeled), and the thickness of the upper sub-interconnect line 460 exposed by the through hole 326 is a third thickness D1 (as Figure 15 shown). Then, the ratio of the third thickness D1 to the first thickness should not be too small or too large. If the ratio of the third thickness D1 to the first thickness is too small, the effect of increasing the contact area between the through-hole interconnect structure 440 and the upper sub-interconnect line 460 is not good, and it is difficult to effectively reduce the RC delay in the back-end process; if the ratio of the third thickness D1 to the first thickness is too large, the probability that the through hole 326 exposes the lower sub-interconnect line 430 on the side of the upper sub-interconnect line 460 becomes higher, thus having an adverse effect on the performance of the semiconductor structure. Therefore, in this embodiment, the ratio of the third thickness D1 to the first thickness is 5% to 80%.

[0120] In this embodiment, in the second direction, the width of the upper sub-interconnect line 460 is defined as a first width (not labeled), and the width of the upper sub-interconnect line 460 exposed by the through hole 326 is a third width W1 (as Figure 15 shown). The ratio of the third width W1 to the first width should not be too small. If the ratio of the third width W1 to the first width is too small, affected by alignment deviation or the dimensional accuracy of the through hole 325, the probability that the through hole 326 cannot expose the sidewall and top of the upper sub-interconnect line 460 is likely to increase. Therefore, in this embodiment, the ratio of the third width W1 to the first width is 20% to 100%. Among them, when the ratio of the third width W1 to the first width is 100%, it means that the through hole 326 exposes the entire top of the upper sub-interconnect line 460 in the second direction.

[0121] With reference to Figure 17 , the steps of forming the second metal interconnect line 310 and the through-hole interconnect structure 440 include: filling a third interconnect material layer in the third interconnect groove 325 and the through hole 326 to form the second metal interconnect line 310 located in the third interconnect groove 325 and the through-hole interconnect structure 440 located in the through hole 326.

[0122] Specifically, after filling the third interconnect material layer, the third interconnect material layer usually also covers the top of the second dielectric layer 320. Therefore, the steps of forming the second metal interconnect line 310 and the through-hole interconnect structure 440 further include: performing a planarization process (e.g., chemical mechanical polishing process) on the third interconnect material layer to remove the third interconnect material layer higher than the top of the second dielectric layer 320. The material of the third interconnect material layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the third interconnect material layer is Cu.

[0123] In this embodiment, before filling the third interconnect material layer in the third interconnect trench 325 and the via 326, the following steps are further included: forming a third diffusion barrier layer on the sidewalls and bottom of the second interconnect trench 425, as well as on the sidewalls and bottom of the via 326. It should be noted that during the process of forming the third diffusion barrier layer, the third diffusion barrier layer also extends to cover the top of the second dielectric layer 320. Correspondingly, during the process of planarizing the third interconnect material layer, the third diffusion barrier layer located on the top of the second dielectric layer 320 is also removed. For the specific description of the third diffusion barrier layer and its materials, reference can be made to the corresponding description of the first diffusion barrier layer above, which will not be elaborated here.

[0124] Correspondingly, in this embodiment, the thickness of the upper sub-interconnect line 460 is defined as the first thickness (not labeled), the thickness of the upper sub-interconnect line 460 covered by the via interconnect structure 440 is defined as the second thickness (not labeled), and the ratio of the second thickness to the first thickness is 5% to 80%. In this embodiment, in the second direction, the width of the upper sub-interconnect line 460 is defined as the first width (not labeled), the width of the upper sub-interconnect line 460 covered by the via interconnect structure 440 is defined as the second width (not labeled), and the ratio of the second width to the first width is 20% to 100%.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the surface normal direction of the substrate being longitudinal; A first dielectric layer, located on the substrate; Multiple first metal interconnect lines, located in the first dielectric layer. The first metal interconnect lines include a lower sub-interconnect line and an upper sub-interconnect line connected to each other. The lower sub-interconnect line is located in a partial thickness of the first dielectric layer, and the upper sub-interconnect line is located in the remaining thickness of the first dielectric layer above the lower sub-interconnect line. Both the lower sub-interconnect line and the upper sub-interconnect line extend along a first direction and are arranged in parallel along a second direction. The upper sub-interconnect line is connected to the adjacent lower sub-interconnect line along the first direction. The first direction is perpendicular to the second direction. In the second direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged; A second dielectric layer, located on the top of the first dielectric layer and the upper sub-interconnect line; Multiple second metal interconnect lines, located in a partial thickness of the second dielectric layer and spaced from the first metal interconnect lines in the longitudinal direction. The second metal interconnect lines extend along the second direction and are arranged in parallel along the first direction; A via interconnect structure, located in the remaining thickness of the second dielectric layer at the bottom of the second metal interconnect line and a partial thickness of the first dielectric layer. The via interconnect structure is connected to the top of the upper sub-interconnect line and covers the sidewalls of a partial thickness of the upper sub-interconnect line in the longitudinal direction.

2. The semiconductor structure according to claim 1, wherein The via interconnect structure covers the entire top or a part of the top of the upper sub-interconnect line along the second direction.

3. The semiconductor structure according to claim 1, characterized in that, In the first direction, adjacent lower sub-interconnect lines are isolated from each other, and adjacent upper sub-interconnect lines are isolated from each other; Wherein, the upper sub-interconnect line further extends along the first direction to the partial top of an adjacent lower sub-interconnect line on either side and is connected to the corresponding lower sub-interconnect line, or the upper sub-interconnect line further extends along the first direction to the partial top of adjacent lower sub-interconnect lines on both sides and is connected to the corresponding lower sub-interconnect lines, or in the first direction, the projections of the lower sub-interconnect line and the upper sub-interconnect line on the substrate are alternately arranged.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The bottom surface of the upper sub-interconnect line on the side of the lower sub-interconnect line is lower than the top surface of the lower sub-interconnect line.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The first dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer located on the top of the first sub-dielectric layer; The lower sub-interconnect line is located in the first sub-dielectric layer, and the upper sub-interconnect line is located in the second sub-dielectric layer.

6. The semiconductor structure according to claim 5, wherein The semiconductor structure further includes: an in-layer etch stop layer, located between the top of the lower sub-interconnect line exposed by the upper sub-interconnect line and the bottom of the second sub-dielectric layer, and between the top of the first sub-dielectric layer exposed by the upper sub-interconnect line and the bottom of the second sub-dielectric layer.

7. The semiconductor structure according to claim 6, wherein The material of the in-layer etch stop layer includes one or more of SiCN, SiCO, SiN, Al2O3, and AlN.

8. The semiconductor structure according to claim 1, wherein In the longitudinal direction, the thickness of the upper sub-interconnect line is a first thickness; The thickness of the upper sub-interconnecting line covered by the via interconnect structure is a second thickness, and the ratio of the second thickness to the first thickness is 5% to 80%.

9. The semiconductor structure according to claim 1 or 2, wherein In the second direction, the width of the upper sub-interconnecting line is a first width; The width of the upper sub-interconnecting line covered by the via interconnect structure is a second width, and the ratio of the second width to the first width is 20% to 100%.

10. The semiconductor structure according to claim 1, characterized in that, The material of the first metal interconnecting line includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the material of the second metal interconnecting line includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the material of the via interconnect structure includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

11. The semiconductor structure according to claim 1, wherein, The material of the first dielectric layer includes one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG; the material of the second dielectric layer includes one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG.

12. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the normal direction of the surface of the substrate being longitudinal; Forming a first sub-dielectric layer on the substrate; Forming a plurality of lower sub-interconnecting lines in the first sub-dielectric layer, the lower sub-interconnecting lines extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; Forming a second sub-dielectric layer covering the lower sub-interconnecting lines and the first sub-dielectric layer, the second sub-dielectric layer and the first sub-dielectric layer constituting a first dielectric layer; Forming a plurality of upper sub-interconnecting lines in the second sub-dielectric layer, the upper sub-interconnecting lines extending along the first direction and arranged in parallel along the second direction. In the second direction, the projections of the lower sub-interconnecting lines and the upper sub-interconnecting lines on the substrate are alternately arranged, and the upper sub-interconnecting lines are connected to adjacent lower sub-interconnecting lines along the first direction, and the connected lower sub-interconnecting lines and upper sub-interconnecting lines constitute a first metal interconnecting line; Forming a second dielectric layer covering the first dielectric layer and the upper sub-interconnecting lines; Forming a plurality of second metal interconnecting lines and via interconnect structures located at the bottoms of the second metal interconnecting lines in the second dielectric layer, the second metal interconnecting lines extending along the second direction and arranged in parallel along the first direction, the via interconnect structures being connected to the tops of the upper sub-interconnecting lines, and the via interconnect structures extending longitudinally into the second sub-dielectric layer with a partial thickness and covering the sidewalls of the upper sub-interconnecting lines with a partial thickness in the longitudinal direction.

13. The method for forming the semiconductor structure according to claim 12, wherein, In the step of forming the via interconnect structure, the via interconnect structure covers the entire top or a partial top of the upper sub-interconnecting line along the second direction.

14. The method for forming the semiconductor structure according to claim 12, wherein In the step of forming a plurality of lower sub-interconnect lines in the first sub-dielectric layer, in the first direction, adjacent lower sub-interconnect lines are isolated from each other; In the step of forming a plurality of upper sub-interconnect lines in the second sub-dielectric layer, adjacent upper sub-interconnect lines are isolated from each other; wherein, in the first direction, the upper sub-interconnect lines further extend in any one side in the first direction to the top of a part of the adjacent lower sub-interconnect lines and are connected to the corresponding lower sub-interconnect lines, or the upper sub-interconnect lines further extend in both sides in the first direction to the top of a part of the adjacent lower sub-interconnect lines and are connected to the corresponding lower sub-interconnect lines, or the projections of the lower sub-interconnect lines and the upper sub-interconnect lines on the substrate are alternately arranged.

15. The method for forming the semiconductor structure according to claim 12, characterized in that, Before forming a plurality of lower sub-interconnect lines in the first sub-dielectric layer, it further includes: etching the first sub-dielectric layer to form a plurality of first interconnect grooves in the first sub-dielectric layer, the first interconnect grooves extending in the first direction and arranged in parallel in the second direction; The step of forming a plurality of lower sub-interconnect lines in the first sub-dielectric layer includes: filling a first interconnect material layer in the first interconnect grooves to form lower sub-interconnect lines located in the first interconnect grooves.

16. The method for forming a semiconductor structure according to claim 12, wherein, Before forming a plurality of upper sub-interconnect lines in the second sub-dielectric layer, it further includes: etching the second sub-dielectric layer to form a plurality of second interconnect grooves in the second sub-dielectric layer, the second interconnect grooves extending in the first direction and arranged in parallel in the second direction, in the second direction, the projections of the lower sub-interconnect lines and the second interconnect grooves on the substrate are alternately arranged; The step of forming a plurality of upper sub-interconnect lines in the second sub-dielectric layer includes: filling a second interconnect material layer in the second interconnect grooves to form upper sub-interconnect lines located in the second interconnect grooves.

17. The method for forming the semiconductor structure according to claim 12, wherein, Before forming a plurality of second metal interconnect lines in the second dielectric layer and via interconnect structures located at the bottom of the second metal interconnect lines, it further includes: etching the second dielectric layer and a part of the thickness of the second sub-dielectric layer to form third interconnect grooves in a part of the thickness of the second sub-dielectric layer, forming vias in the remaining thickness of the second dielectric layer and a part of the thickness of the second sub-dielectric layer, the bottom of the third interconnect grooves is communicated with the top of the vias, the third interconnect grooves extend in the second direction and are arranged in parallel in the first direction, the vias expose the top of the upper sub-interconnect lines and expose the side walls of a part of the thickness of the upper sub-interconnect lines in the longitudinal direction; The step of forming a plurality of second metal interconnect lines in the second dielectric layer and via interconnect structures located at the bottom of the second metal interconnect lines includes: filling a third interconnect material layer in the third interconnect grooves and the vias to form second metal interconnect lines located in the third interconnect grooves and via interconnect structures located in the vias.

18. The method for forming a semiconductor structure according to claim 16, wherein, After forming a plurality of lower sub-interconnect lines in the first sub-dielectric layer and before forming a second sub-dielectric layer covering the lower sub-interconnect lines and the first sub-dielectric layer, the forming method further includes: forming an in-layer etch stop layer covering the top of the lower sub-interconnect lines and the top of the first sub-dielectric layer; In the step of etching the second sub-dielectric layer, the top of the in-layer etch stop layer is used as an etch stop position; In the process of forming the second interconnect groove, it further includes: after etching the second sub-dielectric layer, etching the exposed in-layer etch stop layer.

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